xref: /linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/priv.h (revision 6fdcba32711044c35c0e1b094cbd8f3f0b4472c9)
1 /* SPDX-License-Identifier: MIT */
2 #ifndef __NVKM_GR_PRIV_H__
3 #define __NVKM_GR_PRIV_H__
4 #define nvkm_gr(p) container_of((p), struct nvkm_gr, engine)
5 #include <engine/gr.h>
6 #include <core/enum.h>
7 struct nvkm_fb_tile;
8 struct nvkm_fifo_chan;
9 
10 int nvkm_gr_ctor(const struct nvkm_gr_func *, struct nvkm_device *,
11 		 int index, bool enable, struct nvkm_gr *);
12 
13 bool nv04_gr_idle(struct nvkm_gr *);
14 
15 struct nvkm_gr_func {
16 	void *(*dtor)(struct nvkm_gr *);
17 	int (*oneinit)(struct nvkm_gr *);
18 	int (*init)(struct nvkm_gr *);
19 	int (*fini)(struct nvkm_gr *, bool);
20 	void (*intr)(struct nvkm_gr *);
21 	void (*tile)(struct nvkm_gr *, int region, struct nvkm_fb_tile *);
22 	int (*tlb_flush)(struct nvkm_gr *);
23 	int (*chan_new)(struct nvkm_gr *, struct nvkm_fifo_chan *,
24 			const struct nvkm_oclass *, struct nvkm_object **);
25 	int (*object_get)(struct nvkm_gr *, int, struct nvkm_sclass *);
26 	/* Returns chipset-specific counts of units packed into an u64.
27 	 */
28 	u64 (*units)(struct nvkm_gr *);
29 	bool (*chsw_load)(struct nvkm_gr *);
30 	struct {
31 		int (*pause)(struct nvkm_gr *);
32 		int (*resume)(struct nvkm_gr *);
33 		u32 (*inst)(struct nvkm_gr *);
34 	} ctxsw;
35 	struct nvkm_sclass sclass[];
36 };
37 
38 extern const struct nvkm_bitfield nv04_gr_nsource[];
39 extern const struct nvkm_object_func nv04_gr_object;
40 
41 extern const struct nvkm_bitfield nv10_gr_intr_name[];
42 extern const struct nvkm_bitfield nv10_gr_nstatus[];
43 
44 extern const struct nvkm_enum nv50_data_error_names[];
45 #endif
46