1b7019ac5SIlia Mirkin /* SPDX-License-Identifier: MIT */
2b8bf04e1SBen Skeggs #ifndef __NV40_GR_H__
3b8bf04e1SBen Skeggs #define __NV40_GR_H__
427f3d6cfSBen Skeggs #define nv40_gr(p) container_of((p), struct nv40_gr, base)
527f3d6cfSBen Skeggs #include "priv.h"
69719047bSBen Skeggs
727f3d6cfSBen Skeggs struct nv40_gr {
827f3d6cfSBen Skeggs struct nvkm_gr base;
927f3d6cfSBen Skeggs u32 size;
1027f3d6cfSBen Skeggs struct list_head chan;
1127f3d6cfSBen Skeggs };
1227f3d6cfSBen Skeggs
13864d37c3SBen Skeggs int nv40_gr_new_(const struct nvkm_gr_func *, struct nvkm_device *, enum nvkm_subdev_type, int,
14c85ee6caSBen Skeggs struct nvkm_gr **);
15c85ee6caSBen Skeggs int nv40_gr_init(struct nvkm_gr *);
16c85ee6caSBen Skeggs void nv40_gr_intr(struct nvkm_gr *);
17c85ee6caSBen Skeggs u64 nv40_gr_units(struct nvkm_gr *);
18c85ee6caSBen Skeggs
1927f3d6cfSBen Skeggs #define nv40_gr_chan(p) container_of((p), struct nv40_gr_chan, object)
204246b92cSBen Skeggs #include <core/object.h>
2127f3d6cfSBen Skeggs
2227f3d6cfSBen Skeggs struct nv40_gr_chan {
2327f3d6cfSBen Skeggs struct nvkm_object object;
2427f3d6cfSBen Skeggs struct nv40_gr *gr;
25*c546656fSBen Skeggs struct nvkm_chan *fifo;
2627f3d6cfSBen Skeggs u32 inst;
2727f3d6cfSBen Skeggs struct list_head head;
2827f3d6cfSBen Skeggs };
29b8bf04e1SBen Skeggs
30*c546656fSBen Skeggs int nv40_gr_chan_new(struct nvkm_gr *, struct nvkm_chan *,
31c85ee6caSBen Skeggs const struct nvkm_oclass *, struct nvkm_object **);
32c85ee6caSBen Skeggs
33c85ee6caSBen Skeggs extern const struct nvkm_object_func nv40_gr_object;
34c85ee6caSBen Skeggs
35b8bf04e1SBen Skeggs /* returns 1 if device is one of the nv4x using the 0x4497 object class,
36b8bf04e1SBen Skeggs * helpful to determine a number of other hardware features
37b8bf04e1SBen Skeggs */
38b8bf04e1SBen Skeggs static inline int
nv44_gr_class(struct nvkm_device * device)39b7a2bc18SBen Skeggs nv44_gr_class(struct nvkm_device *device)
40b8bf04e1SBen Skeggs {
41b8bf04e1SBen Skeggs if ((device->chipset & 0xf0) == 0x60)
42b8bf04e1SBen Skeggs return 1;
43b8bf04e1SBen Skeggs
44c85ee6caSBen Skeggs return !(0x0aaf & (1 << (device->chipset & 0x0f)));
45b8bf04e1SBen Skeggs }
46b8bf04e1SBen Skeggs
47e3c71eb2SBen Skeggs int nv40_grctx_init(struct nvkm_device *, u32 *size);
48e3c71eb2SBen Skeggs void nv40_grctx_fill(struct nvkm_device *, struct nvkm_gpuobj *);
49b8bf04e1SBen Skeggs #endif
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