1 #include "nv20.h" 2 #include "regs.h" 3 4 #include <core/client.h> 5 #include <core/handle.h> 6 #include <engine/fifo.h> 7 #include <subdev/fb.h> 8 #include <subdev/timer.h> 9 10 /******************************************************************************* 11 * Graphics object classes 12 ******************************************************************************/ 13 14 static struct nvkm_oclass 15 nv20_gr_sclass[] = { 16 { 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */ 17 { 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */ 18 { 0x0030, &nv04_gr_ofuncs, NULL }, /* null */ 19 { 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */ 20 { 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */ 21 { 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */ 22 { 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */ 23 { 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */ 24 { 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */ 25 { 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */ 26 { 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */ 27 { 0x0096, &nv04_gr_ofuncs, NULL }, /* celcius */ 28 { 0x0097, &nv04_gr_ofuncs, NULL }, /* kelvin */ 29 { 0x009e, &nv04_gr_ofuncs, NULL }, /* swzsurf */ 30 { 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */ 31 {}, 32 }; 33 34 /******************************************************************************* 35 * PGRAPH context 36 ******************************************************************************/ 37 38 static int 39 nv20_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 40 struct nvkm_oclass *oclass, void *data, u32 size, 41 struct nvkm_object **pobject) 42 { 43 struct nv20_gr_chan *chan; 44 struct nvkm_gpuobj *image; 45 int ret, i; 46 47 ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x37f0, 48 16, NVOBJ_FLAG_ZERO_ALLOC, &chan); 49 *pobject = nv_object(chan); 50 if (ret) 51 return ret; 52 53 chan->chid = nvkm_fifo_chan(parent)->chid; 54 image = &chan->base.base.gpuobj; 55 56 nvkm_kmap(image); 57 nvkm_wo32(image, 0x0000, 0x00000001 | (chan->chid << 24)); 58 nvkm_wo32(image, 0x033c, 0xffff0000); 59 nvkm_wo32(image, 0x03a0, 0x0fff0000); 60 nvkm_wo32(image, 0x03a4, 0x0fff0000); 61 nvkm_wo32(image, 0x047c, 0x00000101); 62 nvkm_wo32(image, 0x0490, 0x00000111); 63 nvkm_wo32(image, 0x04a8, 0x44400000); 64 for (i = 0x04d4; i <= 0x04e0; i += 4) 65 nvkm_wo32(image, i, 0x00030303); 66 for (i = 0x04f4; i <= 0x0500; i += 4) 67 nvkm_wo32(image, i, 0x00080000); 68 for (i = 0x050c; i <= 0x0518; i += 4) 69 nvkm_wo32(image, i, 0x01012000); 70 for (i = 0x051c; i <= 0x0528; i += 4) 71 nvkm_wo32(image, i, 0x000105b8); 72 for (i = 0x052c; i <= 0x0538; i += 4) 73 nvkm_wo32(image, i, 0x00080008); 74 for (i = 0x055c; i <= 0x0598; i += 4) 75 nvkm_wo32(image, i, 0x07ff0000); 76 nvkm_wo32(image, 0x05a4, 0x4b7fffff); 77 nvkm_wo32(image, 0x05fc, 0x00000001); 78 nvkm_wo32(image, 0x0604, 0x00004000); 79 nvkm_wo32(image, 0x0610, 0x00000001); 80 nvkm_wo32(image, 0x0618, 0x00040000); 81 nvkm_wo32(image, 0x061c, 0x00010000); 82 for (i = 0x1c1c; i <= 0x248c; i += 16) { 83 nvkm_wo32(image, (i + 0), 0x10700ff9); 84 nvkm_wo32(image, (i + 4), 0x0436086c); 85 nvkm_wo32(image, (i + 8), 0x000c001b); 86 } 87 nvkm_wo32(image, 0x281c, 0x3f800000); 88 nvkm_wo32(image, 0x2830, 0x3f800000); 89 nvkm_wo32(image, 0x285c, 0x40000000); 90 nvkm_wo32(image, 0x2860, 0x3f800000); 91 nvkm_wo32(image, 0x2864, 0x3f000000); 92 nvkm_wo32(image, 0x286c, 0x40000000); 93 nvkm_wo32(image, 0x2870, 0x3f800000); 94 nvkm_wo32(image, 0x2878, 0xbf800000); 95 nvkm_wo32(image, 0x2880, 0xbf800000); 96 nvkm_wo32(image, 0x34a4, 0x000fe000); 97 nvkm_wo32(image, 0x3530, 0x000003f8); 98 nvkm_wo32(image, 0x3540, 0x002fe000); 99 for (i = 0x355c; i <= 0x3578; i += 4) 100 nvkm_wo32(image, i, 0x001c527c); 101 nvkm_done(image); 102 return 0; 103 } 104 105 int 106 nv20_gr_context_init(struct nvkm_object *object) 107 { 108 struct nv20_gr *gr = (void *)object->engine; 109 struct nv20_gr_chan *chan = (void *)object; 110 int ret; 111 112 ret = nvkm_gr_context_init(&chan->base); 113 if (ret) 114 return ret; 115 116 nvkm_kmap(gr->ctxtab); 117 nvkm_wo32(gr->ctxtab, chan->chid * 4, nv_gpuobj(chan)->addr >> 4); 118 nvkm_done(gr->ctxtab); 119 return 0; 120 } 121 122 int 123 nv20_gr_context_fini(struct nvkm_object *object, bool suspend) 124 { 125 struct nv20_gr *gr = (void *)object->engine; 126 struct nv20_gr_chan *chan = (void *)object; 127 struct nvkm_device *device = gr->base.engine.subdev.device; 128 int chid = -1; 129 130 nvkm_mask(device, 0x400720, 0x00000001, 0x00000000); 131 if (nvkm_rd32(device, 0x400144) & 0x00010000) 132 chid = (nvkm_rd32(device, 0x400148) & 0x1f000000) >> 24; 133 if (chan->chid == chid) { 134 nvkm_wr32(device, 0x400784, nv_gpuobj(chan)->addr >> 4); 135 nvkm_wr32(device, 0x400788, 0x00000002); 136 nvkm_msec(device, 2000, 137 if (!nvkm_rd32(device, 0x400700)) 138 break; 139 ); 140 nvkm_wr32(device, 0x400144, 0x10000000); 141 nvkm_mask(device, 0x400148, 0xff000000, 0x1f000000); 142 } 143 nvkm_mask(device, 0x400720, 0x00000001, 0x00000001); 144 145 nvkm_kmap(gr->ctxtab); 146 nvkm_wo32(gr->ctxtab, chan->chid * 4, 0x00000000); 147 nvkm_done(gr->ctxtab); 148 return nvkm_gr_context_fini(&chan->base, suspend); 149 } 150 151 static struct nvkm_oclass 152 nv20_gr_cclass = { 153 .handle = NV_ENGCTX(GR, 0x20), 154 .ofuncs = &(struct nvkm_ofuncs) { 155 .ctor = nv20_gr_context_ctor, 156 .dtor = _nvkm_gr_context_dtor, 157 .init = nv20_gr_context_init, 158 .fini = nv20_gr_context_fini, 159 .rd32 = _nvkm_gr_context_rd32, 160 .wr32 = _nvkm_gr_context_wr32, 161 }, 162 }; 163 164 /******************************************************************************* 165 * PGRAPH engine/subdev functions 166 ******************************************************************************/ 167 168 void 169 nv20_gr_tile_prog(struct nvkm_engine *engine, int i) 170 { 171 struct nv20_gr *gr = (void *)engine; 172 struct nvkm_device *device = gr->base.engine.subdev.device; 173 struct nvkm_fifo *fifo = device->fifo; 174 struct nvkm_fb_tile *tile = &device->fb->tile.region[i]; 175 unsigned long flags; 176 177 fifo->pause(fifo, &flags); 178 nv04_gr_idle(gr); 179 180 nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit); 181 nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); 182 nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr); 183 184 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i); 185 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->limit); 186 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i); 187 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->pitch); 188 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i); 189 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->addr); 190 191 if (nv_device(engine)->chipset != 0x34) { 192 nvkm_wr32(device, NV20_PGRAPH_ZCOMP(i), tile->zcomp); 193 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00ea0090 + 4 * i); 194 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->zcomp); 195 } 196 197 fifo->start(fifo, &flags); 198 } 199 200 void 201 nv20_gr_intr(struct nvkm_subdev *subdev) 202 { 203 struct nvkm_engine *engine = nv_engine(subdev); 204 struct nvkm_object *engctx; 205 struct nvkm_handle *handle; 206 struct nv20_gr *gr = (void *)subdev; 207 struct nvkm_device *device = gr->base.engine.subdev.device; 208 u32 stat = nvkm_rd32(device, NV03_PGRAPH_INTR); 209 u32 nsource = nvkm_rd32(device, NV03_PGRAPH_NSOURCE); 210 u32 nstatus = nvkm_rd32(device, NV03_PGRAPH_NSTATUS); 211 u32 addr = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR); 212 u32 chid = (addr & 0x01f00000) >> 20; 213 u32 subc = (addr & 0x00070000) >> 16; 214 u32 mthd = (addr & 0x00001ffc); 215 u32 data = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_DATA); 216 u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xfff; 217 u32 show = stat; 218 char msg[128], src[128], sta[128]; 219 220 engctx = nvkm_engctx_get(engine, chid); 221 if (stat & NV_PGRAPH_INTR_ERROR) { 222 if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) { 223 handle = nvkm_handle_get_class(engctx, class); 224 if (handle && !nv_call(handle->object, mthd, data)) 225 show &= ~NV_PGRAPH_INTR_ERROR; 226 nvkm_handle_put(handle); 227 } 228 } 229 230 nvkm_wr32(device, NV03_PGRAPH_INTR, stat); 231 nvkm_wr32(device, NV04_PGRAPH_FIFO, 0x00000001); 232 233 if (show) { 234 nvkm_snprintbf(msg, sizeof(msg), nv10_gr_intr_name, show); 235 nvkm_snprintbf(src, sizeof(src), nv04_gr_nsource, nsource); 236 nvkm_snprintbf(sta, sizeof(sta), nv10_gr_nstatus, nstatus); 237 nvkm_error(subdev, "intr %08x [%s] nsource %08x [%s] " 238 "nstatus %08x [%s] ch %d [%s] subc %d " 239 "class %04x mthd %04x data %08x\n", 240 show, msg, nsource, src, nstatus, sta, chid, 241 nvkm_client_name(engctx), subc, class, mthd, data); 242 } 243 244 nvkm_engctx_put(engctx); 245 } 246 247 static int 248 nv20_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 249 struct nvkm_oclass *oclass, void *data, u32 size, 250 struct nvkm_object **pobject) 251 { 252 struct nv20_gr *gr; 253 int ret; 254 255 ret = nvkm_gr_create(parent, engine, oclass, true, &gr); 256 *pobject = nv_object(gr); 257 if (ret) 258 return ret; 259 260 ret = nvkm_gpuobj_new(nv_object(gr), NULL, 32 * 4, 16, 261 NVOBJ_FLAG_ZERO_ALLOC, &gr->ctxtab); 262 if (ret) 263 return ret; 264 265 nv_subdev(gr)->unit = 0x00001000; 266 nv_subdev(gr)->intr = nv20_gr_intr; 267 nv_engine(gr)->cclass = &nv20_gr_cclass; 268 nv_engine(gr)->sclass = nv20_gr_sclass; 269 nv_engine(gr)->tile_prog = nv20_gr_tile_prog; 270 return 0; 271 } 272 273 void 274 nv20_gr_dtor(struct nvkm_object *object) 275 { 276 struct nv20_gr *gr = (void *)object; 277 nvkm_gpuobj_ref(NULL, &gr->ctxtab); 278 nvkm_gr_destroy(&gr->base); 279 } 280 281 int 282 nv20_gr_init(struct nvkm_object *object) 283 { 284 struct nvkm_engine *engine = nv_engine(object); 285 struct nv20_gr *gr = (void *)engine; 286 struct nvkm_device *device = gr->base.engine.subdev.device; 287 struct nvkm_fb *fb = device->fb; 288 u32 tmp, vramsz; 289 int ret, i; 290 291 ret = nvkm_gr_init(&gr->base); 292 if (ret) 293 return ret; 294 295 nvkm_wr32(device, NV20_PGRAPH_CHANNEL_CTX_TABLE, gr->ctxtab->addr >> 4); 296 297 if (nv_device(gr)->chipset == 0x20) { 298 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x003d0000); 299 for (i = 0; i < 15; i++) 300 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, 0x00000000); 301 nvkm_msec(device, 2000, 302 if (!nvkm_rd32(device, 0x400700)) 303 break; 304 ); 305 } else { 306 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x02c80000); 307 for (i = 0; i < 32; i++) 308 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, 0x00000000); 309 nvkm_msec(device, 2000, 310 if (!nvkm_rd32(device, 0x400700)) 311 break; 312 ); 313 } 314 315 nvkm_wr32(device, NV03_PGRAPH_INTR , 0xFFFFFFFF); 316 nvkm_wr32(device, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); 317 318 nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); 319 nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x00000000); 320 nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x00118700); 321 nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xF3CE0475); /* 0x4 = auto ctx switch */ 322 nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x00000000); 323 nvkm_wr32(device, 0x40009C , 0x00000040); 324 325 if (nv_device(gr)->chipset >= 0x25) { 326 nvkm_wr32(device, 0x400890, 0x00a8cfff); 327 nvkm_wr32(device, 0x400610, 0x304B1FB6); 328 nvkm_wr32(device, 0x400B80, 0x1cbd3883); 329 nvkm_wr32(device, 0x400B84, 0x44000000); 330 nvkm_wr32(device, 0x400098, 0x40000080); 331 nvkm_wr32(device, 0x400B88, 0x000000ff); 332 333 } else { 334 nvkm_wr32(device, 0x400880, 0x0008c7df); 335 nvkm_wr32(device, 0x400094, 0x00000005); 336 nvkm_wr32(device, 0x400B80, 0x45eae20e); 337 nvkm_wr32(device, 0x400B84, 0x24000000); 338 nvkm_wr32(device, 0x400098, 0x00000040); 339 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00E00038); 340 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000030); 341 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00E10038); 342 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000030); 343 } 344 345 /* Turn all the tiling regions off. */ 346 for (i = 0; i < fb->tile.regions; i++) 347 engine->tile_prog(engine, i); 348 349 nvkm_wr32(device, 0x4009a0, nvkm_rd32(device, 0x100324)); 350 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA000C); 351 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, nvkm_rd32(device, 0x100324)); 352 353 nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10000100); 354 nvkm_wr32(device, NV10_PGRAPH_STATE , 0xFFFFFFFF); 355 356 tmp = nvkm_rd32(device, NV10_PGRAPH_SURFACE) & 0x0007ff00; 357 nvkm_wr32(device, NV10_PGRAPH_SURFACE, tmp); 358 tmp = nvkm_rd32(device, NV10_PGRAPH_SURFACE) | 0x00020100; 359 nvkm_wr32(device, NV10_PGRAPH_SURFACE, tmp); 360 361 /* begin RAM config */ 362 vramsz = nv_device_resource_len(nv_device(gr), 1) - 1; 363 nvkm_wr32(device, 0x4009A4, nvkm_rd32(device, 0x100200)); 364 nvkm_wr32(device, 0x4009A8, nvkm_rd32(device, 0x100204)); 365 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0000); 366 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , nvkm_rd32(device, 0x100200)); 367 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0004); 368 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , nvkm_rd32(device, 0x100204)); 369 nvkm_wr32(device, 0x400820, 0); 370 nvkm_wr32(device, 0x400824, 0); 371 nvkm_wr32(device, 0x400864, vramsz - 1); 372 nvkm_wr32(device, 0x400868, vramsz - 1); 373 374 /* interesting.. the below overwrites some of the tile setup above.. */ 375 nvkm_wr32(device, 0x400B20, 0x00000000); 376 nvkm_wr32(device, 0x400B04, 0xFFFFFFFF); 377 378 nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_XMIN, 0); 379 nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_YMIN, 0); 380 nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff); 381 nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff); 382 return 0; 383 } 384 385 struct nvkm_oclass 386 nv20_gr_oclass = { 387 .handle = NV_ENGINE(GR, 0x20), 388 .ofuncs = &(struct nvkm_ofuncs) { 389 .ctor = nv20_gr_ctor, 390 .dtor = nv20_gr_dtor, 391 .init = nv20_gr_init, 392 .fini = _nvkm_gr_fini, 393 }, 394 }; 395