1 /* 2 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20 * DEALINGS IN THE SOFTWARE. 21 */ 22 #include "gf100.h" 23 #include "ctxgf100.h" 24 25 #include <core/firmware.h> 26 #include <subdev/acr.h> 27 #include <subdev/timer.h> 28 29 #include <nvfw/flcn.h> 30 31 #include <nvif/class.h> 32 33 void 34 gm20b_gr_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust) 35 { 36 struct flcn_bl_dmem_desc hdr; 37 u64 addr; 38 39 nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr)); 40 addr = ((u64)hdr.code_dma_base1 << 40 | hdr.code_dma_base << 8); 41 hdr.code_dma_base = lower_32_bits((addr + adjust) >> 8); 42 hdr.code_dma_base1 = upper_32_bits((addr + adjust) >> 8); 43 addr = ((u64)hdr.data_dma_base1 << 40 | hdr.data_dma_base << 8); 44 hdr.data_dma_base = lower_32_bits((addr + adjust) >> 8); 45 hdr.data_dma_base1 = upper_32_bits((addr + adjust) >> 8); 46 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr)); 47 48 flcn_bl_dmem_desc_dump(&acr->subdev, &hdr); 49 } 50 51 void 52 gm20b_gr_acr_bld_write(struct nvkm_acr *acr, u32 bld, 53 struct nvkm_acr_lsfw *lsfw) 54 { 55 const u64 base = lsfw->offset.img + lsfw->app_start_offset; 56 const u64 code = (base + lsfw->app_resident_code_offset) >> 8; 57 const u64 data = (base + lsfw->app_resident_data_offset) >> 8; 58 const struct flcn_bl_dmem_desc hdr = { 59 .ctx_dma = FALCON_DMAIDX_UCODE, 60 .code_dma_base = lower_32_bits(code), 61 .non_sec_code_off = lsfw->app_resident_code_offset, 62 .non_sec_code_size = lsfw->app_resident_code_size, 63 .code_entry_point = lsfw->app_imem_entry, 64 .data_dma_base = lower_32_bits(data), 65 .data_size = lsfw->app_resident_data_size, 66 .code_dma_base1 = upper_32_bits(code), 67 .data_dma_base1 = upper_32_bits(data), 68 }; 69 70 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr)); 71 } 72 73 const struct nvkm_acr_lsf_func 74 gm20b_gr_fecs_acr = { 75 .bld_size = sizeof(struct flcn_bl_dmem_desc), 76 .bld_write = gm20b_gr_acr_bld_write, 77 .bld_patch = gm20b_gr_acr_bld_patch, 78 }; 79 80 static void 81 gm20b_gr_init_gpc_mmu(struct gf100_gr *gr) 82 { 83 struct nvkm_device *device = gr->base.engine.subdev.device; 84 u32 val; 85 86 /* Bypass MMU check for non-secure boot */ 87 if (!device->acr) { 88 nvkm_wr32(device, 0x100ce4, 0xffffffff); 89 90 if (nvkm_rd32(device, 0x100ce4) != 0xffffffff) 91 nvdev_warn(device, 92 "cannot bypass secure boot - expect failure soon!\n"); 93 } 94 95 val = nvkm_rd32(device, 0x100c80); 96 val &= 0xf000187f; 97 nvkm_wr32(device, 0x418880, val); 98 nvkm_wr32(device, 0x418890, 0); 99 nvkm_wr32(device, 0x418894, 0); 100 101 nvkm_wr32(device, 0x4188b0, nvkm_rd32(device, 0x100cc4)); 102 nvkm_wr32(device, 0x4188b4, nvkm_rd32(device, 0x100cc8)); 103 nvkm_wr32(device, 0x4188b8, nvkm_rd32(device, 0x100ccc)); 104 105 nvkm_wr32(device, 0x4188ac, nvkm_rd32(device, 0x100800)); 106 } 107 108 static void 109 gm20b_gr_set_hww_esr_report_mask(struct gf100_gr *gr) 110 { 111 struct nvkm_device *device = gr->base.engine.subdev.device; 112 nvkm_wr32(device, 0x419e44, 0xdffffe); 113 nvkm_wr32(device, 0x419e4c, 0x5); 114 } 115 116 static const struct gf100_gr_func 117 gm20b_gr = { 118 .oneinit_tiles = gm200_gr_oneinit_tiles, 119 .oneinit_sm_id = gm200_gr_oneinit_sm_id, 120 .init = gk20a_gr_init, 121 .init_zcull = gf117_gr_init_zcull, 122 .init_gpc_mmu = gm20b_gr_init_gpc_mmu, 123 .init_rop_active_fbps = gk104_gr_init_rop_active_fbps, 124 .trap_mp = gf100_gr_trap_mp, 125 .set_hww_esr_report_mask = gm20b_gr_set_hww_esr_report_mask, 126 .fecs.reset = gf100_gr_fecs_reset, 127 .rops = gm200_gr_rops, 128 .ppc_nr = 1, 129 .grctx = &gm20b_grctx, 130 .zbc = &gf100_gr_zbc, 131 .sclass = { 132 { -1, -1, FERMI_TWOD_A }, 133 { -1, -1, KEPLER_INLINE_TO_MEMORY_B }, 134 { -1, -1, MAXWELL_B, &gf100_fermi }, 135 { -1, -1, MAXWELL_COMPUTE_B }, 136 {} 137 } 138 }; 139 140 static int 141 gm20b_gr_load(struct gf100_gr *gr, int ver, const struct gf100_gr_fwif *fwif) 142 { 143 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 144 int ret; 145 146 ret = nvkm_acr_lsfw_load_bl_inst_data_sig(subdev, &gr->fecs.falcon, 147 NVKM_ACR_LSF_FECS, 148 "gr/fecs_", ver, fwif->fecs); 149 if (ret) 150 return ret; 151 152 153 if (nvkm_firmware_load_blob(subdev, "gr/", "gpccs_inst", ver, 154 &gr->gpccs.inst) || 155 nvkm_firmware_load_blob(subdev, "gr/", "gpccs_data", ver, 156 &gr->gpccs.data)) 157 return -ENOENT; 158 159 gr->firmware = true; 160 161 return gk20a_gr_load_sw(gr, "gr/", ver); 162 } 163 164 #if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) 165 MODULE_FIRMWARE("nvidia/gm20b/gr/fecs_bl.bin"); 166 MODULE_FIRMWARE("nvidia/gm20b/gr/fecs_inst.bin"); 167 MODULE_FIRMWARE("nvidia/gm20b/gr/fecs_data.bin"); 168 MODULE_FIRMWARE("nvidia/gm20b/gr/fecs_sig.bin"); 169 MODULE_FIRMWARE("nvidia/gm20b/gr/gpccs_inst.bin"); 170 MODULE_FIRMWARE("nvidia/gm20b/gr/gpccs_data.bin"); 171 MODULE_FIRMWARE("nvidia/gm20b/gr/sw_ctx.bin"); 172 MODULE_FIRMWARE("nvidia/gm20b/gr/sw_nonctx.bin"); 173 MODULE_FIRMWARE("nvidia/gm20b/gr/sw_bundle_init.bin"); 174 MODULE_FIRMWARE("nvidia/gm20b/gr/sw_method_init.bin"); 175 #endif 176 177 static const struct gf100_gr_fwif 178 gm20b_gr_fwif[] = { 179 { 0, gm20b_gr_load, &gm20b_gr, &gm20b_gr_fecs_acr }, 180 { -1, gm200_gr_nofw }, 181 {} 182 }; 183 184 int 185 gm20b_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) 186 { 187 return gf100_gr_new_(gm20b_gr_fwif, device, type, inst, pgr); 188 } 189