1 /* 2 * Copyright 2013 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs <bskeggs@redhat.com> 23 */ 24 #include "gf100.h" 25 #include "ctxgf100.h" 26 27 #include <subdev/bios.h> 28 #include <subdev/bios/P0260.h> 29 30 #include <nvif/class.h> 31 32 /******************************************************************************* 33 * Graphics object classes 34 ******************************************************************************/ 35 36 static struct nvkm_oclass 37 gm107_gr_sclass[] = { 38 { 0x902d, &nvkm_object_ofuncs }, 39 { 0xa140, &nvkm_object_ofuncs }, 40 { MAXWELL_A, &gf100_fermi_ofuncs, gf100_gr_9097_omthds }, 41 { MAXWELL_COMPUTE_A, &nvkm_object_ofuncs, gf100_gr_90c0_omthds }, 42 {} 43 }; 44 45 /******************************************************************************* 46 * PGRAPH register lists 47 ******************************************************************************/ 48 49 static const struct gf100_gr_init 50 gm107_gr_init_main_0[] = { 51 { 0x400080, 1, 0x04, 0x003003c2 }, 52 { 0x400088, 1, 0x04, 0x0001bfe7 }, 53 { 0x40008c, 1, 0x04, 0x00060000 }, 54 { 0x400090, 1, 0x04, 0x00000030 }, 55 { 0x40013c, 1, 0x04, 0x003901f3 }, 56 { 0x400140, 1, 0x04, 0x00000100 }, 57 { 0x400144, 1, 0x04, 0x00000000 }, 58 { 0x400148, 1, 0x04, 0x00000110 }, 59 { 0x400138, 1, 0x04, 0x00000000 }, 60 { 0x400130, 2, 0x04, 0x00000000 }, 61 { 0x400124, 1, 0x04, 0x00000002 }, 62 {} 63 }; 64 65 static const struct gf100_gr_init 66 gm107_gr_init_ds_0[] = { 67 { 0x405844, 1, 0x04, 0x00ffffff }, 68 { 0x405850, 1, 0x04, 0x00000000 }, 69 { 0x405900, 1, 0x04, 0x00000000 }, 70 { 0x405908, 1, 0x04, 0x00000000 }, 71 {} 72 }; 73 74 static const struct gf100_gr_init 75 gm107_gr_init_scc_0[] = { 76 { 0x40803c, 1, 0x04, 0x00000010 }, 77 {} 78 }; 79 80 static const struct gf100_gr_init 81 gm107_gr_init_sked_0[] = { 82 { 0x407010, 1, 0x04, 0x00000000 }, 83 { 0x407040, 1, 0x04, 0x40440424 }, 84 { 0x407048, 1, 0x04, 0x0000000a }, 85 {} 86 }; 87 88 static const struct gf100_gr_init 89 gm107_gr_init_prop_0[] = { 90 { 0x418408, 1, 0x04, 0x00000000 }, 91 { 0x4184a0, 1, 0x04, 0x00000000 }, 92 {} 93 }; 94 95 static const struct gf100_gr_init 96 gm107_gr_init_setup_1[] = { 97 { 0x4188c8, 2, 0x04, 0x00000000 }, 98 { 0x4188d0, 1, 0x04, 0x00010000 }, 99 { 0x4188d4, 1, 0x04, 0x00010201 }, 100 {} 101 }; 102 103 static const struct gf100_gr_init 104 gm107_gr_init_zcull_0[] = { 105 { 0x418910, 1, 0x04, 0x00010001 }, 106 { 0x418914, 1, 0x04, 0x00000301 }, 107 { 0x418918, 1, 0x04, 0x00800000 }, 108 { 0x418930, 2, 0x04, 0x00000000 }, 109 { 0x418980, 1, 0x04, 0x77777770 }, 110 { 0x418984, 3, 0x04, 0x77777777 }, 111 {} 112 }; 113 114 static const struct gf100_gr_init 115 gm107_gr_init_gpc_unk_1[] = { 116 { 0x418d00, 1, 0x04, 0x00000000 }, 117 { 0x418f00, 1, 0x04, 0x00000400 }, 118 { 0x418f08, 1, 0x04, 0x00000000 }, 119 { 0x418e08, 1, 0x04, 0x00000000 }, 120 {} 121 }; 122 123 static const struct gf100_gr_init 124 gm107_gr_init_tpccs_0[] = { 125 { 0x419dc4, 1, 0x04, 0x00000000 }, 126 { 0x419dc8, 1, 0x04, 0x00000501 }, 127 { 0x419dd0, 1, 0x04, 0x00000000 }, 128 { 0x419dd4, 1, 0x04, 0x00000100 }, 129 { 0x419dd8, 1, 0x04, 0x00000001 }, 130 { 0x419ddc, 1, 0x04, 0x00000002 }, 131 { 0x419de0, 1, 0x04, 0x00000001 }, 132 { 0x419d0c, 1, 0x04, 0x00000000 }, 133 { 0x419d10, 1, 0x04, 0x00000014 }, 134 {} 135 }; 136 137 static const struct gf100_gr_init 138 gm107_gr_init_tex_0[] = { 139 { 0x419ab0, 1, 0x04, 0x00000000 }, 140 { 0x419ab8, 1, 0x04, 0x000000e7 }, 141 { 0x419abc, 1, 0x04, 0x00000000 }, 142 { 0x419acc, 1, 0x04, 0x000000ff }, 143 { 0x419ac0, 1, 0x04, 0x00000000 }, 144 { 0x419aa8, 2, 0x04, 0x00000000 }, 145 { 0x419ad0, 2, 0x04, 0x00000000 }, 146 { 0x419ae0, 2, 0x04, 0x00000000 }, 147 { 0x419af0, 4, 0x04, 0x00000000 }, 148 {} 149 }; 150 151 static const struct gf100_gr_init 152 gm107_gr_init_pe_0[] = { 153 { 0x419900, 1, 0x04, 0x000000ff }, 154 { 0x41980c, 1, 0x04, 0x00000010 }, 155 { 0x419844, 1, 0x04, 0x00000000 }, 156 { 0x419838, 1, 0x04, 0x000000ff }, 157 { 0x419850, 1, 0x04, 0x00000004 }, 158 { 0x419854, 2, 0x04, 0x00000000 }, 159 { 0x419894, 3, 0x04, 0x00100401 }, 160 {} 161 }; 162 163 static const struct gf100_gr_init 164 gm107_gr_init_l1c_0[] = { 165 { 0x419c98, 1, 0x04, 0x00000000 }, 166 { 0x419cc0, 2, 0x04, 0x00000000 }, 167 {} 168 }; 169 170 static const struct gf100_gr_init 171 gm107_gr_init_sm_0[] = { 172 { 0x419e30, 1, 0x04, 0x000000ff }, 173 { 0x419e00, 1, 0x04, 0x00000000 }, 174 { 0x419ea0, 1, 0x04, 0x00000000 }, 175 { 0x419ee4, 1, 0x04, 0x00000000 }, 176 { 0x419ea4, 1, 0x04, 0x00000100 }, 177 { 0x419ea8, 1, 0x04, 0x01000000 }, 178 { 0x419ee8, 1, 0x04, 0x00000091 }, 179 { 0x419eb4, 1, 0x04, 0x00000000 }, 180 { 0x419ebc, 2, 0x04, 0x00000000 }, 181 { 0x419edc, 1, 0x04, 0x000c1810 }, 182 { 0x419ed8, 1, 0x04, 0x00000000 }, 183 { 0x419ee0, 1, 0x04, 0x00000000 }, 184 { 0x419f74, 1, 0x04, 0x00005155 }, 185 { 0x419f80, 4, 0x04, 0x00000000 }, 186 {} 187 }; 188 189 static const struct gf100_gr_init 190 gm107_gr_init_l1c_1[] = { 191 { 0x419ccc, 2, 0x04, 0x00000000 }, 192 { 0x419c80, 1, 0x04, 0x3f006022 }, 193 { 0x419c88, 1, 0x04, 0x00000000 }, 194 {} 195 }; 196 197 static const struct gf100_gr_init 198 gm107_gr_init_pes_0[] = { 199 { 0x41be50, 1, 0x04, 0x000000ff }, 200 { 0x41be04, 1, 0x04, 0x00000000 }, 201 { 0x41be08, 1, 0x04, 0x00000004 }, 202 { 0x41be0c, 1, 0x04, 0x00000008 }, 203 { 0x41be10, 1, 0x04, 0x0e3b8bc7 }, 204 { 0x41be14, 2, 0x04, 0x00000000 }, 205 { 0x41be3c, 5, 0x04, 0x00100401 }, 206 {} 207 }; 208 209 static const struct gf100_gr_init 210 gm107_gr_init_wwdx_0[] = { 211 { 0x41bfd4, 1, 0x04, 0x00800000 }, 212 { 0x41bfdc, 1, 0x04, 0x00000000 }, 213 {} 214 }; 215 216 static const struct gf100_gr_init 217 gm107_gr_init_cbm_0[] = { 218 { 0x41becc, 1, 0x04, 0x00000000 }, 219 {} 220 }; 221 222 static const struct gf100_gr_init 223 gm107_gr_init_be_0[] = { 224 { 0x408890, 1, 0x04, 0x000000ff }, 225 { 0x40880c, 1, 0x04, 0x00000000 }, 226 { 0x408850, 1, 0x04, 0x00000004 }, 227 { 0x408878, 1, 0x04, 0x00c81603 }, 228 { 0x40887c, 1, 0x04, 0x80543432 }, 229 { 0x408880, 1, 0x04, 0x0010581e }, 230 { 0x408884, 1, 0x04, 0x00001205 }, 231 { 0x408974, 1, 0x04, 0x000000ff }, 232 { 0x408910, 9, 0x04, 0x00000000 }, 233 { 0x408950, 1, 0x04, 0x00000000 }, 234 { 0x408954, 1, 0x04, 0x0000ffff }, 235 { 0x408958, 1, 0x04, 0x00000034 }, 236 { 0x40895c, 1, 0x04, 0x8531a003 }, 237 { 0x408960, 1, 0x04, 0x0561985a }, 238 { 0x408964, 1, 0x04, 0x04e15c4f }, 239 { 0x408968, 1, 0x04, 0x02808833 }, 240 { 0x40896c, 1, 0x04, 0x01f02438 }, 241 { 0x408970, 1, 0x04, 0x00012c00 }, 242 { 0x408984, 1, 0x04, 0x00000000 }, 243 { 0x408988, 1, 0x04, 0x08040201 }, 244 { 0x40898c, 1, 0x04, 0x80402010 }, 245 {} 246 }; 247 248 static const struct gf100_gr_init 249 gm107_gr_init_sm_1[] = { 250 { 0x419e5c, 1, 0x04, 0x00000000 }, 251 { 0x419e58, 1, 0x04, 0x00000000 }, 252 {} 253 }; 254 255 static const struct gf100_gr_pack 256 gm107_gr_pack_mmio[] = { 257 { gm107_gr_init_main_0 }, 258 { gk110_gr_init_fe_0 }, 259 { gf100_gr_init_pri_0 }, 260 { gf100_gr_init_rstr2d_0 }, 261 { gf100_gr_init_pd_0 }, 262 { gm107_gr_init_ds_0 }, 263 { gm107_gr_init_scc_0 }, 264 { gm107_gr_init_sked_0 }, 265 { gk110_gr_init_cwd_0 }, 266 { gm107_gr_init_prop_0 }, 267 { gk208_gr_init_gpc_unk_0 }, 268 { gf100_gr_init_setup_0 }, 269 { gf100_gr_init_crstr_0 }, 270 { gm107_gr_init_setup_1 }, 271 { gm107_gr_init_zcull_0 }, 272 { gf100_gr_init_gpm_0 }, 273 { gm107_gr_init_gpc_unk_1 }, 274 { gf100_gr_init_gcc_0 }, 275 { gm107_gr_init_tpccs_0 }, 276 { gm107_gr_init_tex_0 }, 277 { gm107_gr_init_pe_0 }, 278 { gm107_gr_init_l1c_0 }, 279 { gf100_gr_init_mpc_0 }, 280 { gm107_gr_init_sm_0 }, 281 { gm107_gr_init_l1c_1 }, 282 { gm107_gr_init_pes_0 }, 283 { gm107_gr_init_wwdx_0 }, 284 { gm107_gr_init_cbm_0 }, 285 { gm107_gr_init_be_0 }, 286 { gm107_gr_init_sm_1 }, 287 {} 288 }; 289 290 /******************************************************************************* 291 * PGRAPH engine/subdev functions 292 ******************************************************************************/ 293 294 static void 295 gm107_gr_init_bios(struct gf100_gr_priv *priv) 296 { 297 static const struct { 298 u32 ctrl; 299 u32 data; 300 } regs[] = { 301 { 0x419ed8, 0x419ee0 }, 302 { 0x419ad0, 0x419ad4 }, 303 { 0x419ae0, 0x419ae4 }, 304 { 0x419af0, 0x419af4 }, 305 { 0x419af8, 0x419afc }, 306 }; 307 struct nvkm_bios *bios = nvkm_bios(priv); 308 struct nvbios_P0260E infoE; 309 struct nvbios_P0260X infoX; 310 int E = -1, X; 311 u8 ver, hdr; 312 313 while (nvbios_P0260Ep(bios, ++E, &ver, &hdr, &infoE)) { 314 if (X = -1, E < ARRAY_SIZE(regs)) { 315 nv_wr32(priv, regs[E].ctrl, infoE.data); 316 while (nvbios_P0260Xp(bios, ++X, &ver, &hdr, &infoX)) 317 nv_wr32(priv, regs[E].data, infoX.data); 318 } 319 } 320 } 321 322 int 323 gm107_gr_init(struct nvkm_object *object) 324 { 325 struct gf100_gr_oclass *oclass = (void *)object->oclass; 326 struct gf100_gr_priv *priv = (void *)object; 327 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total); 328 u32 data[TPC_MAX / 8] = {}; 329 u8 tpcnr[GPC_MAX]; 330 int gpc, tpc, ppc, rop; 331 int ret, i; 332 333 ret = nvkm_gr_init(&priv->base); 334 if (ret) 335 return ret; 336 337 nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000); 338 nv_wr32(priv, GPC_BCAST(0x0890), 0x00000000); 339 nv_wr32(priv, GPC_BCAST(0x0894), 0x00000000); 340 nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8); 341 nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8); 342 343 gf100_gr_mmio(priv, oclass->mmio); 344 345 gm107_gr_init_bios(priv); 346 347 nv_wr32(priv, GPC_UNIT(0, 0x3018), 0x00000001); 348 349 memset(data, 0x00, sizeof(data)); 350 memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); 351 for (i = 0, gpc = -1; i < priv->tpc_total; i++) { 352 do { 353 gpc = (gpc + 1) % priv->gpc_nr; 354 } while (!tpcnr[gpc]); 355 tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--; 356 357 data[i / 8] |= tpc << ((i % 8) * 4); 358 } 359 360 nv_wr32(priv, GPC_BCAST(0x0980), data[0]); 361 nv_wr32(priv, GPC_BCAST(0x0984), data[1]); 362 nv_wr32(priv, GPC_BCAST(0x0988), data[2]); 363 nv_wr32(priv, GPC_BCAST(0x098c), data[3]); 364 365 for (gpc = 0; gpc < priv->gpc_nr; gpc++) { 366 nv_wr32(priv, GPC_UNIT(gpc, 0x0914), 367 priv->magic_not_rop_nr << 8 | priv->tpc_nr[gpc]); 368 nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 | 369 priv->tpc_total); 370 nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918); 371 } 372 373 nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918); 374 nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800)); 375 376 nv_wr32(priv, 0x400500, 0x00010001); 377 378 nv_wr32(priv, 0x400100, 0xffffffff); 379 nv_wr32(priv, 0x40013c, 0xffffffff); 380 nv_wr32(priv, 0x400124, 0x00000002); 381 nv_wr32(priv, 0x409c24, 0x000e0000); 382 383 nv_wr32(priv, 0x404000, 0xc0000000); 384 nv_wr32(priv, 0x404600, 0xc0000000); 385 nv_wr32(priv, 0x408030, 0xc0000000); 386 nv_wr32(priv, 0x404490, 0xc0000000); 387 nv_wr32(priv, 0x406018, 0xc0000000); 388 nv_wr32(priv, 0x407020, 0x40000000); 389 nv_wr32(priv, 0x405840, 0xc0000000); 390 nv_wr32(priv, 0x405844, 0x00ffffff); 391 nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008); 392 393 for (gpc = 0; gpc < priv->gpc_nr; gpc++) { 394 for (ppc = 0; ppc < 2 /* priv->ppc_nr[gpc] */; ppc++) 395 nv_wr32(priv, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000); 396 nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000); 397 nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000); 398 nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000); 399 nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000); 400 for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { 401 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); 402 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); 403 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); 404 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); 405 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); 406 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000); 407 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe); 408 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x00000005); 409 } 410 nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff); 411 nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff); 412 } 413 414 for (rop = 0; rop < priv->rop_nr; rop++) { 415 nv_wr32(priv, ROP_UNIT(rop, 0x144), 0x40000000); 416 nv_wr32(priv, ROP_UNIT(rop, 0x070), 0x40000000); 417 nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff); 418 nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff); 419 } 420 421 nv_wr32(priv, 0x400108, 0xffffffff); 422 nv_wr32(priv, 0x400138, 0xffffffff); 423 nv_wr32(priv, 0x400118, 0xffffffff); 424 nv_wr32(priv, 0x400130, 0xffffffff); 425 nv_wr32(priv, 0x40011c, 0xffffffff); 426 nv_wr32(priv, 0x400134, 0xffffffff); 427 428 nv_wr32(priv, 0x400054, 0x2c350f63); 429 430 gf100_gr_zbc_init(priv); 431 432 return gf100_gr_init_ctxctl(priv); 433 } 434 435 #include "fuc/hubgm107.fuc5.h" 436 437 static struct gf100_gr_ucode 438 gm107_gr_fecs_ucode = { 439 .code.data = gm107_grhub_code, 440 .code.size = sizeof(gm107_grhub_code), 441 .data.data = gm107_grhub_data, 442 .data.size = sizeof(gm107_grhub_data), 443 }; 444 445 #include "fuc/gpcgm107.fuc5.h" 446 447 static struct gf100_gr_ucode 448 gm107_gr_gpccs_ucode = { 449 .code.data = gm107_grgpc_code, 450 .code.size = sizeof(gm107_grgpc_code), 451 .data.data = gm107_grgpc_data, 452 .data.size = sizeof(gm107_grgpc_data), 453 }; 454 455 struct nvkm_oclass * 456 gm107_gr_oclass = &(struct gf100_gr_oclass) { 457 .base.handle = NV_ENGINE(GR, 0x07), 458 .base.ofuncs = &(struct nvkm_ofuncs) { 459 .ctor = gf100_gr_ctor, 460 .dtor = gf100_gr_dtor, 461 .init = gm107_gr_init, 462 .fini = _nvkm_gr_fini, 463 }, 464 .cclass = &gm107_grctx_oclass, 465 .sclass = gm107_gr_sclass, 466 .mmio = gm107_gr_pack_mmio, 467 .fecs.ucode = 0 ? &gm107_gr_fecs_ucode : NULL, 468 .gpccs.ucode = &gm107_gr_gpccs_ucode, 469 .ppc_nr = 2, 470 }.base; 471