1 /* 2 * Copyright 2013 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs <bskeggs@redhat.com> 23 */ 24 #include "gf100.h" 25 #include "ctxgf100.h" 26 27 #include <subdev/bios.h> 28 #include <subdev/bios/bit.h> 29 #include <subdev/bios/init.h> 30 #include <subdev/bios/P0260.h> 31 #include <subdev/fb.h> 32 33 #include <nvif/class.h> 34 35 /******************************************************************************* 36 * PGRAPH register lists 37 ******************************************************************************/ 38 39 static const struct gf100_gr_init 40 gm107_gr_init_main_0[] = { 41 { 0x40880c, 1, 0x04, 0x00000000 }, 42 { 0x408910, 1, 0x04, 0x00000000 }, 43 { 0x408984, 1, 0x04, 0x00000000 }, 44 { 0x41a8a0, 1, 0x04, 0x00000000 }, 45 { 0x400080, 1, 0x04, 0x003003c2 }, 46 { 0x400088, 1, 0x04, 0x0001bfe7 }, 47 { 0x40008c, 1, 0x04, 0x00060000 }, 48 { 0x400090, 1, 0x04, 0x00000030 }, 49 { 0x40013c, 1, 0x04, 0x003901f3 }, 50 { 0x400140, 1, 0x04, 0x00000100 }, 51 { 0x400144, 1, 0x04, 0x00000000 }, 52 { 0x400148, 1, 0x04, 0x00000110 }, 53 { 0x400138, 1, 0x04, 0x00000000 }, 54 { 0x400130, 2, 0x04, 0x00000000 }, 55 { 0x400124, 1, 0x04, 0x00000002 }, 56 {} 57 }; 58 59 static const struct gf100_gr_init 60 gm107_gr_init_ds_0[] = { 61 { 0x405844, 1, 0x04, 0x00ffffff }, 62 { 0x405850, 1, 0x04, 0x00000000 }, 63 { 0x405900, 1, 0x04, 0x00000000 }, 64 { 0x405908, 1, 0x04, 0x00000000 }, 65 {} 66 }; 67 68 const struct gf100_gr_init 69 gm107_gr_init_scc_0[] = { 70 { 0x40803c, 1, 0x04, 0x00000010 }, 71 {} 72 }; 73 74 static const struct gf100_gr_init 75 gm107_gr_init_sked_0[] = { 76 { 0x407010, 1, 0x04, 0x00000000 }, 77 { 0x407040, 1, 0x04, 0x40440424 }, 78 { 0x407048, 1, 0x04, 0x0000000a }, 79 {} 80 }; 81 82 const struct gf100_gr_init 83 gm107_gr_init_prop_0[] = { 84 { 0x418408, 1, 0x04, 0x00000000 }, 85 { 0x4184a0, 1, 0x04, 0x00000000 }, 86 {} 87 }; 88 89 const struct gf100_gr_init 90 gm107_gr_init_setup_1[] = { 91 { 0x4188c8, 2, 0x04, 0x00000000 }, 92 { 0x4188d0, 1, 0x04, 0x00010000 }, 93 { 0x4188d4, 1, 0x04, 0x00010201 }, 94 {} 95 }; 96 97 const struct gf100_gr_init 98 gm107_gr_init_zcull_0[] = { 99 { 0x418910, 1, 0x04, 0x00010001 }, 100 { 0x418914, 1, 0x04, 0x00000301 }, 101 { 0x418918, 1, 0x04, 0x00800000 }, 102 { 0x418930, 2, 0x04, 0x00000000 }, 103 { 0x418980, 1, 0x04, 0x77777770 }, 104 { 0x418984, 3, 0x04, 0x77777777 }, 105 {} 106 }; 107 108 const struct gf100_gr_init 109 gm107_gr_init_gpc_unk_1[] = { 110 { 0x418d00, 1, 0x04, 0x00000000 }, 111 { 0x418f00, 1, 0x04, 0x00000400 }, 112 { 0x418f08, 1, 0x04, 0x00000000 }, 113 { 0x418e08, 1, 0x04, 0x00000000 }, 114 {} 115 }; 116 117 static const struct gf100_gr_init 118 gm107_gr_init_tpccs_0[] = { 119 { 0x419dc4, 1, 0x04, 0x00000000 }, 120 { 0x419dc8, 1, 0x04, 0x00000501 }, 121 { 0x419dd0, 1, 0x04, 0x00000000 }, 122 { 0x419dd4, 1, 0x04, 0x00000100 }, 123 { 0x419dd8, 1, 0x04, 0x00000001 }, 124 { 0x419ddc, 1, 0x04, 0x00000002 }, 125 { 0x419de0, 1, 0x04, 0x00000001 }, 126 { 0x419d0c, 1, 0x04, 0x00000000 }, 127 { 0x419d10, 1, 0x04, 0x00000014 }, 128 {} 129 }; 130 131 const struct gf100_gr_init 132 gm107_gr_init_tex_0[] = { 133 { 0x419ab0, 1, 0x04, 0x00000000 }, 134 { 0x419ab8, 1, 0x04, 0x000000e7 }, 135 { 0x419abc, 1, 0x04, 0x00000000 }, 136 { 0x419acc, 1, 0x04, 0x000000ff }, 137 { 0x419ac0, 1, 0x04, 0x00000000 }, 138 { 0x419aa8, 2, 0x04, 0x00000000 }, 139 { 0x419ad0, 2, 0x04, 0x00000000 }, 140 { 0x419ae0, 2, 0x04, 0x00000000 }, 141 { 0x419af0, 4, 0x04, 0x00000000 }, 142 {} 143 }; 144 145 static const struct gf100_gr_init 146 gm107_gr_init_pe_0[] = { 147 { 0x419900, 1, 0x04, 0x000000ff }, 148 { 0x41980c, 1, 0x04, 0x00000010 }, 149 { 0x419844, 1, 0x04, 0x00000000 }, 150 { 0x419838, 1, 0x04, 0x000000ff }, 151 { 0x419850, 1, 0x04, 0x00000004 }, 152 { 0x419854, 2, 0x04, 0x00000000 }, 153 { 0x419894, 3, 0x04, 0x00100401 }, 154 {} 155 }; 156 157 const struct gf100_gr_init 158 gm107_gr_init_l1c_0[] = { 159 { 0x419c98, 1, 0x04, 0x00000000 }, 160 { 0x419cc0, 2, 0x04, 0x00000000 }, 161 {} 162 }; 163 164 static const struct gf100_gr_init 165 gm107_gr_init_sm_0[] = { 166 { 0x419e30, 1, 0x04, 0x000000ff }, 167 { 0x419e00, 1, 0x04, 0x00000000 }, 168 { 0x419ea0, 1, 0x04, 0x00000000 }, 169 { 0x419ee4, 1, 0x04, 0x00000000 }, 170 { 0x419ea4, 1, 0x04, 0x00000100 }, 171 { 0x419ea8, 1, 0x04, 0x01000000 }, 172 { 0x419ee8, 1, 0x04, 0x00000091 }, 173 { 0x419eb4, 1, 0x04, 0x00000000 }, 174 { 0x419ebc, 2, 0x04, 0x00000000 }, 175 { 0x419edc, 1, 0x04, 0x000c1810 }, 176 { 0x419ed8, 1, 0x04, 0x00000000 }, 177 { 0x419ee0, 1, 0x04, 0x00000000 }, 178 { 0x419f74, 1, 0x04, 0x00005155 }, 179 { 0x419f80, 4, 0x04, 0x00000000 }, 180 {} 181 }; 182 183 static const struct gf100_gr_init 184 gm107_gr_init_l1c_1[] = { 185 { 0x419ccc, 2, 0x04, 0x00000000 }, 186 { 0x419c80, 1, 0x04, 0x3f006022 }, 187 { 0x419c88, 1, 0x04, 0x00000000 }, 188 {} 189 }; 190 191 static const struct gf100_gr_init 192 gm107_gr_init_pes_0[] = { 193 { 0x41be50, 1, 0x04, 0x000000ff }, 194 { 0x41be04, 1, 0x04, 0x00000000 }, 195 { 0x41be08, 1, 0x04, 0x00000004 }, 196 { 0x41be0c, 1, 0x04, 0x00000008 }, 197 { 0x41be10, 1, 0x04, 0x0e3b8bc7 }, 198 { 0x41be14, 2, 0x04, 0x00000000 }, 199 { 0x41be3c, 5, 0x04, 0x00100401 }, 200 {} 201 }; 202 203 const struct gf100_gr_init 204 gm107_gr_init_wwdx_0[] = { 205 { 0x41bfd4, 1, 0x04, 0x00800000 }, 206 { 0x41bfdc, 1, 0x04, 0x00000000 }, 207 {} 208 }; 209 210 const struct gf100_gr_init 211 gm107_gr_init_cbm_0[] = { 212 { 0x41becc, 1, 0x04, 0x00000000 }, 213 {} 214 }; 215 216 static const struct gf100_gr_init 217 gm107_gr_init_be_0[] = { 218 { 0x408890, 1, 0x04, 0x000000ff }, 219 { 0x408850, 1, 0x04, 0x00000004 }, 220 { 0x408878, 1, 0x04, 0x00c81603 }, 221 { 0x40887c, 1, 0x04, 0x80543432 }, 222 { 0x408880, 1, 0x04, 0x0010581e }, 223 { 0x408884, 1, 0x04, 0x00001205 }, 224 { 0x408974, 1, 0x04, 0x000000ff }, 225 { 0x408914, 8, 0x04, 0x00000000 }, 226 { 0x408950, 1, 0x04, 0x00000000 }, 227 { 0x408954, 1, 0x04, 0x0000ffff }, 228 { 0x408958, 1, 0x04, 0x00000034 }, 229 { 0x40895c, 1, 0x04, 0x8531a003 }, 230 { 0x408960, 1, 0x04, 0x0561985a }, 231 { 0x408964, 1, 0x04, 0x04e15c4f }, 232 { 0x408968, 1, 0x04, 0x02808833 }, 233 { 0x40896c, 1, 0x04, 0x01f02438 }, 234 { 0x408970, 1, 0x04, 0x00012c00 }, 235 { 0x408988, 1, 0x04, 0x08040201 }, 236 { 0x40898c, 1, 0x04, 0x80402010 }, 237 {} 238 }; 239 240 static const struct gf100_gr_init 241 gm107_gr_init_sm_1[] = { 242 { 0x419e5c, 1, 0x04, 0x00000000 }, 243 { 0x419e58, 1, 0x04, 0x00000000 }, 244 {} 245 }; 246 247 static const struct gf100_gr_pack 248 gm107_gr_pack_mmio[] = { 249 { gm107_gr_init_main_0 }, 250 { gk110_gr_init_fe_0 }, 251 { gf100_gr_init_pri_0 }, 252 { gf100_gr_init_rstr2d_0 }, 253 { gf100_gr_init_pd_0 }, 254 { gm107_gr_init_ds_0 }, 255 { gm107_gr_init_scc_0 }, 256 { gm107_gr_init_sked_0 }, 257 { gk110_gr_init_cwd_0 }, 258 { gm107_gr_init_prop_0 }, 259 { gk208_gr_init_gpc_unk_0 }, 260 { gf100_gr_init_setup_0 }, 261 { gf100_gr_init_crstr_0 }, 262 { gm107_gr_init_setup_1 }, 263 { gm107_gr_init_zcull_0 }, 264 { gf100_gr_init_gpm_0 }, 265 { gm107_gr_init_gpc_unk_1 }, 266 { gf100_gr_init_gcc_0 }, 267 { gk104_gr_init_gpc_unk_2 }, 268 { gm107_gr_init_tpccs_0 }, 269 { gm107_gr_init_tex_0 }, 270 { gm107_gr_init_pe_0 }, 271 { gm107_gr_init_l1c_0 }, 272 { gf100_gr_init_mpc_0 }, 273 { gm107_gr_init_sm_0 }, 274 { gm107_gr_init_l1c_1 }, 275 { gm107_gr_init_pes_0 }, 276 { gm107_gr_init_wwdx_0 }, 277 { gm107_gr_init_cbm_0 }, 278 { gm107_gr_init_be_0 }, 279 { gm107_gr_init_sm_1 }, 280 {} 281 }; 282 283 /******************************************************************************* 284 * PGRAPH engine/subdev functions 285 ******************************************************************************/ 286 287 void 288 gm107_gr_init_400054(struct gf100_gr *gr) 289 { 290 nvkm_wr32(gr->base.engine.subdev.device, 0x400054, 0x2c350f63); 291 } 292 293 void 294 gm107_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc) 295 { 296 struct nvkm_device *device = gr->base.engine.subdev.device; 297 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe); 298 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x00000005); 299 } 300 301 void 302 gm107_gr_init_504430(struct gf100_gr *gr, int gpc, int tpc) 303 { 304 struct nvkm_device *device = gr->base.engine.subdev.device; 305 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000); 306 } 307 308 static void 309 gm107_gr_init_bios_2(struct gf100_gr *gr) 310 { 311 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 312 struct nvkm_device *device = subdev->device; 313 struct nvkm_bios *bios = device->bios; 314 struct bit_entry bit_P; 315 if (!bit_entry(bios, 'P', &bit_P) && 316 bit_P.version == 2 && bit_P.length >= 0x2c) { 317 u32 data = nvbios_rd32(bios, bit_P.offset + 0x28); 318 if (data) { 319 u8 ver = nvbios_rd08(bios, data + 0x00); 320 u8 hdr = nvbios_rd08(bios, data + 0x01); 321 if (ver == 0x20 && hdr >= 8) { 322 data = nvbios_rd32(bios, data + 0x04); 323 if (data) { 324 u32 save = nvkm_rd32(device, 0x619444); 325 nvbios_init(subdev, data); 326 nvkm_wr32(device, 0x619444, save); 327 } 328 } 329 } 330 } 331 } 332 333 void 334 gm107_gr_init_bios(struct gf100_gr *gr) 335 { 336 static const struct { 337 u32 ctrl; 338 u32 data; 339 } regs[] = { 340 { 0x419ed8, 0x419ee0 }, 341 { 0x419ad0, 0x419ad4 }, 342 { 0x419ae0, 0x419ae4 }, 343 { 0x419af0, 0x419af4 }, 344 { 0x419af8, 0x419afc }, 345 }; 346 struct nvkm_device *device = gr->base.engine.subdev.device; 347 struct nvkm_bios *bios = device->bios; 348 struct nvbios_P0260E infoE; 349 struct nvbios_P0260X infoX; 350 int E = -1, X; 351 u8 ver, hdr; 352 353 while (nvbios_P0260Ep(bios, ++E, &ver, &hdr, &infoE)) { 354 if (X = -1, E < ARRAY_SIZE(regs)) { 355 nvkm_wr32(device, regs[E].ctrl, infoE.data); 356 while (nvbios_P0260Xp(bios, ++X, &ver, &hdr, &infoX)) 357 nvkm_wr32(device, regs[E].data, infoX.data); 358 } 359 } 360 } 361 362 static void 363 gm107_gr_init_gpc_mmu(struct gf100_gr *gr) 364 { 365 struct nvkm_device *device = gr->base.engine.subdev.device; 366 struct nvkm_fb *fb = device->fb; 367 368 nvkm_wr32(device, GPC_BCAST(0x0880), 0x00000000); 369 nvkm_wr32(device, GPC_BCAST(0x0890), 0x00000000); 370 nvkm_wr32(device, GPC_BCAST(0x0894), 0x00000000); 371 nvkm_wr32(device, GPC_BCAST(0x08b4), nvkm_memory_addr(fb->mmu_wr) >> 8); 372 nvkm_wr32(device, GPC_BCAST(0x08b8), nvkm_memory_addr(fb->mmu_rd) >> 8); 373 } 374 375 #include "fuc/hubgm107.fuc5.h" 376 377 static struct gf100_gr_ucode 378 gm107_gr_fecs_ucode = { 379 .code.data = gm107_grhub_code, 380 .code.size = sizeof(gm107_grhub_code), 381 .data.data = gm107_grhub_data, 382 .data.size = sizeof(gm107_grhub_data), 383 }; 384 385 #include "fuc/gpcgm107.fuc5.h" 386 387 static struct gf100_gr_ucode 388 gm107_gr_gpccs_ucode = { 389 .code.data = gm107_grgpc_code, 390 .code.size = sizeof(gm107_grgpc_code), 391 .data.data = gm107_grgpc_data, 392 .data.size = sizeof(gm107_grgpc_data), 393 }; 394 395 static const struct gf100_gr_func 396 gm107_gr = { 397 .oneinit_tiles = gf100_gr_oneinit_tiles, 398 .oneinit_sm_id = gf100_gr_oneinit_sm_id, 399 .init = gf100_gr_init, 400 .init_gpc_mmu = gm107_gr_init_gpc_mmu, 401 .init_bios = gm107_gr_init_bios, 402 .init_vsc_stream_master = gk104_gr_init_vsc_stream_master, 403 .init_zcull = gf117_gr_init_zcull, 404 .init_num_active_ltcs = gf100_gr_init_num_active_ltcs, 405 .init_rop_active_fbps = gk104_gr_init_rop_active_fbps, 406 .init_bios_2 = gm107_gr_init_bios_2, 407 .init_fecs_exceptions = gf100_gr_init_fecs_exceptions, 408 .init_sked_hww_esr = gk104_gr_init_sked_hww_esr, 409 .init_419cc0 = gf100_gr_init_419cc0, 410 .init_ppc_exceptions = gk104_gr_init_ppc_exceptions, 411 .init_tex_hww_esr = gf100_gr_init_tex_hww_esr, 412 .init_504430 = gm107_gr_init_504430, 413 .init_shader_exceptions = gm107_gr_init_shader_exceptions, 414 .init_400054 = gm107_gr_init_400054, 415 .trap_mp = gf100_gr_trap_mp, 416 .mmio = gm107_gr_pack_mmio, 417 .fecs.ucode = &gm107_gr_fecs_ucode, 418 .gpccs.ucode = &gm107_gr_gpccs_ucode, 419 .rops = gf100_gr_rops, 420 .ppc_nr = 2, 421 .grctx = &gm107_grctx, 422 .zbc = &gf100_gr_zbc, 423 .sclass = { 424 { -1, -1, FERMI_TWOD_A }, 425 { -1, -1, KEPLER_INLINE_TO_MEMORY_B }, 426 { -1, -1, MAXWELL_A, &gf100_fermi }, 427 { -1, -1, MAXWELL_COMPUTE_A }, 428 {} 429 } 430 }; 431 432 static const struct gf100_gr_fwif 433 gm107_gr_fwif[] = { 434 { -1, gf100_gr_load, &gm107_gr }, 435 { -1, gf100_gr_nofw, &gm107_gr }, 436 {} 437 }; 438 439 int 440 gm107_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr) 441 { 442 return gf100_gr_new_(gm107_gr_fwif, device, type, inst, pgr); 443 } 444