1/* fuc microcode for gf100 PGRAPH/HUB 2 * 3 * Copyright 2011 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Ben Skeggs 24 */ 25 26#ifdef INCLUDE_DATA 27hub_mmio_list_head: .b32 #hub_mmio_list_base 28hub_mmio_list_tail: .b32 #hub_mmio_list_next 29 30gpc_count: .b32 0 31rop_count: .b32 0 32cmd_queue: queue_init 33 34ctx_current: .b32 0 35 36.align 256 37chan_data: 38chan_mmio_count: .b32 0 39chan_mmio_address: .b32 0 40 41.align 256 42xfer_data: .skip 256 43 44hub_mmio_list_base: 45.b32 0x0417e91c // 0x17e91c, 2 46hub_mmio_list_next: 47#endif 48 49#ifdef INCLUDE_CODE 50// reports an exception to the host 51// 52// In: $r15 error code (see os.h) 53// 54error: 55 nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(5), 0, $r15) 56 mov $r15 1 57 nv_iowr(NV_PGRAPH_FECS_INTR_UP_SET, 0, $r15) 58 ret 59 60// HUB fuc initialisation, executed by triggering ucode start, will 61// fall through to main loop after completion. 62// 63// Output: 64// CC_SCRATCH[0]: 65// 31:31: set to signal completion 66// CC_SCRATCH[1]: 67// 31:0: total PGRAPH context size 68// 69init: 70 clear b32 $r0 71 mov $xdbase $r0 72 73 // setup stack 74 nv_iord($r1, NV_PGRAPH_FECS_CAPS, 0) 75 extr $r1 $r1 9:17 76 shl b32 $r1 8 77 mov $sp $r1 78 79 // enable fifo access 80 mov $r2 NV_PGRAPH_FECS_ACCESS_FIFO 81 nv_iowr(NV_PGRAPH_FECS_ACCESS, 0, $r2) 82 83 // setup i0 handler, and route all interrupts to it 84 mov $r1 #ih 85 mov $iv0 $r1 86 87 clear b32 $r2 88 nv_iowr(NV_PGRAPH_FECS_INTR_ROUTE, 0, $r2) 89 90 // route HUB_CHSW_PULSE to fuc interrupt 8 91 mov $r2 0x2003 // { HUB_CHSW_PULSE, ZERO } -> intr 8 92 nv_iowr(NV_PGRAPH_FECS_IROUTE, 0, $r2) 93 94 // not sure what these are, route them because NVIDIA does, and 95 // the IRQ handler will signal the host if we ever get one.. we 96 // may find out if/why we need to handle these if so.. 97 // 98 mov $r2 0x2004 // { 0x04, ZERO } -> intr 9 99 nv_iowr(NV_PGRAPH_FECS_IROUTE, 1, $r2) 100 mov $r2 0x200b // { HUB_FIRMWARE_MTHD, ZERO } -> intr 10 101 nv_iowr(NV_PGRAPH_FECS_IROUTE, 2, $r2) 102 mov $r2 0x200c // { 0x0c, ZERO } -> intr 15 103 nv_iowr(NV_PGRAPH_FECS_IROUTE, 7, $r2) 104 105 // enable all INTR_UP interrupts 106 sub b32 $r3 $r0 1 107 nv_iowr(NV_PGRAPH_FECS_INTR_UP_EN, 0, $r3) 108 109 // enable fifo, ctxsw, 9, fwmthd, 15 interrupts 110 imm32($r2, 0x8704) 111 nv_iowr(NV_PGRAPH_FECS_INTR_EN_SET, 0, $r2) 112 113 // fifo level triggered, rest edge 114 mov $r2 NV_PGRAPH_FECS_INTR_MODE_FIFO_LEVEL 115 nv_iowr(NV_PGRAPH_FECS_INTR_MODE, 0, $r2) 116 117 // enable interrupts 118 bset $flags ie0 119 120 // fetch enabled GPC/ROP counts 121 nv_rd32($r14, 0x409604) 122 extr $r1 $r15 16:20 123 st b32 D[$r0 + #rop_count] $r1 124 and $r15 0x1f 125 st b32 D[$r0 + #gpc_count] $r15 126 127 // set BAR_REQMASK to GPC mask 128 mov $r1 1 129 shl b32 $r1 $r15 130 sub b32 $r1 1 131 nv_iowr(NV_PGRAPH_FECS_BAR_MASK0, 0, $r1) 132 nv_iowr(NV_PGRAPH_FECS_BAR_MASK1, 0, $r1) 133 134 // context size calculation, reserve first 256 bytes for use by fuc 135 mov $r1 256 136 137 // 138 mov $r15 2 139 call(ctx_4170s) 140 call(ctx_4170w) 141 mov $r15 0x10 142 call(ctx_86c) 143 144 // calculate size of mmio context data 145 ld b32 $r14 D[$r0 + #hub_mmio_list_head] 146 ld b32 $r15 D[$r0 + #hub_mmio_list_tail] 147 call(mmctx_size) 148 149 // set mmctx base addresses now so we don't have to do it later, 150 // they don't (currently) ever change 151 shr b32 $r4 $r1 8 152 nv_iowr(NV_PGRAPH_FECS_MMCTX_SAVE_SWBASE, 0, $r4) 153 nv_iowr(NV_PGRAPH_FECS_MMCTX_LOAD_SWBASE, 0, $r4) 154 add b32 $r3 0x1300 155 add b32 $r1 $r15 156 shr b32 $r15 2 157 nv_iowr(NV_PGRAPH_FECS_MMCTX_LOAD_COUNT, 0, $r15) // wtf?? 158 159 // strands, base offset needs to be aligned to 256 bytes 160 shr b32 $r1 8 161 add b32 $r1 1 162 shl b32 $r1 8 163 mov b32 $r15 $r1 164 call(strand_ctx_init) 165 add b32 $r1 $r15 166 167 // initialise each GPC in sequence by passing in the offset of its 168 // context data in GPCn_CC_SCRATCH[1], and starting its FUC (which 169 // has previously been uploaded by the host) running. 170 // 171 // the GPC fuc init sequence will set GPCn_CC_SCRATCH[0] bit 31 172 // when it has completed, and return the size of its context data 173 // in GPCn_CC_SCRATCH[1] 174 // 175 ld b32 $r3 D[$r0 + #gpc_count] 176 imm32($r4, 0x502000) 177 init_gpc: 178 // setup, and start GPC ucode running 179 add b32 $r14 $r4 0x804 180 mov b32 $r15 $r1 181 call(nv_wr32) // CC_SCRATCH[1] = ctx offset 182 add b32 $r14 $r4 0x10c 183 clear b32 $r15 184 call(nv_wr32) 185 add b32 $r14 $r4 0x104 186 call(nv_wr32) // ENTRY 187 add b32 $r14 $r4 0x100 188 mov $r15 2 // CTRL_START_TRIGGER 189 call(nv_wr32) // CTRL 190 191 // wait for it to complete, and adjust context size 192 add b32 $r14 $r4 0x800 193 init_gpc_wait: 194 call(nv_rd32) 195 xbit $r15 $r15 31 196 bra e #init_gpc_wait 197 add b32 $r14 $r4 0x804 198 call(nv_rd32) 199 add b32 $r1 $r15 200 201 // next! 202 add b32 $r4 0x8000 203 sub b32 $r3 1 204 bra ne #init_gpc 205 206 // 207 mov $r15 0 208 call(ctx_86c) 209 mov $r15 0 210 call(ctx_4170s) 211 212 // save context size, and tell host we're ready 213 nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(1), 0, $r1) 214 clear b32 $r1 215 bset $r1 31 216 nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_SET(0), 0, $r1) 217 218// Main program loop, very simple, sleeps until woken up by the interrupt 219// handler, pulls a command from the queue and executes its handler 220// 221main: 222 // sleep until we have something to do 223 bset $flags $p0 224 sleep $p0 225 mov $r13 #cmd_queue 226 call(queue_get) 227 bra $p1 #main 228 229 // context switch, requested by GPU? 230 cmpu b32 $r14 0x4001 231 bra ne #main_not_ctx_switch 232 trace_set(T_AUTO) 233 nv_iord($r1, NV_PGRAPH_FECS_CHAN_ADDR, 0) 234 nv_iord($r2, NV_PGRAPH_FECS_CHAN_NEXT, 0) 235 236 xbit $r3 $r1 31 237 bra e #chsw_no_prev 238 xbit $r3 $r2 31 239 bra e #chsw_prev_no_next 240 push $r2 241 mov b32 $r2 $r1 242 trace_set(T_SAVE) 243 bclr $flags $p1 244 bset $flags $p2 245 call(ctx_xfer) 246 trace_clr(T_SAVE); 247 pop $r2 248 trace_set(T_LOAD); 249 bset $flags $p1 250 call(ctx_xfer) 251 trace_clr(T_LOAD); 252 bra #chsw_done 253 chsw_prev_no_next: 254 push $r2 255 mov b32 $r2 $r1 256 bclr $flags $p1 257 bclr $flags $p2 258 call(ctx_xfer) 259 pop $r2 260 nv_iowr(NV_PGRAPH_FECS_CHAN_ADDR, 0, $r2) 261 bra #chsw_done 262 chsw_no_prev: 263 xbit $r3 $r2 31 264 bra e #chsw_done 265 bset $flags $p1 266 bclr $flags $p2 267 call(ctx_xfer) 268 269 // ack the context switch request 270 chsw_done: 271 mov $r2 NV_PGRAPH_FECS_CHSW_ACK 272 nv_iowr(NV_PGRAPH_FECS_CHSW, 0, $r2) 273 trace_clr(T_AUTO) 274 bra #main 275 276 // request to set current channel? (*not* a context switch) 277 main_not_ctx_switch: 278 cmpu b32 $r14 0x0001 279 bra ne #main_not_ctx_chan 280 mov b32 $r2 $r15 281 call(ctx_chan) 282 bra #main_done 283 284 // request to store current channel context? 285 main_not_ctx_chan: 286 cmpu b32 $r14 0x0002 287 bra ne #main_not_ctx_save 288 trace_set(T_SAVE) 289 bclr $flags $p1 290 bclr $flags $p2 291 call(ctx_xfer) 292 trace_clr(T_SAVE) 293 bra #main_done 294 295 main_not_ctx_save: 296 shl b32 $r15 $r14 16 297 or $r15 E_BAD_COMMAND 298 call(error) 299 bra #main 300 301 main_done: 302 clear b32 $r2 303 bset $r2 31 304 nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_SET(0), 0, $r2) 305 bra #main 306 307// interrupt handler 308ih: 309 push $r8 310 mov $r8 $flags 311 push $r8 312 push $r9 313 push $r10 314 push $r11 315 push $r13 316 push $r14 317 push $r15 318 clear b32 $r0 319 320 // incoming fifo command? 321 nv_iord($r10, NV_PGRAPH_FECS_INTR, 0) 322 and $r11 $r10 NV_PGRAPH_FECS_INTR_FIFO 323 bra e #ih_no_fifo 324 // queue incoming fifo command for later processing 325 mov $r13 #cmd_queue 326 nv_iord($r14, NV_PGRAPH_FECS_FIFO_CMD, 0) 327 nv_iord($r15, NV_PGRAPH_FECS_FIFO_DATA, 0) 328 call(queue_put) 329 add b32 $r11 0x400 330 mov $r14 1 331 nv_iowr(NV_PGRAPH_FECS_FIFO_ACK, 0, $r14) 332 333 // context switch request? 334 ih_no_fifo: 335 and $r11 $r10 NV_PGRAPH_FECS_INTR_CHSW 336 bra e #ih_no_ctxsw 337 // enqueue a context switch for later processing 338 mov $r13 #cmd_queue 339 mov $r14 0x4001 340 call(queue_put) 341 342 // firmware method? 343 ih_no_ctxsw: 344 and $r11 $r10 NV_PGRAPH_FECS_INTR_FWMTHD 345 bra e #ih_no_fwmthd 346 // none we handle; report to host and ack 347 nv_rd32($r15, NV_PGRAPH_TRAPPED_DATA_LO) 348 nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(4), 0, $r15) 349 nv_rd32($r15, NV_PGRAPH_TRAPPED_ADDR) 350 nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(3), 0, $r15) 351 extr $r14 $r15 16:18 352 shl b32 $r14 $r14 2 353 imm32($r15, NV_PGRAPH_FE_OBJECT_TABLE(0)) 354 add b32 $r14 $r15 355 call(nv_rd32) 356 nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(2), 0, $r15) 357 mov $r15 E_BAD_FWMTHD 358 call(error) 359 mov $r11 0x100 360 nv_wr32(0x400144, $r11) 361 362 // anything we didn't handle, bring it to the host's attention 363 ih_no_fwmthd: 364 mov $r11 0x504 // FIFO | CHSW | FWMTHD 365 not b32 $r11 366 and $r11 $r10 $r11 367 bra e #ih_no_other 368 nv_iowr(NV_PGRAPH_FECS_INTR_UP_SET, 0, $r11) 369 370 // ack, and wake up main() 371 ih_no_other: 372 nv_iowr(NV_PGRAPH_FECS_INTR_ACK, 0, $r10) 373 374 pop $r15 375 pop $r14 376 pop $r13 377 pop $r11 378 pop $r10 379 pop $r9 380 pop $r8 381 mov $flags $r8 382 pop $r8 383 bclr $flags $p0 384 iret 385 386#if CHIPSET < GK100 387// Not real sure, but, MEM_CMD 7 will hang forever if this isn't done 388ctx_4160s: 389 mov $r15 1 390 nv_wr32(0x404160, $r15) 391 ctx_4160s_wait: 392 nv_rd32($r15, 0x404160) 393 xbit $r15 $r15 4 394 bra e #ctx_4160s_wait 395 ret 396 397// Without clearing again at end of xfer, some things cause PGRAPH 398// to hang with STATUS=0x00000007 until it's cleared.. fbcon can 399// still function with it set however... 400ctx_4160c: 401 clear b32 $r15 402 nv_wr32(0x404160, $r15) 403 ret 404#endif 405 406// Again, not real sure 407// 408// In: $r15 value to set 0x404170 to 409// 410ctx_4170s: 411 or $r15 0x10 412 nv_wr32(0x404170, $r15) 413 ret 414 415// Waits for a ctx_4170s() call to complete 416// 417ctx_4170w: 418 nv_rd32($r15, 0x404170) 419 and $r15 0x10 420 bra ne #ctx_4170w 421 ret 422 423// Disables various things, waits a bit, and re-enables them.. 424// 425// Not sure how exactly this helps, perhaps "ENABLE" is not such a 426// good description for the bits we turn off? Anyways, without this, 427// funny things happen. 428// 429ctx_redswitch: 430 mov $r14 NV_PGRAPH_FECS_RED_SWITCH_ENABLE_GPC 431 or $r14 NV_PGRAPH_FECS_RED_SWITCH_POWER_ROP 432 or $r14 NV_PGRAPH_FECS_RED_SWITCH_POWER_GPC 433 or $r14 NV_PGRAPH_FECS_RED_SWITCH_POWER_MAIN 434 nv_iowr(NV_PGRAPH_FECS_RED_SWITCH, 0, $r14) 435 mov $r15 8 436 ctx_redswitch_delay: 437 sub b32 $r15 1 438 bra ne #ctx_redswitch_delay 439 or $r14 NV_PGRAPH_FECS_RED_SWITCH_ENABLE_ROP 440 or $r14 NV_PGRAPH_FECS_RED_SWITCH_ENABLE_MAIN 441 nv_iowr(NV_PGRAPH_FECS_RED_SWITCH, 0, $r14) 442 ret 443 444// Not a clue what this is for, except that unless the value is 0x10, the 445// strand context is saved (and presumably restored) incorrectly.. 446// 447// In: $r15 value to set to (0x00/0x10 are used) 448// 449ctx_86c: 450 nv_iowr(NV_PGRAPH_FECS_UNK86C, 0, $r15) 451 nv_wr32(0x408a14, $r15) 452 nv_wr32(NV_PGRAPH_GPCX_GPCCS_UNK86C, $r15) 453 ret 454 455// In: $r15 NV_PGRAPH_FECS_MEM_CMD_* 456ctx_mem: 457 nv_iowr(NV_PGRAPH_FECS_MEM_CMD, 0, $r15) 458 ctx_mem_wait: 459 nv_iord($r15, NV_PGRAPH_FECS_MEM_CMD, 0) 460 or $r15 $r15 461 bra ne #ctx_mem_wait 462 ret 463 464// ctx_load - load's a channel's ctxctl data, and selects its vm 465// 466// In: $r2 channel address 467// 468ctx_load: 469 trace_set(T_CHAN) 470 471 // switch to channel, somewhat magic in parts.. 472 mov $r10 12 // DONE_UNK12 473 call(wait_donez) 474 clear b32 $r15 475 nv_iowr(0x409a24, 0, $r15) 476 nv_iowr(NV_PGRAPH_FECS_CHAN_NEXT, 0, $r2) 477 nv_iowr(NV_PGRAPH_FECS_MEM_CHAN, 0, $r2) 478 mov $r15 NV_PGRAPH_FECS_MEM_CMD_LOAD_CHAN 479 call(ctx_mem) 480 nv_iowr(NV_PGRAPH_FECS_CHAN_ADDR, 0, $r2) 481 482 // load channel header, fetch PGRAPH context pointer 483 mov $xtargets $r0 484 bclr $r2 31 485 shl b32 $r2 4 486 add b32 $r2 2 487 488 trace_set(T_LCHAN) 489 nv_iowr(NV_PGRAPH_FECS_MEM_BASE, 0, $r2) 490 imm32($r2, NV_PGRAPH_FECS_MEM_TARGET_UNK31) 491 or $r2 NV_PGRAPH_FECS_MEM_TARGET_AS_VRAM 492 nv_iowr(NV_PGRAPH_FECS_MEM_TARGET, 0, $r2) 493 mov $r1 0x10 // chan + 0x0210 494 mov $r2 #xfer_data 495 sethi $r2 0x00020000 // 16 bytes 496 xdld $r1 $r2 497 xdwait 498 trace_clr(T_LCHAN) 499 500 // update current context 501 ld b32 $r1 D[$r0 + #xfer_data + 4] 502 shl b32 $r1 24 503 ld b32 $r2 D[$r0 + #xfer_data + 0] 504 shr b32 $r2 8 505 or $r1 $r2 506 st b32 D[$r0 + #ctx_current] $r1 507 508 // set transfer base to start of context, and fetch context header 509 trace_set(T_LCTXH) 510 nv_iowr(NV_PGRAPH_FECS_MEM_BASE, 0, $r1) 511 mov $r2 NV_PGRAPH_FECS_MEM_TARGET_AS_VM 512 nv_iowr(NV_PGRAPH_FECS_MEM_TARGET, 0, $r2) 513 mov $r1 #chan_data 514 sethi $r1 0x00060000 // 256 bytes 515 xdld $r0 $r1 516 xdwait 517 trace_clr(T_LCTXH) 518 519 trace_clr(T_CHAN) 520 ret 521 522// ctx_chan - handler for HUB_SET_CHAN command, will set a channel as 523// the active channel for ctxctl, but not actually transfer 524// any context data. intended for use only during initial 525// context construction. 526// 527// In: $r2 channel address 528// 529ctx_chan: 530#if CHIPSET < GK100 531 call(ctx_4160s) 532#endif 533 call(ctx_load) 534 mov $r10 12 // DONE_UNK12 535 call(wait_donez) 536 mov $r15 5 // MEM_CMD 5 ??? 537 call(ctx_mem) 538#if CHIPSET < GK100 539 call(ctx_4160c) 540#endif 541 ret 542 543// Execute per-context state overrides list 544// 545// Only executed on the first load of a channel. Might want to look into 546// removing this and having the host directly modify the channel's context 547// to change this state... The nouveau DRM already builds this list as 548// it's definitely needed for NVIDIA's, so we may as well use it for now 549// 550// Input: $r1 mmio list length 551// 552ctx_mmio_exec: 553 // set transfer base to be the mmio list 554 ld b32 $r3 D[$r0 + #chan_mmio_address] 555 nv_iowr(NV_PGRAPH_FECS_MEM_BASE, 0, $r3) 556 557 clear b32 $r3 558 ctx_mmio_loop: 559 // fetch next 256 bytes of mmio list if necessary 560 and $r4 $r3 0xff 561 bra ne #ctx_mmio_pull 562 mov $r5 #xfer_data 563 sethi $r5 0x00060000 // 256 bytes 564 xdld $r3 $r5 565 xdwait 566 567 // execute a single list entry 568 ctx_mmio_pull: 569 ld b32 $r14 D[$r4 + #xfer_data + 0x00] 570 ld b32 $r15 D[$r4 + #xfer_data + 0x04] 571 call(nv_wr32) 572 573 // next! 574 add b32 $r3 8 575 sub b32 $r1 1 576 bra ne #ctx_mmio_loop 577 578 // set transfer base back to the current context 579 ctx_mmio_done: 580 ld b32 $r3 D[$r0 + #ctx_current] 581 nv_iowr(NV_PGRAPH_FECS_MEM_BASE, 0, $r3) 582 583 // disable the mmio list now, we don't need/want to execute it again 584 st b32 D[$r0 + #chan_mmio_count] $r0 585 mov $r1 #chan_data 586 sethi $r1 0x00060000 // 256 bytes 587 xdst $r0 $r1 588 xdwait 589 ret 590 591// Transfer HUB context data between GPU and storage area 592// 593// In: $r2 channel address 594// $p1 clear on save, set on load 595// $p2 set if opposite direction done/will be done, so: 596// on save it means: "a load will follow this save" 597// on load it means: "a save preceeded this load" 598// 599ctx_xfer: 600 // according to mwk, some kind of wait for idle 601 mov $r14 4 602 nv_iowr(0x409c08, 0, $r14) 603 ctx_xfer_idle: 604 nv_iord($r14, 0x409c00, 0) 605 and $r14 0x2000 606 bra ne #ctx_xfer_idle 607 608 bra not $p1 #ctx_xfer_pre 609 bra $p2 #ctx_xfer_pre_load 610 ctx_xfer_pre: 611 mov $r15 0x10 612 call(ctx_86c) 613#if CHIPSET < GK100 614 call(ctx_4160s) 615#endif 616 bra not $p1 #ctx_xfer_exec 617 618 ctx_xfer_pre_load: 619 mov $r15 2 620 call(ctx_4170s) 621 call(ctx_4170w) 622 call(ctx_redswitch) 623 clear b32 $r15 624 call(ctx_4170s) 625 call(ctx_load) 626 627 // fetch context pointer, and initiate xfer on all GPCs 628 ctx_xfer_exec: 629 ld b32 $r1 D[$r0 + #ctx_current] 630 631 clear b32 $r2 632 nv_iowr(NV_PGRAPH_FECS_BAR, 0, $r2) 633 634 nv_wr32(0x41a500, $r1) // GPC_BCAST_WRCMD_DATA = ctx pointer 635 xbit $r15 $flags $p1 636 xbit $r2 $flags $p2 637 shl b32 $r2 1 638 or $r15 $r2 639 nv_wr32(0x41a504, $r15) // GPC_BCAST_WRCMD_CMD = GPC_XFER(type) 640 641 // strands 642 call(strand_pre) 643 clear b32 $r2 644 nv_iowr(NV_PGRAPH_FECS_STRAND_SELECT, 0x3f, $r2) 645 xbit $r2 $flags $p1 // SAVE/LOAD 646 add b32 $r2 NV_PGRAPH_FECS_STRAND_CMD_SAVE 647 nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r2) 648 649 // mmio context 650 xbit $r10 $flags $p1 // direction 651 or $r10 6 // first, last 652 mov $r11 0 // base = 0 653 ld b32 $r12 D[$r0 + #hub_mmio_list_head] 654 ld b32 $r13 D[$r0 + #hub_mmio_list_tail] 655 mov $r14 0 // not multi 656 call(mmctx_xfer) 657 658 // wait for GPCs to all complete 659 mov $r10 8 // DONE_BAR 660 call(wait_doneo) 661 662 // wait for strand xfer to complete 663 call(strand_wait) 664 665 // post-op 666 bra $p1 #ctx_xfer_post 667 mov $r10 12 // DONE_UNK12 668 call(wait_donez) 669 mov $r15 5 // MEM_CMD 5 ??? 670 call(ctx_mem) 671 672 bra $p2 #ctx_xfer_done 673 ctx_xfer_post: 674 mov $r15 2 675 call(ctx_4170s) 676 clear b32 $r15 677 call(ctx_86c) 678 call(strand_post) 679 call(ctx_4170w) 680 clear b32 $r15 681 call(ctx_4170s) 682 683 bra not $p1 #ctx_xfer_no_post_mmio 684 ld b32 $r1 D[$r0 + #chan_mmio_count] 685 or $r1 $r1 686 bra e #ctx_xfer_no_post_mmio 687 call(ctx_mmio_exec) 688 689 ctx_xfer_no_post_mmio: 690#if CHIPSET < GK100 691 call(ctx_4160c) 692#endif 693 694 ctx_xfer_done: 695 ret 696#endif 697