xref: /linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hub.fuc (revision 0d08df6c493898e679d9c517e77ea95c063d40ec) 
1/* fuc microcode for gf100 PGRAPH/HUB
2 *
3 * Copyright 2011 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Ben Skeggs
24 */
25
26#ifdef INCLUDE_DATA
27hub_mmio_list_head:	.b32 #hub_mmio_list_base
28hub_mmio_list_tail:	.b32 #hub_mmio_list_next
29
30gpc_count:		.b32 0
31rop_count:		.b32 0
32cmd_queue:		queue_init
33
34ctx_current:		.b32 0
35
36.align 256
37chan_data:
38chan_mmio_count:	.b32 0
39chan_mmio_address:	.b32 0
40
41.align 256
42xfer_data: 		.skip 256
43
44hub_mmio_list_base:
45.b32 0x0417e91c // 0x17e91c, 2
46hub_mmio_list_next:
47#endif
48
49#ifdef INCLUDE_CODE
50// reports an exception to the host
51//
52// In: $r15 error code (see os.h)
53//
54error:
55	nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(5), 0, $r15)
56	mov $r15 1
57	nv_iowr(NV_PGRAPH_FECS_INTR_UP_SET, 0, $r15)
58	ret
59
60// HUB fuc initialisation, executed by triggering ucode start, will
61// fall through to main loop after completion.
62//
63// Output:
64//   CC_SCRATCH[0]:
65//	     31:31: set to signal completion
66//   CC_SCRATCH[1]:
67//	      31:0: total PGRAPH context size
68//
69init:
70	clear b32 $r0
71	mov $xdbase $r0
72
73	// setup stack
74	nv_iord($r1, NV_PGRAPH_FECS_CAPS, 0)
75	extr $r1 $r1 9:17
76	shl b32 $r1 8
77	mov $sp $r1
78
79	// enable fifo access
80	mov $r2 NV_PGRAPH_FECS_ACCESS_FIFO
81	nv_iowr(NV_PGRAPH_FECS_ACCESS, 0, $r2)
82
83	// setup i0 handler, and route all interrupts to it
84	mov $r1 #ih
85	mov $iv0 $r1
86
87	clear b32 $r2
88	nv_iowr(NV_PGRAPH_FECS_INTR_ROUTE, 0, $r2)
89
90	// route HUB_CHSW_PULSE to fuc interrupt 8
91	mov $r2 0x2003		// { HUB_CHSW_PULSE, ZERO } -> intr 8
92	nv_iowr(NV_PGRAPH_FECS_IROUTE, 0, $r2)
93
94	// not sure what these are, route them because NVIDIA does, and
95	// the IRQ handler will signal the host if we ever get one.. we
96	// may find out if/why we need to handle these if so..
97	//
98	mov $r2 0x2004		// { 0x04, ZERO } -> intr 9
99	nv_iowr(NV_PGRAPH_FECS_IROUTE, 1, $r2)
100	mov $r2 0x200b		// { HUB_FIRMWARE_MTHD, ZERO } -> intr 10
101	nv_iowr(NV_PGRAPH_FECS_IROUTE, 2, $r2)
102	mov $r2 0x200c		// { 0x0c, ZERO } -> intr 15
103	nv_iowr(NV_PGRAPH_FECS_IROUTE, 7, $r2)
104
105	// enable all INTR_UP interrupts
106	sub b32 $r3 $r0 1
107	nv_iowr(NV_PGRAPH_FECS_INTR_UP_EN, 0, $r3)
108
109	// enable fifo, ctxsw, 9, fwmthd, 15 interrupts
110	imm32($r2, 0x8704)
111	nv_iowr(NV_PGRAPH_FECS_INTR_EN_SET, 0, $r2)
112
113	// fifo level triggered, rest edge
114	mov $r2 NV_PGRAPH_FECS_INTR_MODE_FIFO_LEVEL
115	nv_iowr(NV_PGRAPH_FECS_INTR_MODE, 0, $r2)
116
117	// enable interrupts
118	bset $flags ie0
119
120	// fetch enabled GPC/ROP counts
121	nv_rd32($r14, 0x409604)
122	extr $r1 $r15 16:20
123	st b32 D[$r0 + #rop_count] $r1
124	and $r15 0x1f
125	st b32 D[$r0 + #gpc_count] $r15
126
127	// set BAR_REQMASK to GPC mask
128	mov $r1 1
129	shl b32 $r1 $r15
130	sub b32 $r1 1
131	nv_iowr(NV_PGRAPH_FECS_BAR_MASK0, 0, $r1)
132	nv_iowr(NV_PGRAPH_FECS_BAR_MASK1, 0, $r1)
133
134	// context size calculation, reserve first 256 bytes for use by fuc
135	mov $r1 256
136
137	//
138	mov $r15 2
139	call(ctx_4170s)
140	call(ctx_4170w)
141	mov $r15 0x10
142	call(ctx_86c)
143
144	// calculate size of mmio context data
145	ld b32 $r14 D[$r0 + #hub_mmio_list_head]
146	ld b32 $r15 D[$r0 + #hub_mmio_list_tail]
147	call(mmctx_size)
148
149	// set mmctx base addresses now so we don't have to do it later,
150	// they don't (currently) ever change
151	shr b32 $r4 $r1 8
152	nv_iowr(NV_PGRAPH_FECS_MMCTX_SAVE_SWBASE, 0, $r4)
153	nv_iowr(NV_PGRAPH_FECS_MMCTX_LOAD_SWBASE, 0, $r4)
154	add b32 $r3 0x1300
155	add b32 $r1 $r15
156	shr b32 $r15 2
157	nv_iowr(NV_PGRAPH_FECS_MMCTX_LOAD_COUNT, 0, $r15) // wtf??
158
159	// strands, base offset needs to be aligned to 256 bytes
160	shr b32 $r1 8
161	add b32 $r1 1
162	shl b32 $r1 8
163	mov b32 $r15 $r1
164	call(strand_ctx_init)
165	add b32 $r1 $r15
166
167	// initialise each GPC in sequence by passing in the offset of its
168	// context data in GPCn_CC_SCRATCH[1], and starting its FUC (which
169	// has previously been uploaded by the host) running.
170	//
171	// the GPC fuc init sequence will set GPCn_CC_SCRATCH[0] bit 31
172	// when it has completed, and return the size of its context data
173	// in GPCn_CC_SCRATCH[1]
174	//
175	ld b32 $r3 D[$r0 + #gpc_count]
176	imm32($r4, 0x502000)
177	init_gpc:
178		// setup, and start GPC ucode running
179		add b32 $r14 $r4 0x804
180		mov b32 $r15 $r1
181		call(nv_wr32)			// CC_SCRATCH[1] = ctx offset
182		add b32 $r14 $r4 0x10c
183		clear b32 $r15
184		call(nv_wr32)
185		add b32 $r14 $r4 0x104
186		call(nv_wr32)			// ENTRY
187		add b32 $r14 $r4 0x100
188		mov $r15 2			// CTRL_START_TRIGGER
189		call(nv_wr32)			// CTRL
190
191		// wait for it to complete, and adjust context size
192		add b32 $r14 $r4 0x800
193		init_gpc_wait:
194			call(nv_rd32)
195			xbit $r15 $r15 31
196			bra e #init_gpc_wait
197		add b32 $r14 $r4 0x804
198		call(nv_rd32)
199		add b32 $r1 $r15
200
201		// next!
202		add b32 $r4 0x8000
203		sub b32 $r3 1
204		bra ne #init_gpc
205
206	//
207	mov $r15 0
208	call(ctx_86c)
209	mov $r15 0
210	call(ctx_4170s)
211
212	// save context size, and tell host we're ready
213	nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(1), 0, $r1)
214	clear b32 $r1
215	bset $r1 31
216	nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_SET(0), 0, $r1)
217
218// Main program loop, very simple, sleeps until woken up by the interrupt
219// handler, pulls a command from the queue and executes its handler
220//
221main:
222	// sleep until we have something to do
223	bset $flags $p0
224	sleep $p0
225	mov $r13 #cmd_queue
226	call(queue_get)
227	bra $p1 #main
228
229	// context switch, requested by GPU?
230	cmpu b32 $r14 0x4001
231	bra ne #main_not_ctx_switch
232		trace_set(T_AUTO)
233		nv_iord($r1, NV_PGRAPH_FECS_CHAN_ADDR, 0)
234		nv_iord($r2, NV_PGRAPH_FECS_CHAN_NEXT, 0)
235
236		xbit $r3 $r1 31
237		bra e #chsw_no_prev
238			xbit $r3 $r2 31
239			bra e #chsw_prev_no_next
240				push $r2
241				mov b32 $r2 $r1
242				trace_set(T_SAVE)
243				bclr $flags $p1
244				bset $flags $p2
245				call(ctx_xfer)
246				trace_clr(T_SAVE);
247				pop $r2
248				trace_set(T_LOAD);
249				bset $flags $p1
250				call(ctx_xfer)
251				trace_clr(T_LOAD);
252				bra #chsw_done
253			chsw_prev_no_next:
254				push $r2
255				mov b32 $r2 $r1
256				bclr $flags $p1
257				bclr $flags $p2
258				call(ctx_xfer)
259				pop $r2
260				nv_iowr(NV_PGRAPH_FECS_CHAN_ADDR, 0, $r2)
261				bra #chsw_done
262		chsw_no_prev:
263			xbit $r3 $r2 31
264			bra e #chsw_done
265				bset $flags $p1
266				bclr $flags $p2
267				call(ctx_xfer)
268
269		// ack the context switch request
270		chsw_done:
271		mov $r2 NV_PGRAPH_FECS_CHSW_ACK
272		nv_iowr(NV_PGRAPH_FECS_CHSW, 0, $r2)
273		trace_clr(T_AUTO)
274		bra #main
275
276	// request to set current channel? (*not* a context switch)
277	main_not_ctx_switch:
278	cmpu b32 $r14 0x0001
279	bra ne #main_not_ctx_chan
280		mov b32 $r2 $r15
281		call(ctx_chan)
282		bra #main_done
283
284	// request to store current channel context?
285	main_not_ctx_chan:
286	cmpu b32 $r14 0x0002
287	bra ne #main_not_ctx_save
288		trace_set(T_SAVE)
289		bclr $flags $p1
290		bclr $flags $p2
291		call(ctx_xfer)
292		trace_clr(T_SAVE)
293		bra #main_done
294
295	main_not_ctx_save:
296		shl b32 $r15 $r14 16
297		or $r15 E_BAD_COMMAND
298		call(error)
299		bra #main
300
301	main_done:
302	clear b32 $r2
303	bset $r2 31
304	nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_SET(0), 0, $r2)
305	bra #main
306
307// interrupt handler
308ih:
309	push $r0
310	push $r8
311	mov $r8 $flags
312	push $r8
313	push $r9
314	push $r10
315	push $r11
316	push $r13
317	push $r14
318	push $r15
319	clear b32 $r0
320
321	// incoming fifo command?
322	nv_iord($r10, NV_PGRAPH_FECS_INTR, 0)
323	and $r11 $r10 NV_PGRAPH_FECS_INTR_FIFO
324	bra e #ih_no_fifo
325		// queue incoming fifo command for later processing
326		mov $r13 #cmd_queue
327		nv_iord($r14, NV_PGRAPH_FECS_FIFO_CMD, 0)
328		nv_iord($r15, NV_PGRAPH_FECS_FIFO_DATA, 0)
329		call(queue_put)
330		add b32 $r11 0x400
331		mov $r14 1
332		nv_iowr(NV_PGRAPH_FECS_FIFO_ACK, 0, $r14)
333
334	// context switch request?
335	ih_no_fifo:
336	and $r11 $r10 NV_PGRAPH_FECS_INTR_CHSW
337	bra e #ih_no_ctxsw
338		// enqueue a context switch for later processing
339		mov $r13 #cmd_queue
340		mov $r14 0x4001
341		call(queue_put)
342
343	// firmware method?
344	ih_no_ctxsw:
345	and $r11 $r10 NV_PGRAPH_FECS_INTR_FWMTHD
346	bra e #ih_no_fwmthd
347		// none we handle; report to host and ack
348		nv_rd32($r15, NV_PGRAPH_TRAPPED_DATA_LO)
349		nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(4), 0, $r15)
350		nv_rd32($r15, NV_PGRAPH_TRAPPED_ADDR)
351		nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(3), 0, $r15)
352		extr $r14 $r15 16:18
353		shl b32 $r14 $r14 2
354		imm32($r15, NV_PGRAPH_FE_OBJECT_TABLE(0))
355		add b32 $r14 $r15
356		call(nv_rd32)
357		nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(2), 0, $r15)
358		mov $r15 E_BAD_FWMTHD
359		call(error)
360		mov $r11 0x100
361		nv_wr32(0x400144, $r11)
362
363	// anything we didn't handle, bring it to the host's attention
364	ih_no_fwmthd:
365	mov $r11 0x504 // FIFO | CHSW | FWMTHD
366	not b32 $r11
367	and $r11 $r10 $r11
368	bra e #ih_no_other
369		nv_iowr(NV_PGRAPH_FECS_INTR_UP_SET, 0, $r11)
370
371	// ack, and wake up main()
372	ih_no_other:
373	nv_iowr(NV_PGRAPH_FECS_INTR_ACK, 0, $r10)
374
375	pop $r15
376	pop $r14
377	pop $r13
378	pop $r11
379	pop $r10
380	pop $r9
381	pop $r8
382	mov $flags $r8
383	pop $r8
384	pop $r0
385	bclr $flags $p0
386	iret
387
388#if CHIPSET < GK100
389// Not real sure, but, MEM_CMD 7 will hang forever if this isn't done
390ctx_4160s:
391	mov $r15 1
392	nv_wr32(0x404160, $r15)
393	ctx_4160s_wait:
394		nv_rd32($r15, 0x404160)
395		xbit $r15 $r15 4
396		bra e #ctx_4160s_wait
397	ret
398
399// Without clearing again at end of xfer, some things cause PGRAPH
400// to hang with STATUS=0x00000007 until it's cleared.. fbcon can
401// still function with it set however...
402ctx_4160c:
403	clear b32 $r15
404	nv_wr32(0x404160, $r15)
405	ret
406#endif
407
408// Again, not real sure
409//
410// In: $r15 value to set 0x404170 to
411//
412ctx_4170s:
413	or $r15 0x10
414	nv_wr32(0x404170, $r15)
415	ret
416
417// Waits for a ctx_4170s() call to complete
418//
419ctx_4170w:
420	nv_rd32($r15, 0x404170)
421	and $r15 0x10
422	bra ne #ctx_4170w
423	ret
424
425// Disables various things, waits a bit, and re-enables them..
426//
427// Not sure how exactly this helps, perhaps "ENABLE" is not such a
428// good description for the bits we turn off?  Anyways, without this,
429// funny things happen.
430//
431ctx_redswitch:
432	mov $r14 NV_PGRAPH_FECS_RED_SWITCH_ENABLE_GPC
433	or  $r14 NV_PGRAPH_FECS_RED_SWITCH_POWER_ROP
434	or  $r14 NV_PGRAPH_FECS_RED_SWITCH_POWER_GPC
435	or  $r14 NV_PGRAPH_FECS_RED_SWITCH_POWER_MAIN
436	nv_iowr(NV_PGRAPH_FECS_RED_SWITCH, 0, $r14)
437	mov $r15 8
438	ctx_redswitch_delay:
439		sub b32 $r15 1
440		bra ne #ctx_redswitch_delay
441	or  $r14 NV_PGRAPH_FECS_RED_SWITCH_ENABLE_ROP
442	or  $r14 NV_PGRAPH_FECS_RED_SWITCH_ENABLE_MAIN
443	nv_iowr(NV_PGRAPH_FECS_RED_SWITCH, 0, $r14)
444	ret
445
446// Not a clue what this is for, except that unless the value is 0x10, the
447// strand context is saved (and presumably restored) incorrectly..
448//
449// In: $r15 value to set to (0x00/0x10 are used)
450//
451ctx_86c:
452	nv_iowr(NV_PGRAPH_FECS_UNK86C, 0, $r15)
453	nv_wr32(0x408a14, $r15)
454	nv_wr32(NV_PGRAPH_GPCX_GPCCS_UNK86C, $r15)
455	ret
456
457// In: $r15 NV_PGRAPH_FECS_MEM_CMD_*
458ctx_mem:
459	nv_iowr(NV_PGRAPH_FECS_MEM_CMD, 0, $r15)
460	ctx_mem_wait:
461		nv_iord($r15, NV_PGRAPH_FECS_MEM_CMD, 0)
462		or $r15 $r15
463		bra ne #ctx_mem_wait
464	ret
465
466// ctx_load - load's a channel's ctxctl data, and selects its vm
467//
468// In: $r2 channel address
469//
470ctx_load:
471	trace_set(T_CHAN)
472
473	// switch to channel, somewhat magic in parts..
474	mov $r10 12		// DONE_UNK12
475	call(wait_donez)
476	clear b32 $r15
477	nv_iowr(0x409a24, 0, $r15)
478	nv_iowr(NV_PGRAPH_FECS_CHAN_NEXT, 0, $r2)
479	nv_iowr(NV_PGRAPH_FECS_MEM_CHAN, 0, $r2)
480	mov $r15 NV_PGRAPH_FECS_MEM_CMD_LOAD_CHAN
481	call(ctx_mem)
482	nv_iowr(NV_PGRAPH_FECS_CHAN_ADDR, 0, $r2)
483
484	// load channel header, fetch PGRAPH context pointer
485	mov $xtargets $r0
486	bclr $r2 31
487	shl b32 $r2 4
488	add b32 $r2 2
489
490	trace_set(T_LCHAN)
491	nv_iowr(NV_PGRAPH_FECS_MEM_BASE, 0, $r2)
492	imm32($r2, NV_PGRAPH_FECS_MEM_TARGET_UNK31)
493	or  $r2 NV_PGRAPH_FECS_MEM_TARGET_AS_VRAM
494	nv_iowr(NV_PGRAPH_FECS_MEM_TARGET, 0, $r2)
495	mov $r1 0x10			// chan + 0x0210
496	mov $r2 #xfer_data
497	sethi $r2 0x00020000		// 16 bytes
498	xdld $r1 $r2
499	xdwait
500	trace_clr(T_LCHAN)
501
502	// update current context
503	ld b32 $r1 D[$r0 + #xfer_data + 4]
504	shl b32 $r1 24
505	ld b32 $r2 D[$r0 + #xfer_data + 0]
506	shr b32 $r2 8
507	or $r1 $r2
508	st b32 D[$r0 + #ctx_current] $r1
509
510	// set transfer base to start of context, and fetch context header
511	trace_set(T_LCTXH)
512	nv_iowr(NV_PGRAPH_FECS_MEM_BASE, 0, $r1)
513	mov $r2 NV_PGRAPH_FECS_MEM_TARGET_AS_VM
514	nv_iowr(NV_PGRAPH_FECS_MEM_TARGET, 0, $r2)
515	mov $r1 #chan_data
516	sethi $r1 0x00060000		// 256 bytes
517	xdld $r0 $r1
518	xdwait
519	trace_clr(T_LCTXH)
520
521	trace_clr(T_CHAN)
522	ret
523
524// ctx_chan - handler for HUB_SET_CHAN command, will set a channel as
525//            the active channel for ctxctl, but not actually transfer
526//            any context data.  intended for use only during initial
527//            context construction.
528//
529// In: $r2 channel address
530//
531ctx_chan:
532#if CHIPSET < GK100
533	call(ctx_4160s)
534#endif
535	call(ctx_load)
536	mov $r10 12			// DONE_UNK12
537	call(wait_donez)
538	mov $r15 5 // MEM_CMD 5 ???
539	call(ctx_mem)
540#if CHIPSET < GK100
541	call(ctx_4160c)
542#endif
543	ret
544
545// Execute per-context state overrides list
546//
547// Only executed on the first load of a channel.  Might want to look into
548// removing this and having the host directly modify the channel's context
549// to change this state...  The nouveau DRM already builds this list as
550// it's definitely needed for NVIDIA's, so we may as well use it for now
551//
552// Input: $r1 mmio list length
553//
554ctx_mmio_exec:
555	// set transfer base to be the mmio list
556	ld b32 $r3 D[$r0 + #chan_mmio_address]
557	nv_iowr(NV_PGRAPH_FECS_MEM_BASE, 0, $r3)
558
559	clear b32 $r3
560	ctx_mmio_loop:
561		// fetch next 256 bytes of mmio list if necessary
562		and $r4 $r3 0xff
563		bra ne #ctx_mmio_pull
564			mov $r5 #xfer_data
565			sethi $r5 0x00060000	// 256 bytes
566			xdld $r3 $r5
567			xdwait
568
569		// execute a single list entry
570		ctx_mmio_pull:
571		ld b32 $r14 D[$r4 + #xfer_data + 0x00]
572		ld b32 $r15 D[$r4 + #xfer_data + 0x04]
573		call(nv_wr32)
574
575		// next!
576		add b32 $r3 8
577		sub b32 $r1 1
578		bra ne #ctx_mmio_loop
579
580	// set transfer base back to the current context
581	ctx_mmio_done:
582	ld b32 $r3 D[$r0 + #ctx_current]
583	nv_iowr(NV_PGRAPH_FECS_MEM_BASE, 0, $r3)
584
585	// disable the mmio list now, we don't need/want to execute it again
586	st b32 D[$r0 + #chan_mmio_count] $r0
587	mov $r1 #chan_data
588	sethi $r1 0x00060000		// 256 bytes
589	xdst $r0 $r1
590	xdwait
591	ret
592
593// Transfer HUB context data between GPU and storage area
594//
595// In: $r2 channel address
596//     $p1 clear on save, set on load
597//     $p2 set if opposite direction done/will be done, so:
598//		on save it means: "a load will follow this save"
599//		on load it means: "a save preceeded this load"
600//
601ctx_xfer:
602	// according to mwk, some kind of wait for idle
603	mov $r14 4
604	nv_iowr(0x409c08, 0, $r14)
605	ctx_xfer_idle:
606		nv_iord($r14, 0x409c00, 0)
607		and $r14 0x2000
608		bra ne #ctx_xfer_idle
609
610	bra not $p1 #ctx_xfer_pre
611	bra $p2 #ctx_xfer_pre_load
612	ctx_xfer_pre:
613		mov $r15 0x10
614		call(ctx_86c)
615#if CHIPSET < GK100
616		call(ctx_4160s)
617#endif
618		bra not $p1 #ctx_xfer_exec
619
620	ctx_xfer_pre_load:
621		mov $r15 2
622		call(ctx_4170s)
623		call(ctx_4170w)
624		call(ctx_redswitch)
625		clear b32 $r15
626		call(ctx_4170s)
627		call(ctx_load)
628
629	// fetch context pointer, and initiate xfer on all GPCs
630	ctx_xfer_exec:
631	ld b32 $r1 D[$r0 + #ctx_current]
632
633	clear b32 $r2
634	nv_iowr(NV_PGRAPH_FECS_BAR, 0, $r2)
635
636	nv_wr32(0x41a500, $r1)	// GPC_BCAST_WRCMD_DATA = ctx pointer
637	xbit $r15 $flags $p1
638	xbit $r2 $flags $p2
639	shl b32 $r2 1
640	or $r15 $r2
641	nv_wr32(0x41a504, $r15)	// GPC_BCAST_WRCMD_CMD = GPC_XFER(type)
642
643	// strands
644	call(strand_pre)
645	clear b32 $r2
646	nv_iowr(NV_PGRAPH_FECS_STRAND_SELECT, 0x3f, $r2)
647	xbit $r2 $flags $p1	// SAVE/LOAD
648	add b32 $r2 NV_PGRAPH_FECS_STRAND_CMD_SAVE
649	nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r2)
650
651	// mmio context
652	xbit $r10 $flags $p1	// direction
653	or $r10 6		// first, last
654	mov $r11 0		// base = 0
655	ld b32 $r12 D[$r0 + #hub_mmio_list_head]
656	ld b32 $r13 D[$r0 + #hub_mmio_list_tail]
657	mov $r14 0		// not multi
658	call(mmctx_xfer)
659
660	// wait for GPCs to all complete
661	mov $r10 8		// DONE_BAR
662	call(wait_doneo)
663
664	// wait for strand xfer to complete
665	call(strand_wait)
666
667	// post-op
668	bra $p1 #ctx_xfer_post
669		mov $r10 12		// DONE_UNK12
670		call(wait_donez)
671		mov $r15 5 // MEM_CMD 5 ???
672		call(ctx_mem)
673
674	bra $p2 #ctx_xfer_done
675	ctx_xfer_post:
676		mov $r15 2
677		call(ctx_4170s)
678		clear b32 $r15
679		call(ctx_86c)
680		call(strand_post)
681		call(ctx_4170w)
682		clear b32 $r15
683		call(ctx_4170s)
684
685		bra not $p1 #ctx_xfer_no_post_mmio
686		ld b32 $r1 D[$r0 + #chan_mmio_count]
687		or $r1 $r1
688		bra e #ctx_xfer_no_post_mmio
689			call(ctx_mmio_exec)
690
691		ctx_xfer_no_post_mmio:
692#if CHIPSET < GK100
693		call(ctx_4160c)
694#endif
695
696	ctx_xfer_done:
697	ret
698#endif
699