xref: /linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxtu102.c (revision b501d4dc83aa3940189b68045cadc8b3eac73988)
1 /*
2  * Copyright 2019 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  */
22 #include "ctxgf100.h"
23 
24 static void
25 tu102_grctx_generate_r419c0c(struct gf100_gr *gr)
26 {
27 	struct nvkm_device *device = gr->base.engine.subdev.device;
28 	nvkm_mask(device, 0x419c0c, 0x80000000, 0x80000000);
29 	nvkm_mask(device, 0x40584c, 0x00000008, 0x00000000);
30 	nvkm_mask(device, 0x400080, 0x00000000, 0x00000000);
31 }
32 
33 static void
34 tu102_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm)
35 {
36 	struct nvkm_device *device = gr->base.engine.subdev.device;
37 
38 	tpc = gv100_gr_nonpes_aware_tpc(gr, gpc, tpc);
39 
40 	nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x608), sm);
41 	nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x088), sm);
42 }
43 
44 static const struct gf100_gr_init
45 tu102_grctx_init_unknown_bundle_init_0[] = {
46 	{ 0x00001000,  1, 0x00000001, 0x00000004 },
47 	{ 0x00002020, 64, 0x00000001, 0x00000000 },
48 	{ 0x0001e100,  1, 0x00000001, 0x00000001 },
49 	{}
50 };
51 
52 static const struct gf100_gr_pack
53 tu102_grctx_pack_sw_bundle64_init[] = {
54 	{ tu102_grctx_init_unknown_bundle_init_0, .type = 64 },
55 	{}
56 };
57 
58 void
59 tu102_grctx_generate_unknown(struct gf100_gr_chan *chan, u64 addr, u32 size)
60 {
61 	gf100_grctx_patch_wr32(chan, 0x408070, addr >> 8);
62 	gf100_grctx_patch_wr32(chan, 0x408074, size >> 8); /*XXX: guess */
63 	gf100_grctx_patch_wr32(chan, 0x419034, addr >> 8);
64 	gf100_grctx_patch_wr32(chan, 0x408078, 0x00000000);
65 }
66 
67 const struct gf100_grctx_func
68 tu102_grctx = {
69 	.main = gf100_grctx_generate_main,
70 	.unkn = gv100_grctx_generate_unkn,
71 	.sw_bundle64_init = tu102_grctx_pack_sw_bundle64_init,
72 	.bundle = gm107_grctx_generate_bundle,
73 	.bundle_size = 0x3000,
74 	.bundle_min_gpm_fifo_depth = 0x180,
75 	.bundle_token_limit = 0xa80,
76 	.pagepool = gp100_grctx_generate_pagepool,
77 	.pagepool_size = 0x20000,
78 	.attrib_cb_size = gp102_grctx_generate_attrib_cb_size,
79 	.attrib_cb = gv100_grctx_generate_attrib_cb,
80 	.attrib = gv100_grctx_generate_attrib,
81 	.attrib_nr_max = 0x800,
82 	.attrib_nr = 0x700,
83 	.unknown_size = 0x80000,
84 	.unknown = tu102_grctx_generate_unknown,
85 	.alpha_nr_max = 0xc00,
86 	.alpha_nr = 0x800,
87 	.gfxp_nr = 0xfa8,
88 	.sm_id = tu102_grctx_generate_sm_id,
89 	.skip_pd_num_tpc_per_gpc = true,
90 	.rop_mapping = gv100_grctx_generate_rop_mapping,
91 	.r406500 = gm200_grctx_generate_r406500,
92 	.r400088 = gv100_grctx_generate_r400088,
93 	.r419c0c = tu102_grctx_generate_r419c0c,
94 };
95