1 #ifndef __NVKM_GRCTX_H__ 2 #define __NVKM_GRCTX_H__ 3 #include <core/gpuobj.h> 4 5 struct nvkm_grctx { 6 struct nvkm_device *device; 7 8 enum { 9 NVKM_GRCTX_PROG, 10 NVKM_GRCTX_VALS 11 } mode; 12 void *data; 13 14 u32 ctxprog_max; 15 u32 ctxprog_len; 16 u32 ctxprog_reg; 17 int ctxprog_label[32]; 18 u32 ctxvals_pos; 19 u32 ctxvals_base; 20 }; 21 22 static inline void 23 cp_out(struct nvkm_grctx *ctx, u32 inst) 24 { 25 u32 *ctxprog = ctx->data; 26 27 if (ctx->mode != NVKM_GRCTX_PROG) 28 return; 29 30 BUG_ON(ctx->ctxprog_len == ctx->ctxprog_max); 31 ctxprog[ctx->ctxprog_len++] = inst; 32 } 33 34 static inline void 35 cp_lsr(struct nvkm_grctx *ctx, u32 val) 36 { 37 cp_out(ctx, CP_LOAD_SR | val); 38 } 39 40 static inline void 41 cp_ctx(struct nvkm_grctx *ctx, u32 reg, u32 length) 42 { 43 ctx->ctxprog_reg = (reg - 0x00400000) >> 2; 44 45 ctx->ctxvals_base = ctx->ctxvals_pos; 46 ctx->ctxvals_pos = ctx->ctxvals_base + length; 47 48 if (length > (CP_CTX_COUNT >> CP_CTX_COUNT_SHIFT)) { 49 cp_lsr(ctx, length); 50 length = 0; 51 } 52 53 cp_out(ctx, CP_CTX | (length << CP_CTX_COUNT_SHIFT) | ctx->ctxprog_reg); 54 } 55 56 static inline void 57 cp_name(struct nvkm_grctx *ctx, int name) 58 { 59 u32 *ctxprog = ctx->data; 60 int i; 61 62 if (ctx->mode != NVKM_GRCTX_PROG) 63 return; 64 65 ctx->ctxprog_label[name] = ctx->ctxprog_len; 66 for (i = 0; i < ctx->ctxprog_len; i++) { 67 if ((ctxprog[i] & 0xfff00000) != 0xff400000) 68 continue; 69 if ((ctxprog[i] & CP_BRA_IP) != ((name) << CP_BRA_IP_SHIFT)) 70 continue; 71 ctxprog[i] = (ctxprog[i] & 0x00ff00ff) | 72 (ctx->ctxprog_len << CP_BRA_IP_SHIFT); 73 } 74 } 75 76 static inline void 77 _cp_bra(struct nvkm_grctx *ctx, u32 mod, int flag, int state, int name) 78 { 79 int ip = 0; 80 81 if (mod != 2) { 82 ip = ctx->ctxprog_label[name] << CP_BRA_IP_SHIFT; 83 if (ip == 0) 84 ip = 0xff000000 | (name << CP_BRA_IP_SHIFT); 85 } 86 87 cp_out(ctx, CP_BRA | (mod << 18) | ip | flag | 88 (state ? 0 : CP_BRA_IF_CLEAR)); 89 } 90 #define cp_bra(c, f, s, n) _cp_bra((c), 0, CP_FLAG_##f, CP_FLAG_##f##_##s, n) 91 #define cp_cal(c, f, s, n) _cp_bra((c), 1, CP_FLAG_##f, CP_FLAG_##f##_##s, n) 92 #define cp_ret(c, f, s) _cp_bra((c), 2, CP_FLAG_##f, CP_FLAG_##f##_##s, 0) 93 94 static inline void 95 _cp_wait(struct nvkm_grctx *ctx, int flag, int state) 96 { 97 cp_out(ctx, CP_WAIT | flag | (state ? CP_WAIT_SET : 0)); 98 } 99 #define cp_wait(c, f, s) _cp_wait((c), CP_FLAG_##f, CP_FLAG_##f##_##s) 100 101 static inline void 102 _cp_set(struct nvkm_grctx *ctx, int flag, int state) 103 { 104 cp_out(ctx, CP_SET | flag | (state ? CP_SET_1 : 0)); 105 } 106 #define cp_set(c, f, s) _cp_set((c), CP_FLAG_##f, CP_FLAG_##f##_##s) 107 108 static inline void 109 cp_pos(struct nvkm_grctx *ctx, int offset) 110 { 111 ctx->ctxvals_pos = offset; 112 ctx->ctxvals_base = ctx->ctxvals_pos; 113 114 cp_lsr(ctx, ctx->ctxvals_pos); 115 cp_out(ctx, CP_SET_CONTEXT_POINTER); 116 } 117 118 static inline void 119 gr_def(struct nvkm_grctx *ctx, u32 reg, u32 val) 120 { 121 if (ctx->mode != NVKM_GRCTX_VALS) 122 return; 123 124 reg = (reg - 0x00400000) / 4; 125 reg = (reg - ctx->ctxprog_reg) + ctx->ctxvals_base; 126 127 nv_wo32(ctx->data, reg * 4, val); 128 } 129 #endif 130