1 /* 2 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20 * DEALINGS IN THE SOFTWARE. 21 */ 22 #include "ctxgf100.h" 23 24 static void 25 gm20b_grctx_generate_main(struct gf100_gr_chan *chan, struct gf100_grctx *info) 26 { 27 struct gf100_gr *gr = chan->gr; 28 struct nvkm_device *device = gr->base.engine.subdev.device; 29 const struct gf100_grctx_func *grctx = gr->func->grctx; 30 u32 idle_timeout; 31 int i, tmp; 32 33 gf100_gr_mmio(gr, gr->sw_ctx); 34 35 gf100_gr_wait_idle(gr); 36 37 idle_timeout = nvkm_mask(device, 0x404154, 0xffffffff, 0x00000000); 38 39 grctx->attrib(info); 40 41 grctx->unkn(gr); 42 43 gf100_grctx_generate_floorsweep(gr); 44 45 for (i = 0; i < 8; i++) 46 nvkm_wr32(device, 0x4064d0 + (i * 0x04), 0x00000000); 47 48 nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); 49 50 nvkm_wr32(device, 0x408908, nvkm_rd32(device, 0x410108) | 0x80000000); 51 52 for (tmp = 0, i = 0; i < gr->gpc_nr; i++) 53 tmp |= ((1 << gr->tpc_nr[i]) - 1) << (i * 4); 54 nvkm_wr32(device, 0x4041c4, tmp); 55 56 gm200_grctx_generate_smid_config(gr); 57 58 gf100_gr_wait_idle(gr); 59 60 nvkm_wr32(device, 0x404154, idle_timeout); 61 gf100_gr_wait_idle(gr); 62 63 gf100_gr_mthd(gr, gr->method); 64 gf100_gr_wait_idle(gr); 65 66 gf100_gr_icmd(gr, gr->bundle); 67 grctx->pagepool(chan, chan->pagepool->addr); 68 grctx->bundle(info); 69 } 70 71 const struct gf100_grctx_func 72 gm20b_grctx = { 73 .main = gm20b_grctx_generate_main, 74 .unkn = gk104_grctx_generate_unkn, 75 .bundle = gm107_grctx_generate_bundle, 76 .bundle_size = 0x1800, 77 .bundle_min_gpm_fifo_depth = 0x182, 78 .bundle_token_limit = 0x1c0, 79 .pagepool = gm107_grctx_generate_pagepool, 80 .pagepool_size = 0x8000, 81 .attrib = gm107_grctx_generate_attrib, 82 .attrib_nr_max = 0x600, 83 .attrib_nr = 0x400, 84 .alpha_nr_max = 0xc00, 85 .alpha_nr = 0x800, 86 .sm_id = gm107_grctx_generate_sm_id, 87 .rop_mapping = gf117_grctx_generate_rop_mapping, 88 }; 89