1 /* 2 * Copyright 2018 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #include "priv.h" 23 #include "cgrp.h" 24 #include "chan.h" 25 #include "runl.h" 26 27 #include <core/memory.h> 28 #include <subdev/mc.h> 29 #include <subdev/vfn.h> 30 31 #include <nvif/class.h> 32 33 static u32 34 tu102_chan_doorbell_handle(struct nvkm_chan *chan) 35 { 36 return (chan->cgrp->runl->id << 16) | chan->id; 37 } 38 39 static void 40 tu102_chan_start(struct nvkm_chan *chan) 41 { 42 struct nvkm_device *device = chan->cgrp->runl->fifo->engine.subdev.device; 43 44 gk104_chan_start(chan); 45 nvkm_wr32(device, device->vfn->addr.user + 0x0090, chan->func->doorbell_handle(chan)); 46 } 47 48 static const struct nvkm_chan_func 49 tu102_chan = { 50 .inst = &gf100_chan_inst, 51 .userd = &gv100_chan_userd, 52 .ramfc = &gv100_chan_ramfc, 53 .bind = gk104_chan_bind_inst, 54 .unbind = gk104_chan_unbind, 55 .start = tu102_chan_start, 56 .stop = gk104_chan_stop, 57 .preempt = gk110_chan_preempt, 58 .doorbell_handle = tu102_chan_doorbell_handle, 59 }; 60 61 static bool 62 tu102_runl_pending(struct nvkm_runl *runl) 63 { 64 struct nvkm_device *device = runl->fifo->engine.subdev.device; 65 66 return nvkm_rd32(device, 0x002b0c + (runl->id * 0x10)) & 0x00008000; 67 } 68 69 static void 70 tu102_runl_commit(struct nvkm_runl *runl, struct nvkm_memory *memory, u32 start, int count) 71 { 72 struct nvkm_device *device = runl->fifo->engine.subdev.device; 73 u64 addr = nvkm_memory_addr(memory) + start; 74 /*XXX: target? */ 75 76 nvkm_wr32(device, 0x002b00 + (runl->id * 0x10), lower_32_bits(addr)); 77 nvkm_wr32(device, 0x002b04 + (runl->id * 0x10), upper_32_bits(addr)); 78 nvkm_wr32(device, 0x002b08 + (runl->id * 0x10), count); 79 } 80 81 static const struct nvkm_runl_func 82 tu102_runl = { 83 .runqs = 2, 84 .size = 16, 85 .update = nv50_runl_update, 86 .insert_cgrp = gv100_runl_insert_cgrp, 87 .insert_chan = gv100_runl_insert_chan, 88 .commit = tu102_runl_commit, 89 .wait = nv50_runl_wait, 90 .pending = tu102_runl_pending, 91 .block = gk104_runl_block, 92 .allow = gk104_runl_allow, 93 .preempt = gv100_runl_preempt, 94 .preempt_pending = gf100_runl_preempt_pending, 95 }; 96 97 static const struct nvkm_enum 98 tu102_fifo_mmu_fault_engine[] = { 99 { 0x01, "DISPLAY" }, 100 { 0x03, "PTP" }, 101 { 0x06, "PWR_PMU" }, 102 { 0x08, "IFB", NULL, NVKM_ENGINE_IFB }, 103 { 0x09, "PERF" }, 104 { 0x1f, "PHYSICAL" }, 105 { 0x20, "HOST0" }, 106 { 0x21, "HOST1" }, 107 { 0x22, "HOST2" }, 108 { 0x23, "HOST3" }, 109 { 0x24, "HOST4" }, 110 { 0x25, "HOST5" }, 111 { 0x26, "HOST6" }, 112 { 0x27, "HOST7" }, 113 { 0x28, "HOST8" }, 114 { 0x29, "HOST9" }, 115 { 0x2a, "HOST10" }, 116 { 0x2b, "HOST11" }, 117 { 0x2c, "HOST12" }, 118 { 0x2d, "HOST13" }, 119 { 0x2e, "HOST14" }, 120 { 0x80, "BAR1", NULL, NVKM_SUBDEV_BAR }, 121 { 0xc0, "BAR2", NULL, NVKM_SUBDEV_INSTMEM }, 122 {} 123 }; 124 125 const struct nvkm_fifo_func_mmu_fault 126 tu102_fifo_mmu_fault = { 127 .recover = gf100_fifo_mmu_fault_recover, 128 .access = gv100_fifo_mmu_fault_access, 129 .engine = tu102_fifo_mmu_fault_engine, 130 .reason = gv100_fifo_mmu_fault_reason, 131 .hubclient = gv100_fifo_mmu_fault_hubclient, 132 .gpcclient = gv100_fifo_mmu_fault_gpcclient, 133 }; 134 135 void 136 tu102_fifo_intr_ctxsw_timeout_info(struct nvkm_engn *engn, u32 info) 137 { 138 struct nvkm_runl *runl = engn->runl; 139 struct nvkm_cgrp *cgrp; 140 unsigned long flags; 141 142 /* Check that engine hasn't become unstuck since timeout raised. */ 143 ENGN_DEBUG(engn, "CTXSW_TIMEOUT %08x", info); 144 if (info & 0xc0000000) 145 return; 146 147 /* Determine channel group the engine is stuck on, and schedule recovery. */ 148 switch (info & 0x0000c000) { 149 case 0x00004000: /* LOAD */ 150 cgrp = nvkm_runl_cgrp_get_cgid(runl, info & 0x3fff0000, &flags); 151 break; 152 case 0x00008000: /* SAVE */ 153 case 0x0000c000: /* SWITCH */ 154 cgrp = nvkm_runl_cgrp_get_cgid(runl, info & 0x00003fff, &flags); 155 break; 156 default: 157 cgrp = NULL; 158 break; 159 } 160 161 if (!WARN_ON(!cgrp)) { 162 nvkm_runl_rc_cgrp(cgrp); 163 nvkm_cgrp_put(&cgrp, flags); 164 } 165 } 166 167 static void 168 tu102_fifo_intr_ctxsw_timeout(struct nvkm_fifo *fifo) 169 { 170 struct nvkm_device *device = fifo->engine.subdev.device; 171 struct nvkm_runl *runl; 172 struct nvkm_engn *engn; 173 u32 engm = nvkm_rd32(device, 0x002a30); 174 u32 info; 175 176 nvkm_runl_foreach(runl, fifo) { 177 nvkm_runl_foreach_engn_cond(engn, runl, engm & BIT(engn->id)) { 178 info = nvkm_rd32(device, 0x003200 + (engn->id * 4)); 179 tu102_fifo_intr_ctxsw_timeout_info(engn, info); 180 } 181 } 182 183 nvkm_wr32(device, 0x002a30, engm); 184 } 185 186 static void 187 tu102_fifo_intr_sched(struct nvkm_fifo *fifo) 188 { 189 struct nvkm_subdev *subdev = &fifo->engine.subdev; 190 u32 intr = nvkm_rd32(subdev->device, 0x00254c); 191 u32 code = intr & 0x000000ff; 192 193 nvkm_error(subdev, "SCHED_ERROR %02x\n", code); 194 } 195 196 static irqreturn_t 197 tu102_fifo_intr(struct nvkm_inth *inth) 198 { 199 struct nvkm_fifo *fifo = container_of(inth, typeof(*fifo), engine.subdev.inth); 200 struct nvkm_subdev *subdev = &fifo->engine.subdev; 201 struct nvkm_device *device = subdev->device; 202 u32 mask = nvkm_rd32(device, 0x002140); 203 u32 stat = nvkm_rd32(device, 0x002100) & mask; 204 205 if (stat & 0x00000001) { 206 gk104_fifo_intr_bind(fifo); 207 nvkm_wr32(device, 0x002100, 0x00000001); 208 stat &= ~0x00000001; 209 } 210 211 if (stat & 0x00000002) { 212 tu102_fifo_intr_ctxsw_timeout(fifo); 213 stat &= ~0x00000002; 214 } 215 216 if (stat & 0x00000100) { 217 tu102_fifo_intr_sched(fifo); 218 nvkm_wr32(device, 0x002100, 0x00000100); 219 stat &= ~0x00000100; 220 } 221 222 if (stat & 0x00010000) { 223 gk104_fifo_intr_chsw(fifo); 224 nvkm_wr32(device, 0x002100, 0x00010000); 225 stat &= ~0x00010000; 226 } 227 228 if (stat & 0x20000000) { 229 if (gf100_fifo_intr_pbdma(fifo)) 230 stat &= ~0x20000000; 231 } 232 233 if (stat & 0x40000000) { 234 gk104_fifo_intr_runlist(fifo); 235 stat &= ~0x40000000; 236 } 237 238 if (stat & 0x80000000) { 239 nvkm_wr32(device, 0x002100, 0x80000000); 240 nvkm_event_ntfy(&fifo->nonstall.event, 0, NVKM_FIFO_NONSTALL_EVENT); 241 stat &= ~0x80000000; 242 } 243 244 if (stat) { 245 nvkm_error(subdev, "INTR %08x\n", stat); 246 spin_lock(&fifo->lock); 247 nvkm_mask(device, 0x002140, stat, 0x00000000); 248 spin_unlock(&fifo->lock); 249 nvkm_wr32(device, 0x002100, stat); 250 } 251 252 return IRQ_HANDLED; 253 } 254 255 static void 256 tu102_fifo_init_pbdmas(struct nvkm_fifo *fifo, u32 mask) 257 { 258 /* Not directly related to PBDMAs, but, enables doorbell to function. */ 259 nvkm_mask(fifo->engine.subdev.device, 0xb65000, 0x80000000, 0x80000000); 260 } 261 262 static const struct nvkm_fifo_func 263 tu102_fifo = { 264 .chid_nr = gm200_fifo_chid_nr, 265 .chid_ctor = gk110_fifo_chid_ctor, 266 .runq_nr = gm200_fifo_runq_nr, 267 .runl_ctor = gk104_fifo_runl_ctor, 268 .init = gk104_fifo_init, 269 .init_pbdmas = tu102_fifo_init_pbdmas, 270 .intr = tu102_fifo_intr, 271 .mmu_fault = &tu102_fifo_mmu_fault, 272 .nonstall = &gf100_fifo_nonstall, 273 .runl = &tu102_runl, 274 .runq = &gv100_runq, 275 .engn = &gv100_engn, 276 .engn_ce = &gv100_engn_ce, 277 .cgrp = {{ 0, 0, KEPLER_CHANNEL_GROUP_A }, &gk110_cgrp, .force = true }, 278 .chan = {{ 0, 0, TURING_CHANNEL_GPFIFO_A }, &tu102_chan }, 279 }; 280 281 int 282 tu102_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, 283 struct nvkm_fifo **pfifo) 284 { 285 return nvkm_fifo_new_(&tu102_fifo, device, type, inst, pfifo); 286 } 287