1 /* 2 * Copyright 2018 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #include "priv.h" 23 #include "cgrp.h" 24 #include "chan.h" 25 #include "runl.h" 26 27 #include <core/memory.h> 28 #include <subdev/gsp.h> 29 #include <subdev/mc.h> 30 #include <subdev/vfn.h> 31 32 #include <nvif/class.h> 33 34 static u32 35 tu102_chan_doorbell_handle(struct nvkm_chan *chan) 36 { 37 return (chan->cgrp->runl->id << 16) | chan->id; 38 } 39 40 static void 41 tu102_chan_start(struct nvkm_chan *chan) 42 { 43 struct nvkm_device *device = chan->cgrp->runl->fifo->engine.subdev.device; 44 45 gk104_chan_start(chan); 46 nvkm_wr32(device, device->vfn->addr.user + 0x0090, chan->func->doorbell_handle(chan)); 47 } 48 49 static const struct nvkm_chan_func 50 tu102_chan = { 51 .inst = &gf100_chan_inst, 52 .userd = &gv100_chan_userd, 53 .ramfc = &gv100_chan_ramfc, 54 .bind = gk104_chan_bind_inst, 55 .unbind = gk104_chan_unbind, 56 .start = tu102_chan_start, 57 .stop = gk104_chan_stop, 58 .preempt = gk110_chan_preempt, 59 .doorbell_handle = tu102_chan_doorbell_handle, 60 }; 61 62 static bool 63 tu102_runl_pending(struct nvkm_runl *runl) 64 { 65 struct nvkm_device *device = runl->fifo->engine.subdev.device; 66 67 return nvkm_rd32(device, 0x002b0c + (runl->id * 0x10)) & 0x00008000; 68 } 69 70 static void 71 tu102_runl_commit(struct nvkm_runl *runl, struct nvkm_memory *memory, u32 start, int count) 72 { 73 struct nvkm_device *device = runl->fifo->engine.subdev.device; 74 u64 addr = nvkm_memory_addr(memory) + start; 75 /*XXX: target? */ 76 77 nvkm_wr32(device, 0x002b00 + (runl->id * 0x10), lower_32_bits(addr)); 78 nvkm_wr32(device, 0x002b04 + (runl->id * 0x10), upper_32_bits(addr)); 79 nvkm_wr32(device, 0x002b08 + (runl->id * 0x10), count); 80 } 81 82 static const struct nvkm_runl_func 83 tu102_runl = { 84 .runqs = 2, 85 .size = 16, 86 .update = nv50_runl_update, 87 .insert_cgrp = gv100_runl_insert_cgrp, 88 .insert_chan = gv100_runl_insert_chan, 89 .commit = tu102_runl_commit, 90 .wait = nv50_runl_wait, 91 .pending = tu102_runl_pending, 92 .block = gk104_runl_block, 93 .allow = gk104_runl_allow, 94 .preempt = gv100_runl_preempt, 95 .preempt_pending = gf100_runl_preempt_pending, 96 }; 97 98 static const struct nvkm_enum 99 tu102_fifo_mmu_fault_engine[] = { 100 { 0x01, "DISPLAY" }, 101 { 0x03, "PTP" }, 102 { 0x06, "PWR_PMU" }, 103 { 0x08, "IFB", NULL, NVKM_ENGINE_IFB }, 104 { 0x09, "PERF" }, 105 { 0x1f, "PHYSICAL" }, 106 { 0x20, "HOST0" }, 107 { 0x21, "HOST1" }, 108 { 0x22, "HOST2" }, 109 { 0x23, "HOST3" }, 110 { 0x24, "HOST4" }, 111 { 0x25, "HOST5" }, 112 { 0x26, "HOST6" }, 113 { 0x27, "HOST7" }, 114 { 0x28, "HOST8" }, 115 { 0x29, "HOST9" }, 116 { 0x2a, "HOST10" }, 117 { 0x2b, "HOST11" }, 118 { 0x2c, "HOST12" }, 119 { 0x2d, "HOST13" }, 120 { 0x2e, "HOST14" }, 121 { 0x80, "BAR1", NULL, NVKM_SUBDEV_BAR }, 122 { 0xc0, "BAR2", NULL, NVKM_SUBDEV_INSTMEM }, 123 {} 124 }; 125 126 const struct nvkm_fifo_func_mmu_fault 127 tu102_fifo_mmu_fault = { 128 .recover = gf100_fifo_mmu_fault_recover, 129 .access = gv100_fifo_mmu_fault_access, 130 .engine = tu102_fifo_mmu_fault_engine, 131 .reason = gv100_fifo_mmu_fault_reason, 132 .hubclient = gv100_fifo_mmu_fault_hubclient, 133 .gpcclient = gv100_fifo_mmu_fault_gpcclient, 134 }; 135 136 void 137 tu102_fifo_intr_ctxsw_timeout_info(struct nvkm_engn *engn, u32 info) 138 { 139 struct nvkm_runl *runl = engn->runl; 140 struct nvkm_cgrp *cgrp; 141 unsigned long flags; 142 143 /* Check that engine hasn't become unstuck since timeout raised. */ 144 ENGN_DEBUG(engn, "CTXSW_TIMEOUT %08x", info); 145 if (info & 0xc0000000) 146 return; 147 148 /* Determine channel group the engine is stuck on, and schedule recovery. */ 149 switch (info & 0x0000c000) { 150 case 0x00004000: /* LOAD */ 151 cgrp = nvkm_runl_cgrp_get_cgid(runl, info & 0x3fff0000, &flags); 152 break; 153 case 0x00008000: /* SAVE */ 154 case 0x0000c000: /* SWITCH */ 155 cgrp = nvkm_runl_cgrp_get_cgid(runl, info & 0x00003fff, &flags); 156 break; 157 default: 158 cgrp = NULL; 159 break; 160 } 161 162 if (!WARN_ON(!cgrp)) { 163 nvkm_runl_rc_cgrp(cgrp); 164 nvkm_cgrp_put(&cgrp, flags); 165 } 166 } 167 168 static void 169 tu102_fifo_intr_ctxsw_timeout(struct nvkm_fifo *fifo) 170 { 171 struct nvkm_device *device = fifo->engine.subdev.device; 172 struct nvkm_runl *runl; 173 struct nvkm_engn *engn; 174 u32 engm = nvkm_rd32(device, 0x002a30); 175 u32 info; 176 177 nvkm_runl_foreach(runl, fifo) { 178 nvkm_runl_foreach_engn_cond(engn, runl, engm & BIT(engn->id)) { 179 info = nvkm_rd32(device, 0x003200 + (engn->id * 4)); 180 tu102_fifo_intr_ctxsw_timeout_info(engn, info); 181 } 182 } 183 184 nvkm_wr32(device, 0x002a30, engm); 185 } 186 187 static void 188 tu102_fifo_intr_sched(struct nvkm_fifo *fifo) 189 { 190 struct nvkm_subdev *subdev = &fifo->engine.subdev; 191 u32 intr = nvkm_rd32(subdev->device, 0x00254c); 192 u32 code = intr & 0x000000ff; 193 194 nvkm_error(subdev, "SCHED_ERROR %02x\n", code); 195 } 196 197 static irqreturn_t 198 tu102_fifo_intr(struct nvkm_inth *inth) 199 { 200 struct nvkm_fifo *fifo = container_of(inth, typeof(*fifo), engine.subdev.inth); 201 struct nvkm_subdev *subdev = &fifo->engine.subdev; 202 struct nvkm_device *device = subdev->device; 203 u32 mask = nvkm_rd32(device, 0x002140); 204 u32 stat = nvkm_rd32(device, 0x002100) & mask; 205 206 if (stat & 0x00000001) { 207 gk104_fifo_intr_bind(fifo); 208 nvkm_wr32(device, 0x002100, 0x00000001); 209 stat &= ~0x00000001; 210 } 211 212 if (stat & 0x00000002) { 213 tu102_fifo_intr_ctxsw_timeout(fifo); 214 stat &= ~0x00000002; 215 } 216 217 if (stat & 0x00000100) { 218 tu102_fifo_intr_sched(fifo); 219 nvkm_wr32(device, 0x002100, 0x00000100); 220 stat &= ~0x00000100; 221 } 222 223 if (stat & 0x00010000) { 224 gk104_fifo_intr_chsw(fifo); 225 nvkm_wr32(device, 0x002100, 0x00010000); 226 stat &= ~0x00010000; 227 } 228 229 if (stat & 0x20000000) { 230 if (gf100_fifo_intr_pbdma(fifo)) 231 stat &= ~0x20000000; 232 } 233 234 if (stat & 0x40000000) { 235 gk104_fifo_intr_runlist(fifo); 236 stat &= ~0x40000000; 237 } 238 239 if (stat & 0x80000000) { 240 nvkm_wr32(device, 0x002100, 0x80000000); 241 nvkm_event_ntfy(&fifo->nonstall.event, 0, NVKM_FIFO_NONSTALL_EVENT); 242 stat &= ~0x80000000; 243 } 244 245 if (stat) { 246 nvkm_error(subdev, "INTR %08x\n", stat); 247 spin_lock(&fifo->lock); 248 nvkm_mask(device, 0x002140, stat, 0x00000000); 249 spin_unlock(&fifo->lock); 250 nvkm_wr32(device, 0x002100, stat); 251 } 252 253 return IRQ_HANDLED; 254 } 255 256 static void 257 tu102_fifo_init_pbdmas(struct nvkm_fifo *fifo, u32 mask) 258 { 259 /* Not directly related to PBDMAs, but, enables doorbell to function. */ 260 nvkm_mask(fifo->engine.subdev.device, 0xb65000, 0x80000000, 0x80000000); 261 } 262 263 static const struct nvkm_fifo_func 264 tu102_fifo = { 265 .chid_nr = gm200_fifo_chid_nr, 266 .chid_ctor = gk110_fifo_chid_ctor, 267 .runq_nr = gm200_fifo_runq_nr, 268 .runl_ctor = gk104_fifo_runl_ctor, 269 .init = gk104_fifo_init, 270 .init_pbdmas = tu102_fifo_init_pbdmas, 271 .intr = tu102_fifo_intr, 272 .mmu_fault = &tu102_fifo_mmu_fault, 273 .nonstall = &gf100_fifo_nonstall, 274 .runl = &tu102_runl, 275 .runq = &gv100_runq, 276 .engn = &gv100_engn, 277 .engn_ce = &gv100_engn_ce, 278 .cgrp = {{ 0, 0, KEPLER_CHANNEL_GROUP_A }, &gk110_cgrp, .force = true }, 279 .chan = {{ 0, 0, TURING_CHANNEL_GPFIFO_A }, &tu102_chan }, 280 }; 281 282 int 283 tu102_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, 284 struct nvkm_fifo **pfifo) 285 { 286 if (nvkm_gsp_rm(device->gsp)) 287 return r535_fifo_new(&tu102_fifo, device, type, inst, pfifo); 288 289 return nvkm_fifo_new_(&tu102_fifo, device, type, inst, pfifo); 290 } 291