1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "priv.h" 25 #include "cgrp.h" 26 #include "chan.h" 27 #include "chid.h" 28 #include "runl.h" 29 30 #include "regsnv04.h" 31 32 #include <core/ramht.h> 33 #include <subdev/instmem.h> 34 35 #include <nvif/class.h> 36 37 static int 38 nv17_chan_ramfc_write(struct nvkm_chan *chan, u64 offset, u64 length, u32 devm, bool priv) 39 { 40 struct nvkm_memory *ramfc = chan->cgrp->runl->fifo->engine.subdev.device->imem->ramfc; 41 const u32 base = chan->id * 64; 42 43 chan->ramfc_offset = base; 44 45 nvkm_kmap(ramfc); 46 nvkm_wo32(ramfc, base + 0x00, offset); 47 nvkm_wo32(ramfc, base + 0x04, offset); 48 nvkm_wo32(ramfc, base + 0x0c, chan->push->addr >> 4); 49 nvkm_wo32(ramfc, base + 0x14, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | 50 NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | 51 #ifdef __BIG_ENDIAN 52 NV_PFIFO_CACHE1_BIG_ENDIAN | 53 #endif 54 NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8); 55 nvkm_done(ramfc); 56 return 0; 57 } 58 59 static const struct nvkm_chan_func_ramfc 60 nv17_chan_ramfc = { 61 .layout = (const struct nvkm_ramfc_layout[]) { 62 { 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT }, 63 { 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET }, 64 { 32, 0, 0x08, 0, NV10_PFIFO_CACHE1_REF_CNT }, 65 { 16, 0, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_INSTANCE }, 66 { 16, 16, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_DCOUNT }, 67 { 32, 0, 0x10, 0, NV04_PFIFO_CACHE1_DMA_STATE }, 68 { 32, 0, 0x14, 0, NV04_PFIFO_CACHE1_DMA_FETCH }, 69 { 32, 0, 0x18, 0, NV04_PFIFO_CACHE1_ENGINE }, 70 { 32, 0, 0x1c, 0, NV04_PFIFO_CACHE1_PULL1 }, 71 { 32, 0, 0x20, 0, NV10_PFIFO_CACHE1_ACQUIRE_VALUE }, 72 { 32, 0, 0x24, 0, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP }, 73 { 32, 0, 0x28, 0, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT }, 74 { 32, 0, 0x2c, 0, NV10_PFIFO_CACHE1_SEMAPHORE }, 75 { 32, 0, 0x30, 0, NV10_PFIFO_CACHE1_DMA_SUBROUTINE }, 76 {} 77 }, 78 .write = nv17_chan_ramfc_write, 79 .clear = nv04_chan_ramfc_clear, 80 .ctxdma = true, 81 }; 82 83 static const struct nvkm_chan_func 84 nv17_chan = { 85 .inst = &nv04_chan_inst, 86 .userd = &nv04_chan_userd, 87 .ramfc = &nv17_chan_ramfc, 88 .start = nv04_chan_start, 89 .stop = nv04_chan_stop, 90 }; 91 92 static void 93 nv17_fifo_init(struct nvkm_fifo *fifo) 94 { 95 struct nvkm_device *device = fifo->engine.subdev.device; 96 struct nvkm_instmem *imem = device->imem; 97 struct nvkm_ramht *ramht = imem->ramht; 98 struct nvkm_memory *ramro = imem->ramro; 99 struct nvkm_memory *ramfc = imem->ramfc; 100 101 nvkm_wr32(device, NV04_PFIFO_DELAY_0, 0x000000ff); 102 nvkm_wr32(device, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff); 103 104 nvkm_wr32(device, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ | 105 ((ramht->bits - 9) << 16) | 106 (ramht->gpuobj->addr >> 8)); 107 nvkm_wr32(device, NV03_PFIFO_RAMRO, nvkm_memory_addr(ramro) >> 8); 108 nvkm_wr32(device, NV03_PFIFO_RAMFC, nvkm_memory_addr(ramfc) >> 8 | 109 0x00010000); 110 111 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->chid->mask); 112 113 nvkm_wr32(device, NV03_PFIFO_INTR_0, 0xffffffff); 114 nvkm_wr32(device, NV03_PFIFO_INTR_EN_0, 0xffffffff); 115 116 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1); 117 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); 118 nvkm_wr32(device, NV03_PFIFO_CACHES, 1); 119 } 120 121 static const struct nvkm_fifo_func 122 nv17_fifo = { 123 .chid_nr = nv10_fifo_chid_nr, 124 .chid_ctor = nv04_fifo_chid_ctor, 125 .runl_ctor = nv04_fifo_runl_ctor, 126 .init = nv17_fifo_init, 127 .intr = nv04_fifo_intr, 128 .pause = nv04_fifo_pause, 129 .start = nv04_fifo_start, 130 .runl = &nv04_runl, 131 .engn = &nv04_engn, 132 .engn_sw = &nv04_engn, 133 .cgrp = {{ }, &nv04_cgrp }, 134 .chan = {{ 0, 0, NV17_CHANNEL_DMA }, &nv17_chan }, 135 }; 136 137 int 138 nv17_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, 139 struct nvkm_fifo **pfifo) 140 { 141 return nvkm_fifo_new_(&nv17_fifo, device, type, inst, pfifo); 142 } 143