xref: /linux/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp100.c (revision e9f0878c4b2004ac19581274c1ae4c61ae3ca70e)
1 /*
2  * Copyright 2016 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs
23  */
24 #include "gk104.h"
25 #include "changk104.h"
26 
27 #include <nvif/class.h>
28 
29 const struct nvkm_enum
30 gp100_fifo_fault_engine[] = {
31 	{ 0x01, "DISPLAY" },
32 	{ 0x03, "IFB", NULL, NVKM_ENGINE_IFB },
33 	{ 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR },
34 	{ 0x05, "BAR2", NULL, NVKM_SUBDEV_INSTMEM },
35 	{ 0x06, "HOST0", NULL, NVKM_ENGINE_FIFO },
36 	{ 0x07, "HOST1", NULL, NVKM_ENGINE_FIFO },
37 	{ 0x08, "HOST2", NULL, NVKM_ENGINE_FIFO },
38 	{ 0x09, "HOST3", NULL, NVKM_ENGINE_FIFO },
39 	{ 0x0a, "HOST4", NULL, NVKM_ENGINE_FIFO },
40 	{ 0x0b, "HOST5", NULL, NVKM_ENGINE_FIFO },
41 	{ 0x0c, "HOST6", NULL, NVKM_ENGINE_FIFO },
42 	{ 0x0d, "HOST7", NULL, NVKM_ENGINE_FIFO },
43 	{ 0x0e, "HOST8", NULL, NVKM_ENGINE_FIFO },
44 	{ 0x0f, "HOST9", NULL, NVKM_ENGINE_FIFO },
45 	{ 0x10, "HOST10", NULL, NVKM_ENGINE_FIFO },
46 	{ 0x13, "PERF" },
47 	{ 0x17, "PMU" },
48 	{ 0x18, "PTP" },
49 	{ 0x1f, "PHYSICAL" },
50 	{}
51 };
52 
53 static const struct gk104_fifo_func
54 gp100_fifo = {
55 	.init_pbdma_timeout = gk208_fifo_init_pbdma_timeout,
56 	.fault.access = gk104_fifo_fault_access,
57 	.fault.engine = gp100_fifo_fault_engine,
58 	.fault.reason = gk104_fifo_fault_reason,
59 	.fault.hubclient = gk104_fifo_fault_hubclient,
60 	.fault.gpcclient = gk104_fifo_fault_gpcclient,
61 	.runlist = &gm107_fifo_runlist,
62 	.chan = {{0,0,PASCAL_CHANNEL_GPFIFO_A}, gk104_fifo_gpfifo_new },
63 	.cgrp_force = true,
64 };
65 
66 int
67 gp100_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)
68 {
69 	return gk104_fifo_new_(&gp100_fifo, device, index, 4096, pfifo);
70 }
71