xref: /linux/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp100.c (revision e43c872c03a9ad56f5cbc52149b4454601aa6904)
1 /*
2  * Copyright 2016 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs
23  */
24 #include "runl.h"
25 #include "gk104.h"
26 #include "changk104.h"
27 
28 #include <subdev/fault.h>
29 
30 #include <nvif/class.h>
31 
32 static const struct nvkm_runl_func
33 gp100_runl = {
34 };
35 
36 static const struct nvkm_enum
37 gp100_fifo_mmu_fault_engine[] = {
38 	{ 0x01, "DISPLAY" },
39 	{ 0x03, "IFB", NULL, NVKM_ENGINE_IFB },
40 	{ 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR },
41 	{ 0x05, "BAR2", NULL, NVKM_SUBDEV_INSTMEM },
42 	{ 0x06, "HOST0" },
43 	{ 0x07, "HOST1" },
44 	{ 0x08, "HOST2" },
45 	{ 0x09, "HOST3" },
46 	{ 0x0a, "HOST4" },
47 	{ 0x0b, "HOST5" },
48 	{ 0x0c, "HOST6" },
49 	{ 0x0d, "HOST7" },
50 	{ 0x0e, "HOST8" },
51 	{ 0x0f, "HOST9" },
52 	{ 0x10, "HOST10" },
53 	{ 0x13, "PERF" },
54 	{ 0x17, "PMU" },
55 	{ 0x18, "PTP" },
56 	{ 0x1f, "PHYSICAL" },
57 	{}
58 };
59 
60 static const struct nvkm_fifo_func_mmu_fault
61 gp100_fifo_mmu_fault = {
62 	.recover = gf100_fifo_mmu_fault_recover,
63 	.access = gf100_fifo_mmu_fault_access,
64 	.engine = gp100_fifo_mmu_fault_engine,
65 	.reason = gk104_fifo_mmu_fault_reason,
66 	.hubclient = gk104_fifo_mmu_fault_hubclient,
67 	.gpcclient = gk104_fifo_mmu_fault_gpcclient,
68 };
69 
70 static void
71 gp100_fifo_intr_mmu_fault_unit(struct nvkm_fifo *fifo, int unit)
72 {
73 	struct nvkm_device *device = fifo->engine.subdev.device;
74 	u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10));
75 	u32 valo = nvkm_rd32(device, 0x002804 + (unit * 0x10));
76 	u32 vahi = nvkm_rd32(device, 0x002808 + (unit * 0x10));
77 	u32 type = nvkm_rd32(device, 0x00280c + (unit * 0x10));
78 	struct nvkm_fault_data info;
79 
80 	info.inst   =  (u64)inst << 12;
81 	info.addr   = ((u64)vahi << 32) | valo;
82 	info.time   = 0;
83 	info.engine = unit;
84 	info.valid  = 1;
85 	info.gpc    = (type & 0x1f000000) >> 24;
86 	info.hub    = (type & 0x00100000) >> 20;
87 	info.access = (type & 0x00070000) >> 16;
88 	info.client = (type & 0x00007f00) >> 8;
89 	info.reason = (type & 0x0000001f);
90 
91 	nvkm_fifo_fault(fifo, &info);
92 }
93 
94 static const struct nvkm_fifo_func
95 gp100_fifo = {
96 	.dtor = gk104_fifo_dtor,
97 	.oneinit = gk104_fifo_oneinit,
98 	.chid_nr = gm200_fifo_chid_nr,
99 	.chid_ctor = gk110_fifo_chid_ctor,
100 	.runq_nr = gm200_fifo_runq_nr,
101 	.runl_ctor = gk104_fifo_runl_ctor,
102 	.init = gk104_fifo_init,
103 	.init_pbdmas = gk104_fifo_init_pbdmas,
104 	.fini = gk104_fifo_fini,
105 	.intr = gk104_fifo_intr,
106 	.intr_mmu_fault_unit = gp100_fifo_intr_mmu_fault_unit,
107 	.mmu_fault = &gp100_fifo_mmu_fault,
108 	.engine_id = gk104_fifo_engine_id,
109 	.recover_chan = gk104_fifo_recover_chan,
110 	.runlist = &gm107_fifo_runlist,
111 	.nonstall = &gf100_fifo_nonstall,
112 	.runl = &gp100_runl,
113 	.runq = &gk208_runq,
114 	.engn = &gk104_engn,
115 	.engn_ce = &gk104_engn_ce,
116 	.cgrp = {{ 0, 0, KEPLER_CHANNEL_GROUP_A  }, &gk110_cgrp, .force = true },
117 	.chan = {{ 0, 0, PASCAL_CHANNEL_GPFIFO_A }, &gm107_chan, .ctor = &gk104_fifo_gpfifo_new },
118 };
119 
120 int
121 gp100_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
122 	       struct nvkm_fifo **pfifo)
123 {
124 	return gk104_fifo_new_(&gp100_fifo, device, type, inst, 0, pfifo);
125 }
126