1 /* 2 * Copyright 2016 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "runl.h" 25 #include "gk104.h" 26 #include "changk104.h" 27 28 #include <core/gpuobj.h> 29 #include <subdev/fault.h> 30 31 #include <nvif/class.h> 32 33 static void 34 gp100_runl_insert_chan(struct nvkm_chan *chan, struct nvkm_memory *memory, u64 offset) 35 { 36 nvkm_wo32(memory, offset + 0, chan->id | chan->runq << 14); 37 nvkm_wo32(memory, offset + 4, chan->inst->addr >> 12); 38 } 39 40 static const struct nvkm_runl_func 41 gp100_runl = { 42 .runqs = 2, 43 .size = 8, 44 .update = nv50_runl_update, 45 .insert_cgrp = gk110_runl_insert_cgrp, 46 .insert_chan = gp100_runl_insert_chan, 47 .commit = gk104_runl_commit, 48 .wait = nv50_runl_wait, 49 .pending = gk104_runl_pending, 50 .block = gk104_runl_block, 51 .allow = gk104_runl_allow, 52 .fault_clear = gk104_runl_fault_clear, 53 .preempt_pending = gf100_runl_preempt_pending, 54 }; 55 56 static const struct nvkm_enum 57 gp100_fifo_mmu_fault_engine[] = { 58 { 0x01, "DISPLAY" }, 59 { 0x03, "IFB", NULL, NVKM_ENGINE_IFB }, 60 { 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR }, 61 { 0x05, "BAR2", NULL, NVKM_SUBDEV_INSTMEM }, 62 { 0x06, "HOST0" }, 63 { 0x07, "HOST1" }, 64 { 0x08, "HOST2" }, 65 { 0x09, "HOST3" }, 66 { 0x0a, "HOST4" }, 67 { 0x0b, "HOST5" }, 68 { 0x0c, "HOST6" }, 69 { 0x0d, "HOST7" }, 70 { 0x0e, "HOST8" }, 71 { 0x0f, "HOST9" }, 72 { 0x10, "HOST10" }, 73 { 0x13, "PERF" }, 74 { 0x17, "PMU" }, 75 { 0x18, "PTP" }, 76 { 0x1f, "PHYSICAL" }, 77 {} 78 }; 79 80 static const struct nvkm_fifo_func_mmu_fault 81 gp100_fifo_mmu_fault = { 82 .recover = gf100_fifo_mmu_fault_recover, 83 .access = gf100_fifo_mmu_fault_access, 84 .engine = gp100_fifo_mmu_fault_engine, 85 .reason = gk104_fifo_mmu_fault_reason, 86 .hubclient = gk104_fifo_mmu_fault_hubclient, 87 .gpcclient = gk104_fifo_mmu_fault_gpcclient, 88 }; 89 90 static void 91 gp100_fifo_intr_mmu_fault_unit(struct nvkm_fifo *fifo, int unit) 92 { 93 struct nvkm_device *device = fifo->engine.subdev.device; 94 u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10)); 95 u32 valo = nvkm_rd32(device, 0x002804 + (unit * 0x10)); 96 u32 vahi = nvkm_rd32(device, 0x002808 + (unit * 0x10)); 97 u32 type = nvkm_rd32(device, 0x00280c + (unit * 0x10)); 98 struct nvkm_fault_data info; 99 100 info.inst = (u64)inst << 12; 101 info.addr = ((u64)vahi << 32) | valo; 102 info.time = 0; 103 info.engine = unit; 104 info.valid = 1; 105 info.gpc = (type & 0x1f000000) >> 24; 106 info.hub = (type & 0x00100000) >> 20; 107 info.access = (type & 0x00070000) >> 16; 108 info.client = (type & 0x00007f00) >> 8; 109 info.reason = (type & 0x0000001f); 110 111 nvkm_fifo_fault(fifo, &info); 112 } 113 114 static const struct nvkm_fifo_func 115 gp100_fifo = { 116 .dtor = gk104_fifo_dtor, 117 .oneinit = gk104_fifo_oneinit, 118 .chid_nr = gm200_fifo_chid_nr, 119 .chid_ctor = gk110_fifo_chid_ctor, 120 .runq_nr = gm200_fifo_runq_nr, 121 .runl_ctor = gk104_fifo_runl_ctor, 122 .init = gk104_fifo_init, 123 .init_pbdmas = gk104_fifo_init_pbdmas, 124 .intr = gk104_fifo_intr, 125 .intr_mmu_fault_unit = gp100_fifo_intr_mmu_fault_unit, 126 .intr_ctxsw_timeout = gf100_fifo_intr_ctxsw_timeout, 127 .mmu_fault = &gp100_fifo_mmu_fault, 128 .engine_id = gk104_fifo_engine_id, 129 .nonstall = &gf100_fifo_nonstall, 130 .runl = &gp100_runl, 131 .runq = &gk208_runq, 132 .engn = &gk104_engn, 133 .engn_ce = &gk104_engn_ce, 134 .cgrp = {{ 0, 0, KEPLER_CHANNEL_GROUP_A }, &gk110_cgrp, .force = true }, 135 .chan = {{ 0, 0, PASCAL_CHANNEL_GPFIFO_A }, &gm107_chan, .ctor = &gk104_fifo_gpfifo_new }, 136 }; 137 138 int 139 gp100_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, 140 struct nvkm_fifo **pfifo) 141 { 142 return gk104_fifo_new_(&gp100_fifo, device, type, inst, 0, pfifo); 143 } 144