xref: /linux/drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c (revision c0c914eca7f251c70facc37dfebeaf176601918d)
1 /*
2  * Copyright 2012 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs
23  */
24 #include "nv50.h"
25 #include "channv50.h"
26 
27 static void
28 g84_fifo_uevent_fini(struct nvkm_fifo *fifo)
29 {
30 	struct nvkm_device *device = fifo->engine.subdev.device;
31 	nvkm_mask(device, 0x002140, 0x40000000, 0x00000000);
32 }
33 
34 static void
35 g84_fifo_uevent_init(struct nvkm_fifo *fifo)
36 {
37 	struct nvkm_device *device = fifo->engine.subdev.device;
38 	nvkm_mask(device, 0x002140, 0x40000000, 0x40000000);
39 }
40 
41 static const struct nvkm_fifo_func
42 g84_fifo = {
43 	.dtor = nv50_fifo_dtor,
44 	.oneinit = nv50_fifo_oneinit,
45 	.init = nv50_fifo_init,
46 	.intr = nv04_fifo_intr,
47 	.pause = nv04_fifo_pause,
48 	.start = nv04_fifo_start,
49 	.uevent_init = g84_fifo_uevent_init,
50 	.uevent_fini = g84_fifo_uevent_fini,
51 	.chan = {
52 		&g84_fifo_dma_oclass,
53 		&g84_fifo_gpfifo_oclass,
54 		NULL
55 	},
56 };
57 
58 int
59 g84_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)
60 {
61 	return nv50_fifo_new_(&g84_fifo, device, index, pfifo);
62 }
63