1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include <subdev/vga.h> 25 26 u8 27 nv_rdport(void *obj, int head, u16 port) 28 { 29 struct nvkm_device *device = nv_device(obj); 30 31 if (device->card_type >= NV_50) 32 return nvkm_rd08(device, 0x601000 + port); 33 34 if (port == 0x03c0 || port == 0x03c1 || /* AR */ 35 port == 0x03c2 || port == 0x03da || /* INP0 */ 36 port == 0x03d4 || port == 0x03d5) /* CR */ 37 return nvkm_rd08(device, 0x601000 + (head * 0x2000) + port); 38 39 if (port == 0x03c2 || port == 0x03cc || /* MISC */ 40 port == 0x03c4 || port == 0x03c5 || /* SR */ 41 port == 0x03ce || port == 0x03cf) { /* GR */ 42 if (device->card_type < NV_40) 43 head = 0; /* CR44 selects head */ 44 return nvkm_rd08(device, 0x0c0000 + (head * 0x2000) + port); 45 } 46 47 return 0x00; 48 } 49 50 void 51 nv_wrport(void *obj, int head, u16 port, u8 data) 52 { 53 struct nvkm_device *device = nv_device(obj); 54 55 if (device->card_type >= NV_50) 56 nvkm_wr08(device, 0x601000 + port, data); 57 else 58 if (port == 0x03c0 || port == 0x03c1 || /* AR */ 59 port == 0x03c2 || port == 0x03da || /* INP0 */ 60 port == 0x03d4 || port == 0x03d5) /* CR */ 61 nvkm_wr08(device, 0x601000 + (head * 0x2000) + port, data); 62 else 63 if (port == 0x03c2 || port == 0x03cc || /* MISC */ 64 port == 0x03c4 || port == 0x03c5 || /* SR */ 65 port == 0x03ce || port == 0x03cf) { /* GR */ 66 if (device->card_type < NV_40) 67 head = 0; /* CR44 selects head */ 68 nvkm_wr08(device, 0x0c0000 + (head * 0x2000) + port, data); 69 } 70 } 71 72 u8 73 nv_rdvgas(void *obj, int head, u8 index) 74 { 75 nv_wrport(obj, head, 0x03c4, index); 76 return nv_rdport(obj, head, 0x03c5); 77 } 78 79 void 80 nv_wrvgas(void *obj, int head, u8 index, u8 value) 81 { 82 nv_wrport(obj, head, 0x03c4, index); 83 nv_wrport(obj, head, 0x03c5, value); 84 } 85 86 u8 87 nv_rdvgag(void *obj, int head, u8 index) 88 { 89 nv_wrport(obj, head, 0x03ce, index); 90 return nv_rdport(obj, head, 0x03cf); 91 } 92 93 void 94 nv_wrvgag(void *obj, int head, u8 index, u8 value) 95 { 96 nv_wrport(obj, head, 0x03ce, index); 97 nv_wrport(obj, head, 0x03cf, value); 98 } 99 100 u8 101 nv_rdvgac(void *obj, int head, u8 index) 102 { 103 nv_wrport(obj, head, 0x03d4, index); 104 return nv_rdport(obj, head, 0x03d5); 105 } 106 107 void 108 nv_wrvgac(void *obj, int head, u8 index, u8 value) 109 { 110 nv_wrport(obj, head, 0x03d4, index); 111 nv_wrport(obj, head, 0x03d5, value); 112 } 113 114 u8 115 nv_rdvgai(void *obj, int head, u16 port, u8 index) 116 { 117 if (port == 0x03c4) return nv_rdvgas(obj, head, index); 118 if (port == 0x03ce) return nv_rdvgag(obj, head, index); 119 if (port == 0x03d4) return nv_rdvgac(obj, head, index); 120 return 0x00; 121 } 122 123 void 124 nv_wrvgai(void *obj, int head, u16 port, u8 index, u8 value) 125 { 126 if (port == 0x03c4) nv_wrvgas(obj, head, index, value); 127 else if (port == 0x03ce) nv_wrvgag(obj, head, index, value); 128 else if (port == 0x03d4) nv_wrvgac(obj, head, index, value); 129 } 130 131 bool 132 nv_lockvgac(void *obj, bool lock) 133 { 134 struct nvkm_device *device = nv_device(obj); 135 136 bool locked = !nv_rdvgac(obj, 0, 0x1f); 137 u8 data = lock ? 0x99 : 0x57; 138 if (device->card_type < NV_50) 139 nv_wrvgac(obj, 0, 0x1f, data); 140 else 141 nv_wrvgac(obj, 0, 0x3f, data); 142 if (device->chipset == 0x11) { 143 if (!(nvkm_rd32(device, 0x001084) & 0x10000000)) 144 nv_wrvgac(obj, 1, 0x1f, data); 145 } 146 return locked; 147 } 148 149 /* CR44 takes values 0 (head A), 3 (head B) and 4 (heads tied) 150 * it affects only the 8 bit vga io regs, which we access using mmio at 151 * 0xc{0,2}3c*, 0x60{1,3}3*, and 0x68{1,3}3d* 152 * in general, the set value of cr44 does not matter: reg access works as 153 * expected and values can be set for the appropriate head by using a 0x2000 154 * offset as required 155 * however: 156 * a) pre nv40, the head B range of PRMVIO regs at 0xc23c* was not exposed and 157 * cr44 must be set to 0 or 3 for accessing values on the correct head 158 * through the common 0xc03c* addresses 159 * b) in tied mode (4) head B is programmed to the values set on head A, and 160 * access using the head B addresses can have strange results, ergo we leave 161 * tied mode in init once we know to what cr44 should be restored on exit 162 * 163 * the owner parameter is slightly abused: 164 * 0 and 1 are treated as head values and so the set value is (owner * 3) 165 * other values are treated as literal values to set 166 */ 167 u8 168 nv_rdvgaowner(void *obj) 169 { 170 struct nvkm_device *device = nv_device(obj); 171 if (device->card_type < NV_50) { 172 if (nv_device(obj)->chipset == 0x11) { 173 u32 tied = nvkm_rd32(device, 0x001084) & 0x10000000; 174 if (tied == 0) { 175 u8 slA = nv_rdvgac(obj, 0, 0x28) & 0x80; 176 u8 tvA = nv_rdvgac(obj, 0, 0x33) & 0x01; 177 u8 slB = nv_rdvgac(obj, 1, 0x28) & 0x80; 178 u8 tvB = nv_rdvgac(obj, 1, 0x33) & 0x01; 179 if (slA && !tvA) return 0x00; 180 if (slB && !tvB) return 0x03; 181 if (slA) return 0x00; 182 if (slB) return 0x03; 183 return 0x00; 184 } 185 return 0x04; 186 } 187 188 return nv_rdvgac(obj, 0, 0x44); 189 } 190 191 return 0x00; 192 } 193 194 void 195 nv_wrvgaowner(void *obj, u8 select) 196 { 197 if (nv_device(obj)->card_type < NV_50) { 198 u8 owner = (select == 1) ? 3 : select; 199 if (nv_device(obj)->chipset == 0x11) { 200 /* workaround hw lockup bug */ 201 nv_rdvgac(obj, 0, 0x1f); 202 nv_rdvgac(obj, 1, 0x1f); 203 } 204 205 nv_wrvgac(obj, 0, 0x44, owner); 206 207 if (nv_device(obj)->chipset == 0x11) { 208 nv_wrvgac(obj, 0, 0x2e, owner); 209 nv_wrvgac(obj, 0, 0x2e, owner); 210 } 211 } 212 } 213