1 /* 2 * Copyright 2018 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #include "chan.h" 23 #include "priv.h" 24 #include "head.h" 25 #include "ior.h" 26 27 #include <core/gpuobj.h> 28 #include <subdev/timer.h> 29 30 #include <nvif/class.h> 31 32 void 33 tu102_sor_dp_vcpi(struct nvkm_ior *sor, int head, u8 slot, u8 slot_nr, u16 pbn, u16 aligned) 34 { 35 struct nvkm_device *device = sor->disp->engine.subdev.device; 36 const u32 hoff = head * 0x800; 37 38 nvkm_mask(device, 0x61657c + hoff, 0xffffffff, (aligned << 16) | pbn); 39 nvkm_mask(device, 0x616578 + hoff, 0x00003f3f, (slot_nr << 8) | slot); 40 } 41 42 static int 43 tu102_sor_dp_links(struct nvkm_ior *sor, struct nvkm_i2c_aux *aux) 44 { 45 struct nvkm_device *device = sor->disp->engine.subdev.device; 46 const u32 soff = nv50_ior_base(sor); 47 const u32 loff = nv50_sor_link(sor); 48 u32 dpctrl = 0x00000000; 49 u32 clksor = 0x00000000; 50 51 clksor |= sor->dp.bw << 18; 52 dpctrl |= ((1 << sor->dp.nr) - 1) << 16; 53 if (sor->dp.mst) 54 dpctrl |= 0x40000000; 55 if (sor->dp.ef) 56 dpctrl |= 0x00004000; 57 58 nvkm_mask(device, 0x612300 + soff, 0x007c0000, clksor); 59 60 /*XXX*/ 61 nvkm_msec(device, 40, NVKM_DELAY); 62 nvkm_mask(device, 0x612300 + soff, 0x00030000, 0x00010000); 63 nvkm_mask(device, 0x61c10c + loff, 0x00000003, 0x00000001); 64 65 nvkm_mask(device, 0x61c10c + loff, 0x401f4000, dpctrl); 66 return 0; 67 } 68 69 static const struct nvkm_ior_func_dp 70 tu102_sor_dp = { 71 .lanes = { 0, 1, 2, 3 }, 72 .links = tu102_sor_dp_links, 73 .power = g94_sor_dp_power, 74 .pattern = gm107_sor_dp_pattern, 75 .drive = gm200_sor_dp_drive, 76 .vcpi = tu102_sor_dp_vcpi, 77 .audio = gv100_sor_dp_audio, 78 .audio_sym = gv100_sor_dp_audio_sym, 79 .watermark = gv100_sor_dp_watermark, 80 }; 81 82 static const struct nvkm_ior_func 83 tu102_sor = { 84 .route = { 85 .get = gm200_sor_route_get, 86 .set = gm200_sor_route_set, 87 }, 88 .state = gv100_sor_state, 89 .power = nv50_sor_power, 90 .clock = gf119_sor_clock, 91 .bl = >215_sor_bl, 92 .hdmi = &gv100_sor_hdmi, 93 .dp = &tu102_sor_dp, 94 .hda = &gv100_sor_hda, 95 }; 96 97 static int 98 tu102_sor_new(struct nvkm_disp *disp, int id) 99 { 100 struct nvkm_device *device = disp->engine.subdev.device; 101 u32 hda = nvkm_rd32(device, 0x08a15c); 102 103 return nvkm_ior_new_(&tu102_sor, disp, SOR, id, hda & BIT(id)); 104 } 105 106 int 107 tu102_disp_init(struct nvkm_disp *disp) 108 { 109 struct nvkm_device *device = disp->engine.subdev.device; 110 struct nvkm_head *head; 111 int i, j; 112 u32 tmp; 113 114 /* Claim ownership of display. */ 115 if (nvkm_rd32(device, 0x6254e8) & 0x00000002) { 116 nvkm_mask(device, 0x6254e8, 0x00000001, 0x00000000); 117 if (nvkm_msec(device, 2000, 118 if (!(nvkm_rd32(device, 0x6254e8) & 0x00000002)) 119 break; 120 ) < 0) 121 return -EBUSY; 122 } 123 124 /* Lock pin capabilities. */ 125 tmp = 0x00000021; /*XXX*/ 126 nvkm_wr32(device, 0x640008, tmp); 127 128 /* SOR capabilities. */ 129 for (i = 0; i < disp->sor.nr; i++) { 130 tmp = nvkm_rd32(device, 0x61c000 + (i * 0x800)); 131 nvkm_mask(device, 0x640000, 0x00000100 << i, 0x00000100 << i); 132 nvkm_wr32(device, 0x640144 + (i * 0x08), tmp); 133 } 134 135 /* Head capabilities. */ 136 list_for_each_entry(head, &disp->heads, head) { 137 const int id = head->id; 138 139 /* RG. */ 140 tmp = nvkm_rd32(device, 0x616300 + (id * 0x800)); 141 nvkm_wr32(device, 0x640048 + (id * 0x020), tmp); 142 143 /* POSTCOMP. */ 144 for (j = 0; j < 5 * 4; j += 4) { 145 tmp = nvkm_rd32(device, 0x616140 + (id * 0x800) + j); 146 nvkm_wr32(device, 0x640680 + (id * 0x20) + j, tmp); 147 } 148 } 149 150 /* Window capabilities. */ 151 for (i = 0; i < disp->wndw.nr; i++) { 152 nvkm_mask(device, 0x640004, 1 << i, 1 << i); 153 for (j = 0; j < 6 * 4; j += 4) { 154 tmp = nvkm_rd32(device, 0x630100 + (i * 0x800) + j); 155 nvkm_mask(device, 0x640780 + (i * 0x20) + j, 0xffffffff, tmp); 156 } 157 nvkm_mask(device, 0x64000c, 0x00000100, 0x00000100); 158 } 159 160 /* IHUB capabilities. */ 161 for (i = 0; i < 3; i++) { 162 tmp = nvkm_rd32(device, 0x62e000 + (i * 0x04)); 163 nvkm_wr32(device, 0x640010 + (i * 0x04), tmp); 164 } 165 166 nvkm_mask(device, 0x610078, 0x00000001, 0x00000001); 167 168 /* Setup instance memory. */ 169 switch (nvkm_memory_target(disp->inst->memory)) { 170 case NVKM_MEM_TARGET_VRAM: tmp = 0x00000001; break; 171 case NVKM_MEM_TARGET_NCOH: tmp = 0x00000002; break; 172 case NVKM_MEM_TARGET_HOST: tmp = 0x00000003; break; 173 default: 174 break; 175 } 176 nvkm_wr32(device, 0x610010, 0x00000008 | tmp); 177 nvkm_wr32(device, 0x610014, disp->inst->addr >> 16); 178 179 /* CTRL_DISP: AWAKEN, ERROR, SUPERVISOR[1-3]. */ 180 nvkm_wr32(device, 0x611cf0, 0x00000187); /* MSK. */ 181 nvkm_wr32(device, 0x611db0, 0x00000187); /* EN. */ 182 183 /* EXC_OTHER: CURSn, CORE. */ 184 nvkm_wr32(device, 0x611cec, disp->head.mask << 16 | 185 0x00000001); /* MSK. */ 186 nvkm_wr32(device, 0x611dac, 0x00000000); /* EN. */ 187 188 /* EXC_WINIM. */ 189 nvkm_wr32(device, 0x611ce8, disp->wndw.mask); /* MSK. */ 190 nvkm_wr32(device, 0x611da8, 0x00000000); /* EN. */ 191 192 /* EXC_WIN. */ 193 nvkm_wr32(device, 0x611ce4, disp->wndw.mask); /* MSK. */ 194 nvkm_wr32(device, 0x611da4, 0x00000000); /* EN. */ 195 196 /* HEAD_TIMING(n): VBLANK. */ 197 list_for_each_entry(head, &disp->heads, head) { 198 const u32 hoff = head->id * 4; 199 nvkm_wr32(device, 0x611cc0 + hoff, 0x00000004); /* MSK. */ 200 nvkm_wr32(device, 0x611d80 + hoff, 0x00000000); /* EN. */ 201 } 202 203 /* OR. */ 204 nvkm_wr32(device, 0x611cf4, 0x00000000); /* MSK. */ 205 nvkm_wr32(device, 0x611db4, 0x00000000); /* EN. */ 206 return 0; 207 } 208 209 static const struct nvkm_disp_func 210 tu102_disp = { 211 .oneinit = nv50_disp_oneinit, 212 .init = tu102_disp_init, 213 .fini = gv100_disp_fini, 214 .intr = gv100_disp_intr, 215 .super = gv100_disp_super, 216 .uevent = &gv100_disp_chan_uevent, 217 .wndw = { .cnt = gv100_disp_wndw_cnt }, 218 .head = { .cnt = gv100_head_cnt, .new = gv100_head_new }, 219 .sor = { .cnt = gv100_sor_cnt, .new = tu102_sor_new }, 220 .ramht_size = 0x2000, 221 .root = { 0, 0,TU102_DISP }, 222 .user = { 223 {{-1,-1,GV100_DISP_CAPS }, gv100_disp_caps_new }, 224 {{ 0, 0,TU102_DISP_CURSOR }, nvkm_disp_chan_new, &gv100_disp_curs }, 225 {{ 0, 0,TU102_DISP_WINDOW_IMM_CHANNEL_DMA}, nvkm_disp_wndw_new, &gv100_disp_wimm }, 226 {{ 0, 0,TU102_DISP_CORE_CHANNEL_DMA }, nvkm_disp_core_new, &gv100_disp_core }, 227 {{ 0, 0,TU102_DISP_WINDOW_CHANNEL_DMA }, nvkm_disp_wndw_new, &gv100_disp_wndw }, 228 {} 229 }, 230 }; 231 232 int 233 tu102_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, 234 struct nvkm_disp **pdisp) 235 { 236 return nvkm_disp_new_(&tu102_disp, device, type, inst, pdisp); 237 } 238