1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "nv50.h" 25 #include "rootnv50.h" 26 27 #include <core/client.h> 28 #include <core/enum.h> 29 #include <core/gpuobj.h> 30 #include <subdev/bios.h> 31 #include <subdev/bios/disp.h> 32 #include <subdev/bios/init.h> 33 #include <subdev/bios/pll.h> 34 #include <subdev/devinit.h> 35 #include <subdev/timer.h> 36 37 static const struct nvkm_disp_oclass * 38 nv50_disp_root_(struct nvkm_disp *base) 39 { 40 return nv50_disp(base)->func->root; 41 } 42 43 static int 44 nv50_disp_outp_internal_crt_(struct nvkm_disp *base, int index, 45 struct dcb_output *dcb, struct nvkm_output **poutp) 46 { 47 struct nv50_disp *disp = nv50_disp(base); 48 return disp->func->outp.internal.crt(base, index, dcb, poutp); 49 } 50 51 static int 52 nv50_disp_outp_internal_tmds_(struct nvkm_disp *base, int index, 53 struct dcb_output *dcb, 54 struct nvkm_output **poutp) 55 { 56 struct nv50_disp *disp = nv50_disp(base); 57 return disp->func->outp.internal.tmds(base, index, dcb, poutp); 58 } 59 60 static int 61 nv50_disp_outp_internal_lvds_(struct nvkm_disp *base, int index, 62 struct dcb_output *dcb, 63 struct nvkm_output **poutp) 64 { 65 struct nv50_disp *disp = nv50_disp(base); 66 return disp->func->outp.internal.lvds(base, index, dcb, poutp); 67 } 68 69 static int 70 nv50_disp_outp_internal_dp_(struct nvkm_disp *base, int index, 71 struct dcb_output *dcb, struct nvkm_output **poutp) 72 { 73 struct nv50_disp *disp = nv50_disp(base); 74 if (disp->func->outp.internal.dp) 75 return disp->func->outp.internal.dp(base, index, dcb, poutp); 76 return -ENODEV; 77 } 78 79 static int 80 nv50_disp_outp_external_tmds_(struct nvkm_disp *base, int index, 81 struct dcb_output *dcb, 82 struct nvkm_output **poutp) 83 { 84 struct nv50_disp *disp = nv50_disp(base); 85 if (disp->func->outp.external.tmds) 86 return disp->func->outp.external.tmds(base, index, dcb, poutp); 87 return -ENODEV; 88 } 89 90 static int 91 nv50_disp_outp_external_dp_(struct nvkm_disp *base, int index, 92 struct dcb_output *dcb, struct nvkm_output **poutp) 93 { 94 struct nv50_disp *disp = nv50_disp(base); 95 if (disp->func->outp.external.dp) 96 return disp->func->outp.external.dp(base, index, dcb, poutp); 97 return -ENODEV; 98 } 99 100 static void 101 nv50_disp_vblank_fini_(struct nvkm_disp *base, int head) 102 { 103 struct nv50_disp *disp = nv50_disp(base); 104 disp->func->head.vblank_fini(disp, head); 105 } 106 107 static void 108 nv50_disp_vblank_init_(struct nvkm_disp *base, int head) 109 { 110 struct nv50_disp *disp = nv50_disp(base); 111 disp->func->head.vblank_init(disp, head); 112 } 113 114 static void 115 nv50_disp_intr_(struct nvkm_disp *base) 116 { 117 struct nv50_disp *disp = nv50_disp(base); 118 disp->func->intr(disp); 119 } 120 121 static void * 122 nv50_disp_dtor_(struct nvkm_disp *base) 123 { 124 struct nv50_disp *disp = nv50_disp(base); 125 nvkm_event_fini(&disp->uevent); 126 return disp; 127 } 128 129 static const struct nvkm_disp_func 130 nv50_disp_ = { 131 .dtor = nv50_disp_dtor_, 132 .intr = nv50_disp_intr_, 133 .root = nv50_disp_root_, 134 .outp.internal.crt = nv50_disp_outp_internal_crt_, 135 .outp.internal.tmds = nv50_disp_outp_internal_tmds_, 136 .outp.internal.lvds = nv50_disp_outp_internal_lvds_, 137 .outp.internal.dp = nv50_disp_outp_internal_dp_, 138 .outp.external.tmds = nv50_disp_outp_external_tmds_, 139 .outp.external.dp = nv50_disp_outp_external_dp_, 140 .head.vblank_init = nv50_disp_vblank_init_, 141 .head.vblank_fini = nv50_disp_vblank_fini_, 142 }; 143 144 int 145 nv50_disp_new_(const struct nv50_disp_func *func, struct nvkm_device *device, 146 int index, int heads, struct nvkm_disp **pdisp) 147 { 148 struct nv50_disp *disp; 149 int ret; 150 151 if (!(disp = kzalloc(sizeof(*disp), GFP_KERNEL))) 152 return -ENOMEM; 153 INIT_WORK(&disp->supervisor, func->super); 154 disp->func = func; 155 *pdisp = &disp->base; 156 157 ret = nvkm_disp_ctor(&nv50_disp_, device, index, heads, &disp->base); 158 if (ret) 159 return ret; 160 161 return nvkm_event_init(func->uevent, 1, 1 + (heads * 4), &disp->uevent); 162 } 163 164 void 165 nv50_disp_vblank_fini(struct nv50_disp *disp, int head) 166 { 167 struct nvkm_device *device = disp->base.engine.subdev.device; 168 nvkm_mask(device, 0x61002c, (4 << head), 0); 169 } 170 171 void 172 nv50_disp_vblank_init(struct nv50_disp *disp, int head) 173 { 174 struct nvkm_device *device = disp->base.engine.subdev.device; 175 nvkm_mask(device, 0x61002c, (4 << head), (4 << head)); 176 } 177 178 static const struct nvkm_enum 179 nv50_disp_intr_error_type[] = { 180 { 3, "ILLEGAL_MTHD" }, 181 { 4, "INVALID_VALUE" }, 182 { 5, "INVALID_STATE" }, 183 { 7, "INVALID_HANDLE" }, 184 {} 185 }; 186 187 static const struct nvkm_enum 188 nv50_disp_intr_error_code[] = { 189 { 0x00, "" }, 190 {} 191 }; 192 193 static void 194 nv50_disp_intr_error(struct nv50_disp *disp, int chid) 195 { 196 struct nvkm_subdev *subdev = &disp->base.engine.subdev; 197 struct nvkm_device *device = subdev->device; 198 u32 data = nvkm_rd32(device, 0x610084 + (chid * 0x08)); 199 u32 addr = nvkm_rd32(device, 0x610080 + (chid * 0x08)); 200 u32 code = (addr & 0x00ff0000) >> 16; 201 u32 type = (addr & 0x00007000) >> 12; 202 u32 mthd = (addr & 0x00000ffc); 203 const struct nvkm_enum *ec, *et; 204 205 et = nvkm_enum_find(nv50_disp_intr_error_type, type); 206 ec = nvkm_enum_find(nv50_disp_intr_error_code, code); 207 208 nvkm_error(subdev, 209 "ERROR %d [%s] %02x [%s] chid %d mthd %04x data %08x\n", 210 type, et ? et->name : "", code, ec ? ec->name : "", 211 chid, mthd, data); 212 213 if (chid < ARRAY_SIZE(disp->chan)) { 214 switch (mthd) { 215 case 0x0080: 216 nv50_disp_chan_mthd(disp->chan[chid], NV_DBG_ERROR); 217 break; 218 default: 219 break; 220 } 221 } 222 223 nvkm_wr32(device, 0x610020, 0x00010000 << chid); 224 nvkm_wr32(device, 0x610080 + (chid * 0x08), 0x90000000); 225 } 226 227 static struct nvkm_output * 228 exec_lookup(struct nv50_disp *disp, int head, int or, u32 ctrl, 229 u32 *data, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, 230 struct nvbios_outp *info) 231 { 232 struct nvkm_subdev *subdev = &disp->base.engine.subdev; 233 struct nvkm_bios *bios = subdev->device->bios; 234 struct nvkm_output *outp; 235 u16 mask, type; 236 237 if (or < 4) { 238 type = DCB_OUTPUT_ANALOG; 239 mask = 0; 240 } else 241 if (or < 8) { 242 switch (ctrl & 0x00000f00) { 243 case 0x00000000: type = DCB_OUTPUT_LVDS; mask = 1; break; 244 case 0x00000100: type = DCB_OUTPUT_TMDS; mask = 1; break; 245 case 0x00000200: type = DCB_OUTPUT_TMDS; mask = 2; break; 246 case 0x00000500: type = DCB_OUTPUT_TMDS; mask = 3; break; 247 case 0x00000800: type = DCB_OUTPUT_DP; mask = 1; break; 248 case 0x00000900: type = DCB_OUTPUT_DP; mask = 2; break; 249 default: 250 nvkm_error(subdev, "unknown SOR mc %08x\n", ctrl); 251 return NULL; 252 } 253 or -= 4; 254 } else { 255 or = or - 8; 256 type = 0x0010; 257 mask = 0; 258 switch (ctrl & 0x00000f00) { 259 case 0x00000000: type |= disp->pior.type[or]; break; 260 default: 261 nvkm_error(subdev, "unknown PIOR mc %08x\n", ctrl); 262 return NULL; 263 } 264 } 265 266 mask = 0x00c0 & (mask << 6); 267 mask |= 0x0001 << or; 268 mask |= 0x0100 << head; 269 270 list_for_each_entry(outp, &disp->base.outp, head) { 271 if ((outp->info.hasht & 0xff) == type && 272 (outp->info.hashm & mask) == mask) { 273 *data = nvbios_outp_match(bios, outp->info.hasht, mask, 274 ver, hdr, cnt, len, info); 275 if (!*data) 276 return NULL; 277 return outp; 278 } 279 } 280 281 return NULL; 282 } 283 284 static struct nvkm_output * 285 exec_script(struct nv50_disp *disp, int head, int id) 286 { 287 struct nvkm_subdev *subdev = &disp->base.engine.subdev; 288 struct nvkm_device *device = subdev->device; 289 struct nvkm_bios *bios = device->bios; 290 struct nvkm_output *outp; 291 struct nvbios_outp info; 292 u8 ver, hdr, cnt, len; 293 u32 data, ctrl = 0; 294 u32 reg; 295 int i; 296 297 /* DAC */ 298 for (i = 0; !(ctrl & (1 << head)) && i < disp->func->dac.nr; i++) 299 ctrl = nvkm_rd32(device, 0x610b5c + (i * 8)); 300 301 /* SOR */ 302 if (!(ctrl & (1 << head))) { 303 if (device->chipset < 0x90 || 304 device->chipset == 0x92 || 305 device->chipset == 0xa0) { 306 reg = 0x610b74; 307 } else { 308 reg = 0x610798; 309 } 310 for (i = 0; !(ctrl & (1 << head)) && i < disp->func->sor.nr; i++) 311 ctrl = nvkm_rd32(device, reg + (i * 8)); 312 i += 4; 313 } 314 315 /* PIOR */ 316 if (!(ctrl & (1 << head))) { 317 for (i = 0; !(ctrl & (1 << head)) && i < disp->func->pior.nr; i++) 318 ctrl = nvkm_rd32(device, 0x610b84 + (i * 8)); 319 i += 8; 320 } 321 322 if (!(ctrl & (1 << head))) 323 return NULL; 324 i--; 325 326 outp = exec_lookup(disp, head, i, ctrl, &data, &ver, &hdr, &cnt, &len, &info); 327 if (outp) { 328 struct nvbios_init init = { 329 .subdev = subdev, 330 .bios = bios, 331 .offset = info.script[id], 332 .outp = &outp->info, 333 .crtc = head, 334 .execute = 1, 335 }; 336 337 nvbios_exec(&init); 338 } 339 340 return outp; 341 } 342 343 static struct nvkm_output * 344 exec_clkcmp(struct nv50_disp *disp, int head, int id, u32 pclk, u32 *conf) 345 { 346 struct nvkm_subdev *subdev = &disp->base.engine.subdev; 347 struct nvkm_device *device = subdev->device; 348 struct nvkm_bios *bios = device->bios; 349 struct nvkm_output *outp; 350 struct nvbios_outp info1; 351 struct nvbios_ocfg info2; 352 u8 ver, hdr, cnt, len; 353 u32 data, ctrl = 0; 354 u32 reg; 355 int i; 356 357 /* DAC */ 358 for (i = 0; !(ctrl & (1 << head)) && i < disp->func->dac.nr; i++) 359 ctrl = nvkm_rd32(device, 0x610b58 + (i * 8)); 360 361 /* SOR */ 362 if (!(ctrl & (1 << head))) { 363 if (device->chipset < 0x90 || 364 device->chipset == 0x92 || 365 device->chipset == 0xa0) { 366 reg = 0x610b70; 367 } else { 368 reg = 0x610794; 369 } 370 for (i = 0; !(ctrl & (1 << head)) && i < disp->func->sor.nr; i++) 371 ctrl = nvkm_rd32(device, reg + (i * 8)); 372 i += 4; 373 } 374 375 /* PIOR */ 376 if (!(ctrl & (1 << head))) { 377 for (i = 0; !(ctrl & (1 << head)) && i < disp->func->pior.nr; i++) 378 ctrl = nvkm_rd32(device, 0x610b80 + (i * 8)); 379 i += 8; 380 } 381 382 if (!(ctrl & (1 << head))) 383 return NULL; 384 i--; 385 386 outp = exec_lookup(disp, head, i, ctrl, &data, &ver, &hdr, &cnt, &len, &info1); 387 if (!outp) 388 return NULL; 389 390 *conf = (ctrl & 0x00000f00) >> 8; 391 if (outp->info.location == 0) { 392 switch (outp->info.type) { 393 case DCB_OUTPUT_TMDS: 394 if (*conf == 5) 395 *conf |= 0x0100; 396 break; 397 case DCB_OUTPUT_LVDS: 398 *conf |= disp->sor.lvdsconf; 399 break; 400 default: 401 break; 402 } 403 } else { 404 *conf = (ctrl & 0x00000f00) >> 8; 405 pclk = pclk / 2; 406 } 407 408 data = nvbios_ocfg_match(bios, data, *conf & 0xff, *conf >> 8, 409 &ver, &hdr, &cnt, &len, &info2); 410 if (data && id < 0xff) { 411 data = nvbios_oclk_match(bios, info2.clkcmp[id], pclk); 412 if (data) { 413 struct nvbios_init init = { 414 .subdev = subdev, 415 .bios = bios, 416 .offset = data, 417 .outp = &outp->info, 418 .crtc = head, 419 .execute = 1, 420 }; 421 422 nvbios_exec(&init); 423 } 424 } 425 426 return outp; 427 } 428 429 static bool 430 nv50_disp_dptmds_war(struct nvkm_device *device) 431 { 432 switch (device->chipset) { 433 case 0x94: 434 case 0x96: 435 case 0x98: 436 return true; 437 default: 438 break; 439 } 440 return false; 441 } 442 443 static bool 444 nv50_disp_dptmds_war_needed(struct nv50_disp *disp, struct dcb_output *outp) 445 { 446 struct nvkm_device *device = disp->base.engine.subdev.device; 447 const u32 soff = __ffs(outp->or) * 0x800; 448 if (nv50_disp_dptmds_war(device) && outp->type == DCB_OUTPUT_TMDS) { 449 switch (nvkm_rd32(device, 0x614300 + soff) & 0x00030000) { 450 case 0x00000000: 451 case 0x00030000: 452 return true; 453 default: 454 break; 455 } 456 } 457 return false; 458 459 } 460 461 static void 462 nv50_disp_dptmds_war_2(struct nv50_disp *disp, struct dcb_output *outp) 463 { 464 struct nvkm_device *device = disp->base.engine.subdev.device; 465 const u32 soff = __ffs(outp->or) * 0x800; 466 467 if (!nv50_disp_dptmds_war_needed(disp, outp)) 468 return; 469 470 nvkm_mask(device, 0x00e840, 0x80000000, 0x80000000); 471 nvkm_mask(device, 0x614300 + soff, 0x03000000, 0x03000000); 472 nvkm_mask(device, 0x61c10c + soff, 0x00000001, 0x00000001); 473 474 nvkm_mask(device, 0x61c00c + soff, 0x0f000000, 0x00000000); 475 nvkm_mask(device, 0x61c008 + soff, 0xff000000, 0x14000000); 476 nvkm_usec(device, 400, NVKM_DELAY); 477 nvkm_mask(device, 0x61c008 + soff, 0xff000000, 0x00000000); 478 nvkm_mask(device, 0x61c00c + soff, 0x0f000000, 0x01000000); 479 480 if (nvkm_rd32(device, 0x61c004 + soff) & 0x00000001) { 481 u32 seqctl = nvkm_rd32(device, 0x61c030 + soff); 482 u32 pu_pc = seqctl & 0x0000000f; 483 nvkm_wr32(device, 0x61c040 + soff + pu_pc * 4, 0x1f008000); 484 } 485 } 486 487 static void 488 nv50_disp_dptmds_war_3(struct nv50_disp *disp, struct dcb_output *outp) 489 { 490 struct nvkm_device *device = disp->base.engine.subdev.device; 491 const u32 soff = __ffs(outp->or) * 0x800; 492 u32 sorpwr; 493 494 if (!nv50_disp_dptmds_war_needed(disp, outp)) 495 return; 496 497 sorpwr = nvkm_rd32(device, 0x61c004 + soff); 498 if (sorpwr & 0x00000001) { 499 u32 seqctl = nvkm_rd32(device, 0x61c030 + soff); 500 u32 pd_pc = (seqctl & 0x00000f00) >> 8; 501 u32 pu_pc = seqctl & 0x0000000f; 502 503 nvkm_wr32(device, 0x61c040 + soff + pd_pc * 4, 0x1f008000); 504 505 nvkm_msec(device, 2000, 506 if (!(nvkm_rd32(device, 0x61c030 + soff) & 0x10000000)) 507 break; 508 ); 509 nvkm_mask(device, 0x61c004 + soff, 0x80000001, 0x80000000); 510 nvkm_msec(device, 2000, 511 if (!(nvkm_rd32(device, 0x61c030 + soff) & 0x10000000)) 512 break; 513 ); 514 515 nvkm_wr32(device, 0x61c040 + soff + pd_pc * 4, 0x00002000); 516 nvkm_wr32(device, 0x61c040 + soff + pu_pc * 4, 0x1f000000); 517 } 518 519 nvkm_mask(device, 0x61c10c + soff, 0x00000001, 0x00000000); 520 nvkm_mask(device, 0x614300 + soff, 0x03000000, 0x00000000); 521 522 if (sorpwr & 0x00000001) { 523 nvkm_mask(device, 0x61c004 + soff, 0x80000001, 0x80000001); 524 } 525 } 526 527 static void 528 nv50_disp_update_sppll1(struct nv50_disp *disp) 529 { 530 struct nvkm_device *device = disp->base.engine.subdev.device; 531 bool used = false; 532 int sor; 533 534 if (!nv50_disp_dptmds_war(device)) 535 return; 536 537 for (sor = 0; sor < disp->func->sor.nr; sor++) { 538 u32 clksor = nvkm_rd32(device, 0x614300 + (sor * 0x800)); 539 switch (clksor & 0x03000000) { 540 case 0x02000000: 541 case 0x03000000: 542 used = true; 543 break; 544 default: 545 break; 546 } 547 } 548 549 if (used) 550 return; 551 552 nvkm_mask(device, 0x00e840, 0x80000000, 0x00000000); 553 } 554 555 static void 556 nv50_disp_intr_unk10_0(struct nv50_disp *disp, int head) 557 { 558 exec_script(disp, head, 1); 559 } 560 561 static void 562 nv50_disp_intr_unk20_0(struct nv50_disp *disp, int head) 563 { 564 struct nvkm_subdev *subdev = &disp->base.engine.subdev; 565 struct nvkm_output *outp = exec_script(disp, head, 2); 566 567 /* the binary driver does this outside of the supervisor handling 568 * (after the third supervisor from a detach). we (currently?) 569 * allow both detach/attach to happen in the same set of 570 * supervisor interrupts, so it would make sense to execute this 571 * (full power down?) script after all the detach phases of the 572 * supervisor handling. like with training if needed from the 573 * second supervisor, nvidia doesn't do this, so who knows if it's 574 * entirely safe, but it does appear to work.. 575 * 576 * without this script being run, on some configurations i've 577 * seen, switching from DP to TMDS on a DP connector may result 578 * in a blank screen (SOR_PWR off/on can restore it) 579 */ 580 if (outp && outp->info.type == DCB_OUTPUT_DP) { 581 struct nvkm_output_dp *outpdp = nvkm_output_dp(outp); 582 struct nvbios_init init = { 583 .subdev = subdev, 584 .bios = subdev->device->bios, 585 .outp = &outp->info, 586 .crtc = head, 587 .offset = outpdp->info.script[4], 588 .execute = 1, 589 }; 590 591 nvkm_notify_put(&outpdp->irq); 592 nvbios_exec(&init); 593 atomic_set(&outpdp->lt.done, 0); 594 } 595 } 596 597 static void 598 nv50_disp_intr_unk20_1(struct nv50_disp *disp, int head) 599 { 600 struct nvkm_device *device = disp->base.engine.subdev.device; 601 struct nvkm_devinit *devinit = device->devinit; 602 u32 pclk = nvkm_rd32(device, 0x610ad0 + (head * 0x540)) & 0x3fffff; 603 if (pclk) 604 nvkm_devinit_pll_set(devinit, PLL_VPLL0 + head, pclk); 605 } 606 607 static void 608 nv50_disp_intr_unk20_2_dp(struct nv50_disp *disp, int head, 609 struct dcb_output *outp, u32 pclk) 610 { 611 struct nvkm_subdev *subdev = &disp->base.engine.subdev; 612 struct nvkm_device *device = subdev->device; 613 const int link = !(outp->sorconf.link & 1); 614 const int or = ffs(outp->or) - 1; 615 const u32 soff = ( or * 0x800); 616 const u32 loff = (link * 0x080) + soff; 617 const u32 ctrl = nvkm_rd32(device, 0x610794 + (or * 8)); 618 const u32 symbol = 100000; 619 const s32 vactive = nvkm_rd32(device, 0x610af8 + (head * 0x540)) & 0xffff; 620 const s32 vblanke = nvkm_rd32(device, 0x610ae8 + (head * 0x540)) & 0xffff; 621 const s32 vblanks = nvkm_rd32(device, 0x610af0 + (head * 0x540)) & 0xffff; 622 u32 dpctrl = nvkm_rd32(device, 0x61c10c + loff); 623 u32 clksor = nvkm_rd32(device, 0x614300 + soff); 624 int bestTU = 0, bestVTUi = 0, bestVTUf = 0, bestVTUa = 0; 625 int TU, VTUi, VTUf, VTUa; 626 u64 link_data_rate, link_ratio, unk; 627 u32 best_diff = 64 * symbol; 628 u32 link_nr, link_bw, bits; 629 u64 value; 630 631 link_bw = (clksor & 0x000c0000) ? 270000 : 162000; 632 link_nr = hweight32(dpctrl & 0x000f0000); 633 634 /* symbols/hblank - algorithm taken from comments in tegra driver */ 635 value = vblanke + vactive - vblanks - 7; 636 value = value * link_bw; 637 do_div(value, pclk); 638 value = value - (3 * !!(dpctrl & 0x00004000)) - (12 / link_nr); 639 nvkm_mask(device, 0x61c1e8 + soff, 0x0000ffff, value); 640 641 /* symbols/vblank - algorithm taken from comments in tegra driver */ 642 value = vblanks - vblanke - 25; 643 value = value * link_bw; 644 do_div(value, pclk); 645 value = value - ((36 / link_nr) + 3) - 1; 646 nvkm_mask(device, 0x61c1ec + soff, 0x00ffffff, value); 647 648 /* watermark / activesym */ 649 if ((ctrl & 0xf0000) == 0x60000) bits = 30; 650 else if ((ctrl & 0xf0000) == 0x50000) bits = 24; 651 else bits = 18; 652 653 link_data_rate = (pclk * bits / 8) / link_nr; 654 655 /* calculate ratio of packed data rate to link symbol rate */ 656 link_ratio = link_data_rate * symbol; 657 do_div(link_ratio, link_bw); 658 659 for (TU = 64; TU >= 32; TU--) { 660 /* calculate average number of valid symbols in each TU */ 661 u32 tu_valid = link_ratio * TU; 662 u32 calc, diff; 663 664 /* find a hw representation for the fraction.. */ 665 VTUi = tu_valid / symbol; 666 calc = VTUi * symbol; 667 diff = tu_valid - calc; 668 if (diff) { 669 if (diff >= (symbol / 2)) { 670 VTUf = symbol / (symbol - diff); 671 if (symbol - (VTUf * diff)) 672 VTUf++; 673 674 if (VTUf <= 15) { 675 VTUa = 1; 676 calc += symbol - (symbol / VTUf); 677 } else { 678 VTUa = 0; 679 VTUf = 1; 680 calc += symbol; 681 } 682 } else { 683 VTUa = 0; 684 VTUf = min((int)(symbol / diff), 15); 685 calc += symbol / VTUf; 686 } 687 688 diff = calc - tu_valid; 689 } else { 690 /* no remainder, but the hw doesn't like the fractional 691 * part to be zero. decrement the integer part and 692 * have the fraction add a whole symbol back 693 */ 694 VTUa = 0; 695 VTUf = 1; 696 VTUi--; 697 } 698 699 if (diff < best_diff) { 700 best_diff = diff; 701 bestTU = TU; 702 bestVTUa = VTUa; 703 bestVTUf = VTUf; 704 bestVTUi = VTUi; 705 if (diff == 0) 706 break; 707 } 708 } 709 710 if (!bestTU) { 711 nvkm_error(subdev, "unable to find suitable dp config\n"); 712 return; 713 } 714 715 /* XXX close to vbios numbers, but not right */ 716 unk = (symbol - link_ratio) * bestTU; 717 unk *= link_ratio; 718 do_div(unk, symbol); 719 do_div(unk, symbol); 720 unk += 6; 721 722 nvkm_mask(device, 0x61c10c + loff, 0x000001fc, bestTU << 2); 723 nvkm_mask(device, 0x61c128 + loff, 0x010f7f3f, bestVTUa << 24 | 724 bestVTUf << 16 | 725 bestVTUi << 8 | unk); 726 } 727 728 static void 729 nv50_disp_intr_unk20_2(struct nv50_disp *disp, int head) 730 { 731 struct nvkm_device *device = disp->base.engine.subdev.device; 732 struct nvkm_output *outp; 733 u32 pclk = nvkm_rd32(device, 0x610ad0 + (head * 0x540)) & 0x3fffff; 734 u32 hval, hreg = 0x614200 + (head * 0x800); 735 u32 oval, oreg; 736 u32 mask, conf; 737 738 outp = exec_clkcmp(disp, head, 0xff, pclk, &conf); 739 if (!outp) 740 return; 741 742 /* we allow both encoder attach and detach operations to occur 743 * within a single supervisor (ie. modeset) sequence. the 744 * encoder detach scripts quite often switch off power to the 745 * lanes, which requires the link to be re-trained. 746 * 747 * this is not generally an issue as the sink "must" (heh) 748 * signal an irq when it's lost sync so the driver can 749 * re-train. 750 * 751 * however, on some boards, if one does not configure at least 752 * the gpu side of the link *before* attaching, then various 753 * things can go horribly wrong (PDISP disappearing from mmio, 754 * third supervisor never happens, etc). 755 * 756 * the solution is simply to retrain here, if necessary. last 757 * i checked, the binary driver userspace does not appear to 758 * trigger this situation (it forces an UPDATE between steps). 759 */ 760 if (outp->info.type == DCB_OUTPUT_DP) { 761 u32 soff = (ffs(outp->info.or) - 1) * 0x08; 762 u32 ctrl, datarate; 763 764 if (outp->info.location == 0) { 765 ctrl = nvkm_rd32(device, 0x610794 + soff); 766 soff = 1; 767 } else { 768 ctrl = nvkm_rd32(device, 0x610b80 + soff); 769 soff = 2; 770 } 771 772 switch ((ctrl & 0x000f0000) >> 16) { 773 case 6: datarate = pclk * 30; break; 774 case 5: datarate = pclk * 24; break; 775 case 2: 776 default: 777 datarate = pclk * 18; 778 break; 779 } 780 781 if (nvkm_output_dp_train(outp, datarate / soff)) 782 OUTP_ERR(outp, "link not trained before attach"); 783 } 784 785 exec_clkcmp(disp, head, 0, pclk, &conf); 786 787 if (!outp->info.location && outp->info.type == DCB_OUTPUT_ANALOG) { 788 oreg = 0x614280 + (ffs(outp->info.or) - 1) * 0x800; 789 oval = 0x00000000; 790 hval = 0x00000000; 791 mask = 0xffffffff; 792 } else 793 if (!outp->info.location) { 794 if (outp->info.type == DCB_OUTPUT_DP) 795 nv50_disp_intr_unk20_2_dp(disp, head, &outp->info, pclk); 796 oreg = 0x614300 + (ffs(outp->info.or) - 1) * 0x800; 797 oval = (conf & 0x0100) ? 0x00000101 : 0x00000000; 798 hval = 0x00000000; 799 mask = 0x00000707; 800 } else { 801 oreg = 0x614380 + (ffs(outp->info.or) - 1) * 0x800; 802 oval = 0x00000001; 803 hval = 0x00000001; 804 mask = 0x00000707; 805 } 806 807 nvkm_mask(device, hreg, 0x0000000f, hval); 808 nvkm_mask(device, oreg, mask, oval); 809 810 nv50_disp_dptmds_war_2(disp, &outp->info); 811 } 812 813 /* If programming a TMDS output on a SOR that can also be configured for 814 * DisplayPort, make sure NV50_SOR_DP_CTRL_ENABLE is forced off. 815 * 816 * It looks like the VBIOS TMDS scripts make an attempt at this, however, 817 * the VBIOS scripts on at least one board I have only switch it off on 818 * link 0, causing a blank display if the output has previously been 819 * programmed for DisplayPort. 820 */ 821 static void 822 nv50_disp_intr_unk40_0_tmds(struct nv50_disp *disp, 823 struct dcb_output *outp) 824 { 825 struct nvkm_device *device = disp->base.engine.subdev.device; 826 struct nvkm_bios *bios = device->bios; 827 const int link = !(outp->sorconf.link & 1); 828 const int or = ffs(outp->or) - 1; 829 const u32 loff = (or * 0x800) + (link * 0x80); 830 const u16 mask = (outp->sorconf.link << 6) | outp->or; 831 struct dcb_output match; 832 u8 ver, hdr; 833 834 if (dcb_outp_match(bios, DCB_OUTPUT_DP, mask, &ver, &hdr, &match)) 835 nvkm_mask(device, 0x61c10c + loff, 0x00000001, 0x00000000); 836 } 837 838 static void 839 nv50_disp_intr_unk40_0(struct nv50_disp *disp, int head) 840 { 841 struct nvkm_device *device = disp->base.engine.subdev.device; 842 struct nvkm_output *outp; 843 u32 pclk = nvkm_rd32(device, 0x610ad0 + (head * 0x540)) & 0x3fffff; 844 u32 conf; 845 846 outp = exec_clkcmp(disp, head, 1, pclk, &conf); 847 if (!outp) 848 return; 849 850 if (outp->info.location == 0 && outp->info.type == DCB_OUTPUT_TMDS) 851 nv50_disp_intr_unk40_0_tmds(disp, &outp->info); 852 nv50_disp_dptmds_war_3(disp, &outp->info); 853 } 854 855 void 856 nv50_disp_intr_supervisor(struct work_struct *work) 857 { 858 struct nv50_disp *disp = 859 container_of(work, struct nv50_disp, supervisor); 860 struct nvkm_subdev *subdev = &disp->base.engine.subdev; 861 struct nvkm_device *device = subdev->device; 862 u32 super = nvkm_rd32(device, 0x610030); 863 int head; 864 865 nvkm_debug(subdev, "supervisor %08x %08x\n", disp->super, super); 866 867 if (disp->super & 0x00000010) { 868 nv50_disp_chan_mthd(disp->chan[0], NV_DBG_DEBUG); 869 for (head = 0; head < disp->base.head.nr; head++) { 870 if (!(super & (0x00000020 << head))) 871 continue; 872 if (!(super & (0x00000080 << head))) 873 continue; 874 nv50_disp_intr_unk10_0(disp, head); 875 } 876 } else 877 if (disp->super & 0x00000020) { 878 for (head = 0; head < disp->base.head.nr; head++) { 879 if (!(super & (0x00000080 << head))) 880 continue; 881 nv50_disp_intr_unk20_0(disp, head); 882 } 883 for (head = 0; head < disp->base.head.nr; head++) { 884 if (!(super & (0x00000200 << head))) 885 continue; 886 nv50_disp_intr_unk20_1(disp, head); 887 } 888 for (head = 0; head < disp->base.head.nr; head++) { 889 if (!(super & (0x00000080 << head))) 890 continue; 891 nv50_disp_intr_unk20_2(disp, head); 892 } 893 } else 894 if (disp->super & 0x00000040) { 895 for (head = 0; head < disp->base.head.nr; head++) { 896 if (!(super & (0x00000080 << head))) 897 continue; 898 nv50_disp_intr_unk40_0(disp, head); 899 } 900 nv50_disp_update_sppll1(disp); 901 } 902 903 nvkm_wr32(device, 0x610030, 0x80000000); 904 } 905 906 void 907 nv50_disp_intr(struct nv50_disp *disp) 908 { 909 struct nvkm_device *device = disp->base.engine.subdev.device; 910 u32 intr0 = nvkm_rd32(device, 0x610020); 911 u32 intr1 = nvkm_rd32(device, 0x610024); 912 913 while (intr0 & 0x001f0000) { 914 u32 chid = __ffs(intr0 & 0x001f0000) - 16; 915 nv50_disp_intr_error(disp, chid); 916 intr0 &= ~(0x00010000 << chid); 917 } 918 919 while (intr0 & 0x0000001f) { 920 u32 chid = __ffs(intr0 & 0x0000001f); 921 nv50_disp_chan_uevent_send(disp, chid); 922 intr0 &= ~(0x00000001 << chid); 923 } 924 925 if (intr1 & 0x00000004) { 926 nvkm_disp_vblank(&disp->base, 0); 927 nvkm_wr32(device, 0x610024, 0x00000004); 928 } 929 930 if (intr1 & 0x00000008) { 931 nvkm_disp_vblank(&disp->base, 1); 932 nvkm_wr32(device, 0x610024, 0x00000008); 933 } 934 935 if (intr1 & 0x00000070) { 936 disp->super = (intr1 & 0x00000070); 937 schedule_work(&disp->supervisor); 938 nvkm_wr32(device, 0x610024, disp->super); 939 } 940 } 941 942 static const struct nv50_disp_func 943 nv50_disp = { 944 .intr = nv50_disp_intr, 945 .uevent = &nv50_disp_chan_uevent, 946 .super = nv50_disp_intr_supervisor, 947 .root = &nv50_disp_root_oclass, 948 .head.vblank_init = nv50_disp_vblank_init, 949 .head.vblank_fini = nv50_disp_vblank_fini, 950 .head.scanoutpos = nv50_disp_root_scanoutpos, 951 .outp.internal.crt = nv50_dac_output_new, 952 .outp.internal.tmds = nv50_sor_output_new, 953 .outp.internal.lvds = nv50_sor_output_new, 954 .outp.external.tmds = nv50_pior_output_new, 955 .outp.external.dp = nv50_pior_dp_new, 956 .dac.nr = 3, 957 .dac.power = nv50_dac_power, 958 .dac.sense = nv50_dac_sense, 959 .sor.nr = 2, 960 .sor.power = nv50_sor_power, 961 .pior.nr = 3, 962 .pior.power = nv50_pior_power, 963 }; 964 965 int 966 nv50_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp) 967 { 968 return nv50_disp_new_(&nv50_disp, device, index, 2, pdisp); 969 } 970