xref: /linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.c (revision e5c86679d5e864947a52fb31e45a425dea3e7fa9)
1 /*
2  * Copyright 2016 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs <bskeggs@redhat.com>
23  */
24 #include "nv50.h"
25 #include "rootnv50.h"
26 
27 static void
28 gp102_disp_intr_error(struct nv50_disp *disp, int chid)
29 {
30 	struct nvkm_subdev *subdev = &disp->base.engine.subdev;
31 	struct nvkm_device *device = subdev->device;
32 	u32 mthd = nvkm_rd32(device, 0x6111f0 + (chid * 12));
33 	u32 data = nvkm_rd32(device, 0x6111f4 + (chid * 12));
34 	u32 unkn = nvkm_rd32(device, 0x6111f8 + (chid * 12));
35 
36 	nvkm_error(subdev, "chid %d mthd %04x data %08x %08x %08x\n",
37 		   chid, (mthd & 0x0000ffc), data, mthd, unkn);
38 
39 	if (chid < ARRAY_SIZE(disp->chan)) {
40 		switch (mthd & 0xffc) {
41 		case 0x0080:
42 			nv50_disp_chan_mthd(disp->chan[chid], NV_DBG_ERROR);
43 			break;
44 		default:
45 			break;
46 		}
47 	}
48 
49 	nvkm_wr32(device, 0x61009c, (1 << chid));
50 	nvkm_wr32(device, 0x6111f0 + (chid * 12), 0x90000000);
51 }
52 
53 static const struct nv50_disp_func
54 gp102_disp = {
55 	.intr = gf119_disp_intr,
56 	.intr_error = gp102_disp_intr_error,
57 	.uevent = &gf119_disp_chan_uevent,
58 	.super = gf119_disp_intr_supervisor,
59 	.root = &gp102_disp_root_oclass,
60 	.head.vblank_init = gf119_disp_vblank_init,
61 	.head.vblank_fini = gf119_disp_vblank_fini,
62 	.head.scanoutpos = gf119_disp_root_scanoutpos,
63 	.outp.internal.crt = nv50_dac_output_new,
64 	.outp.internal.tmds = nv50_sor_output_new,
65 	.outp.internal.lvds = nv50_sor_output_new,
66 	.outp.internal.dp = gm200_sor_dp_new,
67 	.dac.nr = 3,
68 	.dac.power = nv50_dac_power,
69 	.dac.sense = nv50_dac_sense,
70 	.sor.nr = 4,
71 	.sor.power = nv50_sor_power,
72 	.sor.hda_eld = gf119_hda_eld,
73 	.sor.hdmi = gk104_hdmi_ctrl,
74 	.sor.magic = gm200_sor_magic,
75 };
76 
77 int
78 gp102_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp)
79 {
80 	return gf119_disp_new_(&gp102_disp, device, index, pdisp);
81 }
82