xref: /linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.c (revision c532de5a67a70f8533d495f8f2aaa9a0491c3ad0)
1 /*
2  * Copyright 2012 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs
23  */
24 #include "priv.h"
25 #include "chan.h"
26 #include "head.h"
27 #include "ior.h"
28 
29 #include <nvif/class.h>
30 
31 static const struct nvkm_disp_func
32 gk110_disp = {
33 	.oneinit = nv50_disp_oneinit,
34 	.init = gf119_disp_init,
35 	.fini = gf119_disp_fini,
36 	.intr = gf119_disp_intr,
37 	.intr_error = gf119_disp_intr_error,
38 	.super = gf119_disp_super,
39 	.uevent = &gf119_disp_chan_uevent,
40 	.head = { .cnt = gf119_head_cnt, .new = gf119_head_new },
41 	.dac = { .cnt = gf119_dac_cnt, .new = gf119_dac_new },
42 	.sor = { .cnt = gf119_sor_cnt, .new = gk104_sor_new },
43 	.root = { 0,0,GK110_DISP },
44 	.user = {
45 		{{0,0,GK104_DISP_CURSOR             }, nvkm_disp_chan_new, &gf119_disp_curs },
46 		{{0,0,GK104_DISP_OVERLAY            }, nvkm_disp_chan_new, &gf119_disp_oimm },
47 		{{0,0,GK110_DISP_BASE_CHANNEL_DMA   }, nvkm_disp_chan_new, &gf119_disp_base },
48 		{{0,0,GK110_DISP_CORE_CHANNEL_DMA   }, nvkm_disp_core_new, &gk104_disp_core },
49 		{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, nvkm_disp_chan_new, &gk104_disp_ovly },
50 		{}
51 	},
52 };
53 
54 int
55 gk110_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
56 	       struct nvkm_disp **pdisp)
57 {
58 	return nvkm_disp_new_(&gk110_disp, device, type, inst, pdisp);
59 }
60