1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "nv50.h" 25 #include "rootnv50.h" 26 27 #include <subdev/bios.h> 28 #include <subdev/bios/disp.h> 29 #include <subdev/bios/init.h> 30 #include <subdev/bios/pll.h> 31 #include <subdev/devinit.h> 32 33 static void 34 gf119_disp_vblank_init(struct nvkm_event *event, int type, int head) 35 { 36 struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank); 37 struct nvkm_device *device = disp->engine.subdev.device; 38 nvkm_mask(device, 0x6100c0 + (head * 0x800), 0x00000001, 0x00000001); 39 } 40 41 static void 42 gf119_disp_vblank_fini(struct nvkm_event *event, int type, int head) 43 { 44 struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank); 45 struct nvkm_device *device = disp->engine.subdev.device; 46 nvkm_mask(device, 0x6100c0 + (head * 0x800), 0x00000001, 0x00000000); 47 } 48 49 const struct nvkm_event_func 50 gf119_disp_vblank_func = { 51 .ctor = nvkm_disp_vblank_ctor, 52 .init = gf119_disp_vblank_init, 53 .fini = gf119_disp_vblank_fini, 54 }; 55 56 static struct nvkm_output * 57 exec_lookup(struct nv50_disp *disp, int head, int or, u32 ctrl, 58 u32 *data, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, 59 struct nvbios_outp *info) 60 { 61 struct nvkm_subdev *subdev = &disp->base.engine.subdev; 62 struct nvkm_bios *bios = subdev->device->bios; 63 struct nvkm_output *outp; 64 u16 mask, type; 65 66 if (or < 4) { 67 type = DCB_OUTPUT_ANALOG; 68 mask = 0; 69 } else { 70 or -= 4; 71 switch (ctrl & 0x00000f00) { 72 case 0x00000000: type = DCB_OUTPUT_LVDS; mask = 1; break; 73 case 0x00000100: type = DCB_OUTPUT_TMDS; mask = 1; break; 74 case 0x00000200: type = DCB_OUTPUT_TMDS; mask = 2; break; 75 case 0x00000500: type = DCB_OUTPUT_TMDS; mask = 3; break; 76 case 0x00000800: type = DCB_OUTPUT_DP; mask = 1; break; 77 case 0x00000900: type = DCB_OUTPUT_DP; mask = 2; break; 78 default: 79 nvkm_error(subdev, "unknown SOR mc %08x\n", ctrl); 80 return NULL; 81 } 82 } 83 84 mask = 0x00c0 & (mask << 6); 85 mask |= 0x0001 << or; 86 mask |= 0x0100 << head; 87 88 list_for_each_entry(outp, &disp->base.outp, head) { 89 if ((outp->info.hasht & 0xff) == type && 90 (outp->info.hashm & mask) == mask) { 91 *data = nvbios_outp_match(bios, outp->info.hasht, 92 outp->info.hashm, 93 ver, hdr, cnt, len, info); 94 if (!*data) 95 return NULL; 96 return outp; 97 } 98 } 99 100 return NULL; 101 } 102 103 static struct nvkm_output * 104 exec_script(struct nv50_disp *disp, int head, int id) 105 { 106 struct nvkm_device *device = disp->base.engine.subdev.device; 107 struct nvkm_bios *bios = device->bios; 108 struct nvkm_output *outp; 109 struct nvbios_outp info; 110 u8 ver, hdr, cnt, len; 111 u32 data, ctrl = 0; 112 int or; 113 114 for (or = 0; !(ctrl & (1 << head)) && or < 8; or++) { 115 ctrl = nvkm_rd32(device, 0x640180 + (or * 0x20)); 116 if (ctrl & (1 << head)) 117 break; 118 } 119 120 if (or == 8) 121 return NULL; 122 123 outp = exec_lookup(disp, head, or, ctrl, &data, &ver, &hdr, &cnt, &len, &info); 124 if (outp) { 125 struct nvbios_init init = { 126 .subdev = nv_subdev(disp), 127 .bios = bios, 128 .offset = info.script[id], 129 .outp = &outp->info, 130 .crtc = head, 131 .execute = 1, 132 }; 133 134 nvbios_exec(&init); 135 } 136 137 return outp; 138 } 139 140 static struct nvkm_output * 141 exec_clkcmp(struct nv50_disp *disp, int head, int id, u32 pclk, u32 *conf) 142 { 143 struct nvkm_device *device = disp->base.engine.subdev.device; 144 struct nvkm_bios *bios = device->bios; 145 struct nvkm_output *outp; 146 struct nvbios_outp info1; 147 struct nvbios_ocfg info2; 148 u8 ver, hdr, cnt, len; 149 u32 data, ctrl = 0; 150 int or; 151 152 for (or = 0; !(ctrl & (1 << head)) && or < 8; or++) { 153 ctrl = nvkm_rd32(device, 0x660180 + (or * 0x20)); 154 if (ctrl & (1 << head)) 155 break; 156 } 157 158 if (or == 8) 159 return NULL; 160 161 outp = exec_lookup(disp, head, or, ctrl, &data, &ver, &hdr, &cnt, &len, &info1); 162 if (!outp) 163 return NULL; 164 165 switch (outp->info.type) { 166 case DCB_OUTPUT_TMDS: 167 *conf = (ctrl & 0x00000f00) >> 8; 168 if (pclk >= 165000) 169 *conf |= 0x0100; 170 break; 171 case DCB_OUTPUT_LVDS: 172 *conf = disp->sor.lvdsconf; 173 break; 174 case DCB_OUTPUT_DP: 175 *conf = (ctrl & 0x00000f00) >> 8; 176 break; 177 case DCB_OUTPUT_ANALOG: 178 default: 179 *conf = 0x00ff; 180 break; 181 } 182 183 data = nvbios_ocfg_match(bios, data, *conf, &ver, &hdr, &cnt, &len, &info2); 184 if (data && id < 0xff) { 185 data = nvbios_oclk_match(bios, info2.clkcmp[id], pclk); 186 if (data) { 187 struct nvbios_init init = { 188 .subdev = nv_subdev(disp), 189 .bios = bios, 190 .offset = data, 191 .outp = &outp->info, 192 .crtc = head, 193 .execute = 1, 194 }; 195 196 nvbios_exec(&init); 197 } 198 } 199 200 return outp; 201 } 202 203 static void 204 gf119_disp_intr_unk1_0(struct nv50_disp *disp, int head) 205 { 206 exec_script(disp, head, 1); 207 } 208 209 static void 210 gf119_disp_intr_unk2_0(struct nv50_disp *disp, int head) 211 { 212 struct nvkm_subdev *subdev = &disp->base.engine.subdev; 213 struct nvkm_output *outp = exec_script(disp, head, 2); 214 215 /* see note in nv50_disp_intr_unk20_0() */ 216 if (outp && outp->info.type == DCB_OUTPUT_DP) { 217 struct nvkm_output_dp *outpdp = nvkm_output_dp(outp); 218 struct nvbios_init init = { 219 .subdev = subdev, 220 .bios = subdev->device->bios, 221 .outp = &outp->info, 222 .crtc = head, 223 .offset = outpdp->info.script[4], 224 .execute = 1, 225 }; 226 227 nvbios_exec(&init); 228 atomic_set(&outpdp->lt.done, 0); 229 } 230 } 231 232 static void 233 gf119_disp_intr_unk2_1(struct nv50_disp *disp, int head) 234 { 235 struct nvkm_device *device = disp->base.engine.subdev.device; 236 struct nvkm_devinit *devinit = device->devinit; 237 u32 pclk = nvkm_rd32(device, 0x660450 + (head * 0x300)) / 1000; 238 if (pclk) 239 nvkm_devinit_pll_set(devinit, PLL_VPLL0 + head, pclk); 240 nvkm_wr32(device, 0x612200 + (head * 0x800), 0x00000000); 241 } 242 243 static void 244 gf119_disp_intr_unk2_2_tu(struct nv50_disp *disp, int head, 245 struct dcb_output *outp) 246 { 247 struct nvkm_device *device = disp->base.engine.subdev.device; 248 const int or = ffs(outp->or) - 1; 249 const u32 ctrl = nvkm_rd32(device, 0x660200 + (or * 0x020)); 250 const u32 conf = nvkm_rd32(device, 0x660404 + (head * 0x300)); 251 const s32 vactive = nvkm_rd32(device, 0x660414 + (head * 0x300)) & 0xffff; 252 const s32 vblanke = nvkm_rd32(device, 0x66041c + (head * 0x300)) & 0xffff; 253 const s32 vblanks = nvkm_rd32(device, 0x660420 + (head * 0x300)) & 0xffff; 254 const u32 pclk = nvkm_rd32(device, 0x660450 + (head * 0x300)) / 1000; 255 const u32 link = ((ctrl & 0xf00) == 0x800) ? 0 : 1; 256 const u32 hoff = (head * 0x800); 257 const u32 soff = ( or * 0x800); 258 const u32 loff = (link * 0x080) + soff; 259 const u32 symbol = 100000; 260 const u32 TU = 64; 261 u32 dpctrl = nvkm_rd32(device, 0x61c10c + loff); 262 u32 clksor = nvkm_rd32(device, 0x612300 + soff); 263 u32 datarate, link_nr, link_bw, bits; 264 u64 ratio, value; 265 266 link_nr = hweight32(dpctrl & 0x000f0000); 267 link_bw = (clksor & 0x007c0000) >> 18; 268 link_bw *= 27000; 269 270 /* symbols/hblank - algorithm taken from comments in tegra driver */ 271 value = vblanke + vactive - vblanks - 7; 272 value = value * link_bw; 273 do_div(value, pclk); 274 value = value - (3 * !!(dpctrl & 0x00004000)) - (12 / link_nr); 275 nvkm_mask(device, 0x616620 + hoff, 0x0000ffff, value); 276 277 /* symbols/vblank - algorithm taken from comments in tegra driver */ 278 value = vblanks - vblanke - 25; 279 value = value * link_bw; 280 do_div(value, pclk); 281 value = value - ((36 / link_nr) + 3) - 1; 282 nvkm_mask(device, 0x616624 + hoff, 0x00ffffff, value); 283 284 /* watermark */ 285 if ((conf & 0x3c0) == 0x180) bits = 30; 286 else if ((conf & 0x3c0) == 0x140) bits = 24; 287 else bits = 18; 288 datarate = (pclk * bits) / 8; 289 290 ratio = datarate; 291 ratio *= symbol; 292 do_div(ratio, link_nr * link_bw); 293 294 value = (symbol - ratio) * TU; 295 value *= ratio; 296 do_div(value, symbol); 297 do_div(value, symbol); 298 299 value += 5; 300 value |= 0x08000000; 301 302 nvkm_wr32(device, 0x616610 + hoff, value); 303 } 304 305 static void 306 gf119_disp_intr_unk2_2(struct nv50_disp *disp, int head) 307 { 308 struct nvkm_device *device = disp->base.engine.subdev.device; 309 struct nvkm_output *outp; 310 u32 pclk = nvkm_rd32(device, 0x660450 + (head * 0x300)) / 1000; 311 u32 conf, addr, data; 312 313 outp = exec_clkcmp(disp, head, 0xff, pclk, &conf); 314 if (!outp) 315 return; 316 317 /* see note in nv50_disp_intr_unk20_2() */ 318 if (outp->info.type == DCB_OUTPUT_DP) { 319 u32 sync = nvkm_rd32(device, 0x660404 + (head * 0x300)); 320 switch ((sync & 0x000003c0) >> 6) { 321 case 6: pclk = pclk * 30; break; 322 case 5: pclk = pclk * 24; break; 323 case 2: 324 default: 325 pclk = pclk * 18; 326 break; 327 } 328 329 if (nvkm_output_dp_train(outp, pclk, true)) 330 OUTP_ERR(outp, "link not trained before attach"); 331 } else { 332 if (disp->sor.magic) 333 disp->sor.magic(outp); 334 } 335 336 exec_clkcmp(disp, head, 0, pclk, &conf); 337 338 if (outp->info.type == DCB_OUTPUT_ANALOG) { 339 addr = 0x612280 + (ffs(outp->info.or) - 1) * 0x800; 340 data = 0x00000000; 341 } else { 342 addr = 0x612300 + (ffs(outp->info.or) - 1) * 0x800; 343 data = (conf & 0x0100) ? 0x00000101 : 0x00000000; 344 switch (outp->info.type) { 345 case DCB_OUTPUT_TMDS: 346 nvkm_mask(device, addr, 0x007c0000, 0x00280000); 347 break; 348 case DCB_OUTPUT_DP: 349 gf119_disp_intr_unk2_2_tu(disp, head, &outp->info); 350 break; 351 default: 352 break; 353 } 354 } 355 356 nvkm_mask(device, addr, 0x00000707, data); 357 } 358 359 static void 360 gf119_disp_intr_unk4_0(struct nv50_disp *disp, int head) 361 { 362 struct nvkm_device *device = disp->base.engine.subdev.device; 363 u32 pclk = nvkm_rd32(device, 0x660450 + (head * 0x300)) / 1000; 364 u32 conf; 365 366 exec_clkcmp(disp, head, 1, pclk, &conf); 367 } 368 369 void 370 gf119_disp_intr_supervisor(struct work_struct *work) 371 { 372 struct nv50_disp *disp = 373 container_of(work, struct nv50_disp, supervisor); 374 struct nvkm_subdev *subdev = &disp->base.engine.subdev; 375 struct nvkm_device *device = subdev->device; 376 u32 mask[4]; 377 int head; 378 379 nvkm_debug(subdev, "supervisor %d\n", ffs(disp->super)); 380 for (head = 0; head < disp->head.nr; head++) { 381 mask[head] = nvkm_rd32(device, 0x6101d4 + (head * 0x800)); 382 nvkm_debug(subdev, "head %d: %08x\n", head, mask[head]); 383 } 384 385 if (disp->super & 0x00000001) { 386 nv50_disp_chan_mthd(disp->chan[0], NV_DBG_DEBUG); 387 for (head = 0; head < disp->head.nr; head++) { 388 if (!(mask[head] & 0x00001000)) 389 continue; 390 nvkm_debug(subdev, "supervisor 1.0 - head %d\n", head); 391 gf119_disp_intr_unk1_0(disp, head); 392 } 393 } else 394 if (disp->super & 0x00000002) { 395 for (head = 0; head < disp->head.nr; head++) { 396 if (!(mask[head] & 0x00001000)) 397 continue; 398 nvkm_debug(subdev, "supervisor 2.0 - head %d\n", head); 399 gf119_disp_intr_unk2_0(disp, head); 400 } 401 for (head = 0; head < disp->head.nr; head++) { 402 if (!(mask[head] & 0x00010000)) 403 continue; 404 nvkm_debug(subdev, "supervisor 2.1 - head %d\n", head); 405 gf119_disp_intr_unk2_1(disp, head); 406 } 407 for (head = 0; head < disp->head.nr; head++) { 408 if (!(mask[head] & 0x00001000)) 409 continue; 410 nvkm_debug(subdev, "supervisor 2.2 - head %d\n", head); 411 gf119_disp_intr_unk2_2(disp, head); 412 } 413 } else 414 if (disp->super & 0x00000004) { 415 for (head = 0; head < disp->head.nr; head++) { 416 if (!(mask[head] & 0x00001000)) 417 continue; 418 nvkm_debug(subdev, "supervisor 3.0 - head %d\n", head); 419 gf119_disp_intr_unk4_0(disp, head); 420 } 421 } 422 423 for (head = 0; head < disp->head.nr; head++) 424 nvkm_wr32(device, 0x6101d4 + (head * 0x800), 0x00000000); 425 nvkm_wr32(device, 0x6101d0, 0x80000000); 426 } 427 428 static void 429 gf119_disp_intr_error(struct nv50_disp *disp, int chid) 430 { 431 struct nvkm_subdev *subdev = &disp->base.engine.subdev; 432 struct nvkm_device *device = subdev->device; 433 u32 mthd = nvkm_rd32(device, 0x6101f0 + (chid * 12)); 434 u32 data = nvkm_rd32(device, 0x6101f4 + (chid * 12)); 435 u32 unkn = nvkm_rd32(device, 0x6101f8 + (chid * 12)); 436 437 nvkm_error(subdev, "chid %d mthd %04x data %08x %08x %08x\n", 438 chid, (mthd & 0x0000ffc), data, mthd, unkn); 439 440 if (chid < ARRAY_SIZE(disp->chan)) { 441 switch (mthd & 0xffc) { 442 case 0x0080: 443 nv50_disp_chan_mthd(disp->chan[chid], NV_DBG_ERROR); 444 break; 445 default: 446 break; 447 } 448 } 449 450 nvkm_wr32(device, 0x61009c, (1 << chid)); 451 nvkm_wr32(device, 0x6101f0 + (chid * 12), 0x90000000); 452 } 453 454 void 455 gf119_disp_intr(struct nvkm_subdev *subdev) 456 { 457 struct nv50_disp *disp = (void *)subdev; 458 struct nvkm_device *device = subdev->device; 459 u32 intr = nvkm_rd32(device, 0x610088); 460 int i; 461 462 if (intr & 0x00000001) { 463 u32 stat = nvkm_rd32(device, 0x61008c); 464 while (stat) { 465 int chid = __ffs(stat); stat &= ~(1 << chid); 466 nv50_disp_chan_uevent_send(disp, chid); 467 nvkm_wr32(device, 0x61008c, 1 << chid); 468 } 469 intr &= ~0x00000001; 470 } 471 472 if (intr & 0x00000002) { 473 u32 stat = nvkm_rd32(device, 0x61009c); 474 int chid = ffs(stat) - 1; 475 if (chid >= 0) 476 gf119_disp_intr_error(disp, chid); 477 intr &= ~0x00000002; 478 } 479 480 if (intr & 0x00100000) { 481 u32 stat = nvkm_rd32(device, 0x6100ac); 482 if (stat & 0x00000007) { 483 disp->super = (stat & 0x00000007); 484 schedule_work(&disp->supervisor); 485 nvkm_wr32(device, 0x6100ac, disp->super); 486 stat &= ~0x00000007; 487 } 488 489 if (stat) { 490 nvkm_warn(subdev, "intr24 %08x\n", stat); 491 nvkm_wr32(device, 0x6100ac, stat); 492 } 493 494 intr &= ~0x00100000; 495 } 496 497 for (i = 0; i < disp->head.nr; i++) { 498 u32 mask = 0x01000000 << i; 499 if (mask & intr) { 500 u32 stat = nvkm_rd32(device, 0x6100bc + (i * 0x800)); 501 if (stat & 0x00000001) 502 nvkm_disp_vblank(&disp->base, i); 503 nvkm_mask(device, 0x6100bc + (i * 0x800), 0, 0); 504 nvkm_rd32(device, 0x6100c0 + (i * 0x800)); 505 } 506 } 507 } 508 509 static const struct nvkm_disp_func 510 gf119_disp = { 511 .root = &gf119_disp_root_oclass, 512 }; 513 514 static int 515 gf119_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 516 struct nvkm_oclass *oclass, void *data, u32 size, 517 struct nvkm_object **pobject) 518 { 519 struct nvkm_device *device = (void *)parent; 520 struct nv50_disp *disp; 521 int heads = nvkm_rd32(device, 0x022448); 522 int ret; 523 524 ret = nvkm_disp_create(parent, engine, oclass, heads, 525 "PDISP", "display", &disp); 526 *pobject = nv_object(disp); 527 if (ret) 528 return ret; 529 530 disp->base.func = &gf119_disp; 531 532 ret = nvkm_event_init(&gf119_disp_chan_uevent, 1, 17, &disp->uevent); 533 if (ret) 534 return ret; 535 536 nv_subdev(disp)->intr = gf119_disp_intr; 537 INIT_WORK(&disp->supervisor, gf119_disp_intr_supervisor); 538 disp->head.nr = heads; 539 disp->dac.nr = 3; 540 disp->sor.nr = 4; 541 disp->dac.power = nv50_dac_power; 542 disp->dac.sense = nv50_dac_sense; 543 disp->sor.power = nv50_sor_power; 544 disp->sor.hda_eld = gf119_hda_eld; 545 disp->sor.hdmi = gf119_hdmi_ctrl; 546 return 0; 547 } 548 549 struct nvkm_oclass * 550 gf110_disp_oclass = &(struct nv50_disp_impl) { 551 .base.base.handle = NV_ENGINE(DISP, 0x90), 552 .base.base.ofuncs = &(struct nvkm_ofuncs) { 553 .ctor = gf119_disp_ctor, 554 .dtor = _nvkm_disp_dtor, 555 .init = _nvkm_disp_init, 556 .fini = _nvkm_disp_fini, 557 }, 558 .base.outp.internal.crt = nv50_dac_output_new, 559 .base.outp.internal.tmds = nv50_sor_output_new, 560 .base.outp.internal.lvds = nv50_sor_output_new, 561 .base.outp.internal.dp = gf119_sor_dp_new, 562 .base.vblank = &gf119_disp_vblank_func, 563 .head.scanoutpos = gf119_disp_root_scanoutpos, 564 }.base.base; 565