1 /* 2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20 * DEALINGS IN THE SOFTWARE. 21 */ 22 #include <core/tegra.h> 23 #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER 24 #include "priv.h" 25 26 #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU) 27 #include <asm/dma-iommu.h> 28 #endif 29 30 static int 31 nvkm_device_tegra_power_up(struct nvkm_device_tegra *tdev) 32 { 33 int ret; 34 35 if (tdev->vdd) { 36 ret = regulator_enable(tdev->vdd); 37 if (ret) 38 goto err_power; 39 } 40 41 ret = clk_prepare_enable(tdev->clk); 42 if (ret) 43 goto err_clk; 44 ret = clk_prepare_enable(tdev->clk_ref); 45 if (ret) 46 goto err_clk_ref; 47 ret = clk_prepare_enable(tdev->clk_pwr); 48 if (ret) 49 goto err_clk_pwr; 50 clk_set_rate(tdev->clk_pwr, 204000000); 51 udelay(10); 52 53 if (!tdev->pdev->dev.pm_domain) { 54 reset_control_assert(tdev->rst); 55 udelay(10); 56 57 ret = tegra_powergate_remove_clamping(TEGRA_POWERGATE_3D); 58 if (ret) 59 goto err_clamp; 60 udelay(10); 61 62 reset_control_deassert(tdev->rst); 63 udelay(10); 64 } 65 66 return 0; 67 68 err_clamp: 69 clk_disable_unprepare(tdev->clk_pwr); 70 err_clk_pwr: 71 clk_disable_unprepare(tdev->clk_ref); 72 err_clk_ref: 73 clk_disable_unprepare(tdev->clk); 74 err_clk: 75 if (tdev->vdd) 76 regulator_disable(tdev->vdd); 77 err_power: 78 return ret; 79 } 80 81 static int 82 nvkm_device_tegra_power_down(struct nvkm_device_tegra *tdev) 83 { 84 int ret; 85 86 clk_disable_unprepare(tdev->clk_pwr); 87 clk_disable_unprepare(tdev->clk_ref); 88 clk_disable_unprepare(tdev->clk); 89 udelay(10); 90 91 if (tdev->vdd) { 92 ret = regulator_disable(tdev->vdd); 93 if (ret) 94 return ret; 95 } 96 97 return 0; 98 } 99 100 static void 101 nvkm_device_tegra_probe_iommu(struct nvkm_device_tegra *tdev) 102 { 103 #if IS_ENABLED(CONFIG_IOMMU_API) 104 struct device *dev = &tdev->pdev->dev; 105 unsigned long pgsize_bitmap; 106 int ret; 107 108 #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU) 109 if (dev->archdata.mapping) { 110 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); 111 112 arm_iommu_detach_device(dev); 113 arm_iommu_release_mapping(mapping); 114 } 115 #endif 116 117 if (!tdev->func->iommu_bit) 118 return; 119 120 mutex_init(&tdev->iommu.mutex); 121 122 if (device_iommu_mapped(dev)) { 123 tdev->iommu.domain = iommu_paging_domain_alloc(dev); 124 if (IS_ERR(tdev->iommu.domain)) 125 goto error; 126 127 /* 128 * A IOMMU is only usable if it supports page sizes smaller 129 * or equal to the system's PAGE_SIZE, with a preference if 130 * both are equal. 131 */ 132 pgsize_bitmap = tdev->iommu.domain->pgsize_bitmap; 133 if (pgsize_bitmap & PAGE_SIZE) { 134 tdev->iommu.pgshift = PAGE_SHIFT; 135 } else { 136 tdev->iommu.pgshift = fls(pgsize_bitmap & ~PAGE_MASK); 137 if (tdev->iommu.pgshift == 0) { 138 dev_warn(dev, "unsupported IOMMU page size\n"); 139 goto free_domain; 140 } 141 tdev->iommu.pgshift -= 1; 142 } 143 144 ret = iommu_attach_device(tdev->iommu.domain, dev); 145 if (ret) 146 goto free_domain; 147 148 ret = nvkm_mm_init(&tdev->iommu.mm, 0, 0, 149 (1ULL << tdev->func->iommu_bit) >> 150 tdev->iommu.pgshift, 1); 151 if (ret) 152 goto detach_device; 153 } 154 155 return; 156 157 detach_device: 158 iommu_detach_device(tdev->iommu.domain, dev); 159 160 free_domain: 161 iommu_domain_free(tdev->iommu.domain); 162 163 error: 164 tdev->iommu.domain = NULL; 165 tdev->iommu.pgshift = 0; 166 dev_err(dev, "cannot initialize IOMMU MM\n"); 167 #endif 168 } 169 170 static void 171 nvkm_device_tegra_remove_iommu(struct nvkm_device_tegra *tdev) 172 { 173 #if IS_ENABLED(CONFIG_IOMMU_API) 174 if (tdev->iommu.domain) { 175 nvkm_mm_fini(&tdev->iommu.mm); 176 iommu_detach_device(tdev->iommu.domain, tdev->device.dev); 177 iommu_domain_free(tdev->iommu.domain); 178 } 179 #endif 180 } 181 182 static struct nvkm_device_tegra * 183 nvkm_device_tegra(struct nvkm_device *device) 184 { 185 return container_of(device, struct nvkm_device_tegra, device); 186 } 187 188 static struct resource * 189 nvkm_device_tegra_resource(struct nvkm_device *device, enum nvkm_bar_id bar) 190 { 191 struct nvkm_device_tegra *tdev = nvkm_device_tegra(device); 192 int idx; 193 194 switch (bar) { 195 case NVKM_BAR0_PRI: idx = 0; break; 196 case NVKM_BAR1_FB : idx = 1; break; 197 default: 198 WARN_ON(1); 199 return NULL; 200 } 201 202 return platform_get_resource(tdev->pdev, IORESOURCE_MEM, idx); 203 } 204 205 static resource_size_t 206 nvkm_device_tegra_resource_addr(struct nvkm_device *device, enum nvkm_bar_id bar) 207 { 208 struct resource *res = nvkm_device_tegra_resource(device, bar); 209 return res ? res->start : 0; 210 } 211 212 static resource_size_t 213 nvkm_device_tegra_resource_size(struct nvkm_device *device, enum nvkm_bar_id bar) 214 { 215 struct resource *res = nvkm_device_tegra_resource(device, bar); 216 return res ? resource_size(res) : 0; 217 } 218 219 static int 220 nvkm_device_tegra_irq(struct nvkm_device *device) 221 { 222 struct nvkm_device_tegra *tdev = nvkm_device_tegra(device); 223 224 return platform_get_irq_byname(tdev->pdev, "stall"); 225 } 226 227 static void * 228 nvkm_device_tegra_dtor(struct nvkm_device *device) 229 { 230 struct nvkm_device_tegra *tdev = nvkm_device_tegra(device); 231 nvkm_device_tegra_power_down(tdev); 232 nvkm_device_tegra_remove_iommu(tdev); 233 return tdev; 234 } 235 236 static const struct nvkm_device_func 237 nvkm_device_tegra_func = { 238 .tegra = nvkm_device_tegra, 239 .dtor = nvkm_device_tegra_dtor, 240 .irq = nvkm_device_tegra_irq, 241 .resource_addr = nvkm_device_tegra_resource_addr, 242 .resource_size = nvkm_device_tegra_resource_size, 243 .cpu_coherent = false, 244 }; 245 246 int 247 nvkm_device_tegra_new(const struct nvkm_device_tegra_func *func, 248 struct platform_device *pdev, 249 const char *cfg, const char *dbg, 250 struct nvkm_device **pdevice) 251 { 252 struct nvkm_device_tegra *tdev; 253 unsigned long rate; 254 int ret; 255 256 if (!(tdev = kzalloc(sizeof(*tdev), GFP_KERNEL))) 257 return -ENOMEM; 258 259 tdev->func = func; 260 tdev->pdev = pdev; 261 262 if (func->require_vdd) { 263 tdev->vdd = devm_regulator_get(&pdev->dev, "vdd"); 264 if (IS_ERR(tdev->vdd)) { 265 ret = PTR_ERR(tdev->vdd); 266 goto free; 267 } 268 } 269 270 tdev->rst = devm_reset_control_get(&pdev->dev, "gpu"); 271 if (IS_ERR(tdev->rst)) { 272 ret = PTR_ERR(tdev->rst); 273 goto free; 274 } 275 276 tdev->clk = devm_clk_get(&pdev->dev, "gpu"); 277 if (IS_ERR(tdev->clk)) { 278 ret = PTR_ERR(tdev->clk); 279 goto free; 280 } 281 282 rate = clk_get_rate(tdev->clk); 283 if (rate == 0) { 284 ret = clk_set_rate(tdev->clk, ULONG_MAX); 285 if (ret < 0) 286 goto free; 287 288 rate = clk_get_rate(tdev->clk); 289 290 dev_dbg(&pdev->dev, "GPU clock set to %lu\n", rate); 291 } 292 293 if (func->require_ref_clk) 294 tdev->clk_ref = devm_clk_get(&pdev->dev, "ref"); 295 if (IS_ERR(tdev->clk_ref)) { 296 ret = PTR_ERR(tdev->clk_ref); 297 goto free; 298 } 299 300 tdev->clk_pwr = devm_clk_get(&pdev->dev, "pwr"); 301 if (IS_ERR(tdev->clk_pwr)) { 302 ret = PTR_ERR(tdev->clk_pwr); 303 goto free; 304 } 305 306 /** 307 * The IOMMU bit defines the upper limit of the GPU-addressable space. 308 */ 309 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(tdev->func->iommu_bit)); 310 if (ret) 311 goto free; 312 313 nvkm_device_tegra_probe_iommu(tdev); 314 315 ret = nvkm_device_tegra_power_up(tdev); 316 if (ret) 317 goto remove; 318 319 tdev->gpu_speedo = tegra_sku_info.gpu_speedo_value; 320 tdev->gpu_speedo_id = tegra_sku_info.gpu_speedo_id; 321 ret = nvkm_device_ctor(&nvkm_device_tegra_func, NULL, &pdev->dev, 322 NVKM_DEVICE_TEGRA, pdev->id, NULL, 323 cfg, dbg, &tdev->device); 324 if (ret) 325 goto powerdown; 326 327 *pdevice = &tdev->device; 328 329 return 0; 330 331 powerdown: 332 nvkm_device_tegra_power_down(tdev); 333 remove: 334 nvkm_device_tegra_remove_iommu(tdev); 335 free: 336 kfree(tdev); 337 return ret; 338 } 339 #else 340 int 341 nvkm_device_tegra_new(const struct nvkm_device_tegra_func *func, 342 struct platform_device *pdev, 343 const char *cfg, const char *dbg, 344 struct nvkm_device **pdevice) 345 { 346 return -ENOSYS; 347 } 348 #endif 349