xref: /linux/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c (revision ca55b2fef3a9373fcfc30f82fd26bc7fccbda732)
1 /*
2  * Copyright 2013 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs <bskeggs@redhat.com>
23  */
24 #include "ctrl.h"
25 
26 #include <core/client.h>
27 #include <subdev/clk.h>
28 
29 #include <nvif/class.h>
30 #include <nvif/ioctl.h>
31 #include <nvif/unpack.h>
32 
33 static int
34 nvkm_control_mthd_pstate_info(struct nvkm_control *ctrl, void *data, u32 size)
35 {
36 	union {
37 		struct nvif_control_pstate_info_v0 v0;
38 	} *args = data;
39 	struct nvkm_clk *clk = ctrl->device->clk;
40 	int ret;
41 
42 	nvif_ioctl(&ctrl->object, "control pstate info size %d\n", size);
43 	if (nvif_unpack(args->v0, 0, 0, false)) {
44 		nvif_ioctl(&ctrl->object, "control pstate info vers %d\n",
45 			   args->v0.version);
46 	} else
47 		return ret;
48 
49 	if (clk) {
50 		args->v0.count = clk->state_nr;
51 		args->v0.ustate_ac = clk->ustate_ac;
52 		args->v0.ustate_dc = clk->ustate_dc;
53 		args->v0.pwrsrc = clk->pwrsrc;
54 		args->v0.pstate = clk->pstate;
55 	} else {
56 		args->v0.count = 0;
57 		args->v0.ustate_ac = NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE;
58 		args->v0.ustate_dc = NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE;
59 		args->v0.pwrsrc = -ENOSYS;
60 		args->v0.pstate = NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_UNKNOWN;
61 	}
62 
63 	return 0;
64 }
65 
66 static int
67 nvkm_control_mthd_pstate_attr(struct nvkm_control *ctrl, void *data, u32 size)
68 {
69 	union {
70 		struct nvif_control_pstate_attr_v0 v0;
71 	} *args = data;
72 	struct nvkm_clk *clk = ctrl->device->clk;
73 	const struct nvkm_domain *domain;
74 	struct nvkm_pstate *pstate;
75 	struct nvkm_cstate *cstate;
76 	int i = 0, j = -1;
77 	u32 lo, hi;
78 	int ret;
79 
80 	nvif_ioctl(&ctrl->object, "control pstate attr size %d\n", size);
81 	if (nvif_unpack(args->v0, 0, 0, false)) {
82 		nvif_ioctl(&ctrl->object,
83 			   "control pstate attr vers %d state %d index %d\n",
84 			   args->v0.version, args->v0.state, args->v0.index);
85 		if (!clk)
86 			return -ENODEV;
87 		if (args->v0.state < NVIF_CONTROL_PSTATE_ATTR_V0_STATE_CURRENT)
88 			return -EINVAL;
89 		if (args->v0.state >= clk->state_nr)
90 			return -EINVAL;
91 	} else
92 		return ret;
93 	domain = clk->domains;
94 
95 	while (domain->name != nv_clk_src_max) {
96 		if (domain->mname && ++j == args->v0.index)
97 			break;
98 		domain++;
99 	}
100 
101 	if (domain->name == nv_clk_src_max)
102 		return -EINVAL;
103 
104 	if (args->v0.state != NVIF_CONTROL_PSTATE_ATTR_V0_STATE_CURRENT) {
105 		list_for_each_entry(pstate, &clk->states, head) {
106 			if (i++ == args->v0.state)
107 				break;
108 		}
109 
110 		lo = pstate->base.domain[domain->name];
111 		hi = lo;
112 		list_for_each_entry(cstate, &pstate->list, head) {
113 			lo = min(lo, cstate->domain[domain->name]);
114 			hi = max(hi, cstate->domain[domain->name]);
115 		}
116 
117 		args->v0.state = pstate->pstate;
118 	} else {
119 		lo = max(nvkm_clk_read(clk, domain->name), 0);
120 		hi = lo;
121 	}
122 
123 	snprintf(args->v0.name, sizeof(args->v0.name), "%s", domain->mname);
124 	snprintf(args->v0.unit, sizeof(args->v0.unit), "MHz");
125 	args->v0.min = lo / domain->mdiv;
126 	args->v0.max = hi / domain->mdiv;
127 
128 	args->v0.index = 0;
129 	while ((++domain)->name != nv_clk_src_max) {
130 		if (domain->mname) {
131 			args->v0.index = ++j;
132 			break;
133 		}
134 	}
135 
136 	return 0;
137 }
138 
139 static int
140 nvkm_control_mthd_pstate_user(struct nvkm_control *ctrl, void *data, u32 size)
141 {
142 	union {
143 		struct nvif_control_pstate_user_v0 v0;
144 	} *args = data;
145 	struct nvkm_clk *clk = ctrl->device->clk;
146 	int ret;
147 
148 	nvif_ioctl(&ctrl->object, "control pstate user size %d\n", size);
149 	if (nvif_unpack(args->v0, 0, 0, false)) {
150 		nvif_ioctl(&ctrl->object,
151 			   "control pstate user vers %d ustate %d pwrsrc %d\n",
152 			   args->v0.version, args->v0.ustate, args->v0.pwrsrc);
153 		if (!clk)
154 			return -ENODEV;
155 	} else
156 		return ret;
157 
158 	if (args->v0.pwrsrc >= 0) {
159 		ret |= nvkm_clk_ustate(clk, args->v0.ustate, args->v0.pwrsrc);
160 	} else {
161 		ret |= nvkm_clk_ustate(clk, args->v0.ustate, 0);
162 		ret |= nvkm_clk_ustate(clk, args->v0.ustate, 1);
163 	}
164 
165 	return ret;
166 }
167 
168 static int
169 nvkm_control_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size)
170 {
171 	struct nvkm_control *ctrl = nvkm_control(object);
172 	switch (mthd) {
173 	case NVIF_CONTROL_PSTATE_INFO:
174 		return nvkm_control_mthd_pstate_info(ctrl, data, size);
175 	case NVIF_CONTROL_PSTATE_ATTR:
176 		return nvkm_control_mthd_pstate_attr(ctrl, data, size);
177 	case NVIF_CONTROL_PSTATE_USER:
178 		return nvkm_control_mthd_pstate_user(ctrl, data, size);
179 	default:
180 		break;
181 	}
182 	return -EINVAL;
183 }
184 
185 static const struct nvkm_object_func
186 nvkm_control = {
187 	.mthd = nvkm_control_mthd,
188 };
189 
190 static int
191 nvkm_control_new(struct nvkm_device *device, const struct nvkm_oclass *oclass,
192 		 void *data, u32 size, struct nvkm_object **pobject)
193 {
194 	struct nvkm_control *ctrl;
195 
196 	if (!(ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL)))
197 		return -ENOMEM;
198 	*pobject = &ctrl->object;
199 	ctrl->device = device;
200 
201 	nvkm_object_ctor(&nvkm_control, oclass, &ctrl->object);
202 	return 0;
203 }
204 
205 const struct nvkm_device_oclass
206 nvkm_control_oclass = {
207 	.base.oclass = NVIF_IOCTL_NEW_V0_CONTROL,
208 	.base.minver = -1,
209 	.base.maxver = -1,
210 	.ctor = nvkm_control_new,
211 };
212