1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include <engine/ce.h> 25 #include <engine/falcon.h> 26 #include <engine/fifo.h> 27 #include "fuc/gt215.fuc3.h" 28 29 #include <core/client.h> 30 #include <core/device.h> 31 #include <core/enum.h> 32 33 struct gt215_ce_priv { 34 struct nvkm_falcon base; 35 }; 36 37 /******************************************************************************* 38 * Copy object classes 39 ******************************************************************************/ 40 41 static struct nvkm_oclass 42 gt215_ce_sclass[] = { 43 { 0x85b5, &nvkm_object_ofuncs }, 44 {} 45 }; 46 47 /******************************************************************************* 48 * PCE context 49 ******************************************************************************/ 50 51 static struct nvkm_oclass 52 gt215_ce_cclass = { 53 .handle = NV_ENGCTX(CE0, 0xa3), 54 .ofuncs = &(struct nvkm_ofuncs) { 55 .ctor = _nvkm_falcon_context_ctor, 56 .dtor = _nvkm_falcon_context_dtor, 57 .init = _nvkm_falcon_context_init, 58 .fini = _nvkm_falcon_context_fini, 59 .rd32 = _nvkm_falcon_context_rd32, 60 .wr32 = _nvkm_falcon_context_wr32, 61 62 }, 63 }; 64 65 /******************************************************************************* 66 * PCE engine/subdev functions 67 ******************************************************************************/ 68 69 static const struct nvkm_enum 70 gt215_ce_isr_error_name[] = { 71 { 0x0001, "ILLEGAL_MTHD" }, 72 { 0x0002, "INVALID_ENUM" }, 73 { 0x0003, "INVALID_BITFIELD" }, 74 {} 75 }; 76 77 void 78 gt215_ce_intr(struct nvkm_subdev *subdev) 79 { 80 struct nvkm_fifo *pfifo = nvkm_fifo(subdev); 81 struct nvkm_engine *engine = nv_engine(subdev); 82 struct nvkm_falcon *falcon = (void *)subdev; 83 struct nvkm_object *engctx; 84 u32 dispatch = nv_ro32(falcon, 0x01c); 85 u32 stat = nv_ro32(falcon, 0x008) & dispatch & ~(dispatch >> 16); 86 u64 inst = nv_ro32(falcon, 0x050) & 0x3fffffff; 87 u32 ssta = nv_ro32(falcon, 0x040) & 0x0000ffff; 88 u32 addr = nv_ro32(falcon, 0x040) >> 16; 89 u32 mthd = (addr & 0x07ff) << 2; 90 u32 subc = (addr & 0x3800) >> 11; 91 u32 data = nv_ro32(falcon, 0x044); 92 int chid; 93 94 engctx = nvkm_engctx_get(engine, inst); 95 chid = pfifo->chid(pfifo, engctx); 96 97 if (stat & 0x00000040) { 98 nv_error(falcon, "DISPATCH_ERROR ["); 99 nvkm_enum_print(gt215_ce_isr_error_name, ssta); 100 pr_cont("] ch %d [0x%010llx %s] subc %d mthd 0x%04x data 0x%08x\n", 101 chid, inst << 12, nvkm_client_name(engctx), subc, 102 mthd, data); 103 nv_wo32(falcon, 0x004, 0x00000040); 104 stat &= ~0x00000040; 105 } 106 107 if (stat) { 108 nv_error(falcon, "unhandled intr 0x%08x\n", stat); 109 nv_wo32(falcon, 0x004, stat); 110 } 111 112 nvkm_engctx_put(engctx); 113 } 114 115 static int 116 gt215_ce_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 117 struct nvkm_oclass *oclass, void *data, u32 size, 118 struct nvkm_object **pobject) 119 { 120 bool enable = (nv_device(parent)->chipset != 0xaf); 121 struct gt215_ce_priv *priv; 122 int ret; 123 124 ret = nvkm_falcon_create(parent, engine, oclass, 0x104000, enable, 125 "PCE0", "ce0", &priv); 126 *pobject = nv_object(priv); 127 if (ret) 128 return ret; 129 130 nv_subdev(priv)->unit = 0x00802000; 131 nv_subdev(priv)->intr = gt215_ce_intr; 132 nv_engine(priv)->cclass = >215_ce_cclass; 133 nv_engine(priv)->sclass = gt215_ce_sclass; 134 nv_falcon(priv)->code.data = gt215_pce_code; 135 nv_falcon(priv)->code.size = sizeof(gt215_pce_code); 136 nv_falcon(priv)->data.data = gt215_pce_data; 137 nv_falcon(priv)->data.size = sizeof(gt215_pce_data); 138 return 0; 139 } 140 141 struct nvkm_oclass 142 gt215_ce_oclass = { 143 .handle = NV_ENGINE(CE0, 0xa3), 144 .ofuncs = &(struct nvkm_ofuncs) { 145 .ctor = gt215_ce_ctor, 146 .dtor = _nvkm_falcon_dtor, 147 .init = _nvkm_falcon_init, 148 .fini = _nvkm_falcon_fini, 149 .rd32 = _nvkm_falcon_rd32, 150 .wr32 = _nvkm_falcon_wr32, 151 }, 152 }; 153