1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 25 #include <linux/aperture.h> 26 #include <linux/delay.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/vga_switcheroo.h> 31 #include <linux/mmu_notifier.h> 32 #include <linux/dynamic_debug.h> 33 #include <linux/debugfs.h> 34 35 #include <drm/clients/drm_client_setup.h> 36 #include <drm/drm_drv.h> 37 #include <drm/drm_fbdev_ttm.h> 38 #include <drm/drm_gem_ttm_helper.h> 39 #include <drm/drm_ioctl.h> 40 #include <drm/drm_vblank.h> 41 42 #include <core/gpuobj.h> 43 #include <core/option.h> 44 #include <core/pci.h> 45 #include <core/tegra.h> 46 47 #include <nvif/driver.h> 48 #include <nvif/fifo.h> 49 #include <nvif/push006c.h> 50 #include <nvif/user.h> 51 #include <nvif/log.h> 52 53 #include <nvif/class.h> 54 #include <nvif/cl0002.h> 55 56 #include "nouveau_drv.h" 57 #include "nouveau_dma.h" 58 #include "nouveau_ttm.h" 59 #include "nouveau_gem.h" 60 #include "nouveau_vga.h" 61 #include "nouveau_led.h" 62 #include "nouveau_hwmon.h" 63 #include "nouveau_acpi.h" 64 #include "nouveau_bios.h" 65 #include "nouveau_ioctl.h" 66 #include "nouveau_abi16.h" 67 #include "nouveau_fence.h" 68 #include "nouveau_debugfs.h" 69 #include "nouveau_connector.h" 70 #include "nouveau_platform.h" 71 #include "nouveau_svm.h" 72 #include "nouveau_dmem.h" 73 #include "nouveau_exec.h" 74 #include "nouveau_uvmm.h" 75 #include "nouveau_sched.h" 76 77 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 78 "DRM_UT_CORE", 79 "DRM_UT_DRIVER", 80 "DRM_UT_KMS", 81 "DRM_UT_PRIME", 82 "DRM_UT_ATOMIC", 83 "DRM_UT_VBL", 84 "DRM_UT_STATE", 85 "DRM_UT_LEASE", 86 "DRM_UT_DP", 87 "DRM_UT_DRMRES"); 88 89 MODULE_PARM_DESC(config, "option string to pass to driver core"); 90 static char *nouveau_config; 91 module_param_named(config, nouveau_config, charp, 0400); 92 93 MODULE_PARM_DESC(debug, "debug string to pass to driver core"); 94 static char *nouveau_debug; 95 module_param_named(debug, nouveau_debug, charp, 0400); 96 97 MODULE_PARM_DESC(noaccel, "disable kernel/abi16 acceleration"); 98 static int nouveau_noaccel = 0; 99 module_param_named(noaccel, nouveau_noaccel, int, 0400); 100 101 MODULE_PARM_DESC(modeset, "enable driver (default: auto, " 102 "0 = disabled, 1 = enabled, 2 = headless)"); 103 int nouveau_modeset = -1; 104 module_param_named(modeset, nouveau_modeset, int, 0400); 105 106 MODULE_PARM_DESC(atomic, "Expose atomic ioctl (default: disabled)"); 107 static int nouveau_atomic = 0; 108 module_param_named(atomic, nouveau_atomic, int, 0400); 109 110 MODULE_PARM_DESC(runpm, "disable (0), force enable (1), optimus only default (-1)"); 111 static int nouveau_runtime_pm = -1; 112 module_param_named(runpm, nouveau_runtime_pm, int, 0400); 113 114 static struct drm_driver driver_stub; 115 static struct drm_driver driver_pci; 116 static struct drm_driver driver_platform; 117 118 #ifdef CONFIG_DEBUG_FS 119 struct dentry *nouveau_debugfs_root; 120 121 /** 122 * gsp_logs - list of nvif_log GSP-RM logging buffers 123 * 124 * Head pointer to a a list of nvif_log buffers that is created for each GPU 125 * upon GSP shutdown if the "keep_gsp_logging" command-line parameter is 126 * specified. This is used to track the alternative debugfs entries for the 127 * GSP-RM logs. 128 */ 129 NVIF_LOGS_DECLARE(gsp_logs); 130 #endif 131 132 static u64 133 nouveau_pci_name(struct pci_dev *pdev) 134 { 135 u64 name = (u64)pci_domain_nr(pdev->bus) << 32; 136 name |= pdev->bus->number << 16; 137 name |= PCI_SLOT(pdev->devfn) << 8; 138 return name | PCI_FUNC(pdev->devfn); 139 } 140 141 static u64 142 nouveau_platform_name(struct platform_device *platformdev) 143 { 144 return platformdev->id; 145 } 146 147 static u64 148 nouveau_name(struct drm_device *dev) 149 { 150 if (dev_is_pci(dev->dev)) 151 return nouveau_pci_name(to_pci_dev(dev->dev)); 152 else 153 return nouveau_platform_name(to_platform_device(dev->dev)); 154 } 155 156 static inline bool 157 nouveau_cli_work_ready(struct dma_fence *fence) 158 { 159 bool ret = true; 160 161 spin_lock_irq(fence->lock); 162 if (!dma_fence_is_signaled_locked(fence)) 163 ret = false; 164 spin_unlock_irq(fence->lock); 165 166 if (ret == true) 167 dma_fence_put(fence); 168 return ret; 169 } 170 171 static void 172 nouveau_cli_work(struct work_struct *w) 173 { 174 struct nouveau_cli *cli = container_of(w, typeof(*cli), work); 175 struct nouveau_cli_work *work, *wtmp; 176 mutex_lock(&cli->lock); 177 list_for_each_entry_safe(work, wtmp, &cli->worker, head) { 178 if (!work->fence || nouveau_cli_work_ready(work->fence)) { 179 list_del(&work->head); 180 work->func(work); 181 } 182 } 183 mutex_unlock(&cli->lock); 184 } 185 186 static void 187 nouveau_cli_work_fence(struct dma_fence *fence, struct dma_fence_cb *cb) 188 { 189 struct nouveau_cli_work *work = container_of(cb, typeof(*work), cb); 190 schedule_work(&work->cli->work); 191 } 192 193 void 194 nouveau_cli_work_queue(struct nouveau_cli *cli, struct dma_fence *fence, 195 struct nouveau_cli_work *work) 196 { 197 work->fence = dma_fence_get(fence); 198 work->cli = cli; 199 mutex_lock(&cli->lock); 200 list_add_tail(&work->head, &cli->worker); 201 if (dma_fence_add_callback(fence, &work->cb, nouveau_cli_work_fence)) 202 nouveau_cli_work_fence(fence, &work->cb); 203 mutex_unlock(&cli->lock); 204 } 205 206 static void 207 nouveau_cli_fini(struct nouveau_cli *cli) 208 { 209 struct nouveau_uvmm *uvmm = nouveau_cli_uvmm_locked(cli); 210 211 /* All our channels are dead now, which means all the fences they 212 * own are signalled, and all callback functions have been called. 213 * 214 * So, after flushing the workqueue, there should be nothing left. 215 */ 216 flush_work(&cli->work); 217 WARN_ON(!list_empty(&cli->worker)); 218 219 if (cli->sched) 220 nouveau_sched_destroy(&cli->sched); 221 if (uvmm) 222 nouveau_uvmm_fini(uvmm); 223 nouveau_vmm_fini(&cli->svm); 224 nouveau_vmm_fini(&cli->vmm); 225 nvif_mmu_dtor(&cli->mmu); 226 cli->device.object.map.ptr = NULL; 227 nvif_device_dtor(&cli->device); 228 mutex_lock(&cli->drm->client_mutex); 229 nvif_client_dtor(&cli->base); 230 mutex_unlock(&cli->drm->client_mutex); 231 } 232 233 static int 234 nouveau_cli_init(struct nouveau_drm *drm, const char *sname, 235 struct nouveau_cli *cli) 236 { 237 static const struct nvif_mclass 238 mems[] = { 239 { NVIF_CLASS_MEM_GF100, -1 }, 240 { NVIF_CLASS_MEM_NV50 , -1 }, 241 { NVIF_CLASS_MEM_NV04 , -1 }, 242 {} 243 }; 244 static const struct nvif_mclass 245 vmms[] = { 246 { NVIF_CLASS_VMM_GP100, -1 }, 247 { NVIF_CLASS_VMM_GM200, -1 }, 248 { NVIF_CLASS_VMM_GF100, -1 }, 249 { NVIF_CLASS_VMM_NV50 , -1 }, 250 { NVIF_CLASS_VMM_NV04 , -1 }, 251 {} 252 }; 253 int ret; 254 255 snprintf(cli->name, sizeof(cli->name), "%s", sname); 256 cli->drm = drm; 257 mutex_init(&cli->mutex); 258 259 INIT_WORK(&cli->work, nouveau_cli_work); 260 INIT_LIST_HEAD(&cli->worker); 261 mutex_init(&cli->lock); 262 263 mutex_lock(&drm->client_mutex); 264 ret = nvif_client_ctor(&drm->_client, cli->name, &cli->base); 265 mutex_unlock(&drm->client_mutex); 266 if (ret) { 267 NV_PRINTK(err, cli, "Client allocation failed: %d\n", ret); 268 goto done; 269 } 270 271 ret = nvif_device_ctor(&cli->base, "drmDevice", &cli->device); 272 if (ret) { 273 NV_PRINTK(err, cli, "Device allocation failed: %d\n", ret); 274 goto done; 275 } 276 277 cli->device.object.map.ptr = drm->device.object.map.ptr; 278 279 ret = nvif_mmu_ctor(&cli->device.object, "drmMmu", drm->mmu.object.oclass, 280 &cli->mmu); 281 if (ret) { 282 NV_PRINTK(err, cli, "MMU allocation failed: %d\n", ret); 283 goto done; 284 } 285 286 ret = nvif_mclass(&cli->mmu.object, vmms); 287 if (ret < 0) { 288 NV_PRINTK(err, cli, "No supported VMM class\n"); 289 goto done; 290 } 291 292 ret = nouveau_vmm_init(cli, vmms[ret].oclass, &cli->vmm); 293 if (ret) { 294 NV_PRINTK(err, cli, "VMM allocation failed: %d\n", ret); 295 goto done; 296 } 297 298 ret = nvif_mclass(&cli->mmu.object, mems); 299 if (ret < 0) { 300 NV_PRINTK(err, cli, "No supported MEM class\n"); 301 goto done; 302 } 303 304 cli->mem = &mems[ret]; 305 306 /* Don't pass in the (shared) sched_wq in order to let 307 * nouveau_sched_create() create a dedicated one for VM_BIND jobs. 308 * 309 * This is required to ensure that for VM_BIND jobs free_job() work and 310 * run_job() work can always run concurrently and hence, free_job() work 311 * can never stall run_job() work. For EXEC jobs we don't have this 312 * requirement, since EXEC job's free_job() does not require to take any 313 * locks which indirectly or directly are held for allocations 314 * elsewhere. 315 */ 316 ret = nouveau_sched_create(&cli->sched, drm, NULL, 1); 317 if (ret) 318 goto done; 319 320 return 0; 321 done: 322 if (ret) 323 nouveau_cli_fini(cli); 324 return ret; 325 } 326 327 static void 328 nouveau_accel_ce_fini(struct nouveau_drm *drm) 329 { 330 nouveau_channel_idle(drm->cechan); 331 nvif_object_dtor(&drm->ttm.copy); 332 nouveau_channel_del(&drm->cechan); 333 } 334 335 static void 336 nouveau_accel_ce_init(struct nouveau_drm *drm) 337 { 338 struct nvif_device *device = &drm->client.device; 339 u64 runm; 340 int ret = 0; 341 342 /* Allocate channel that has access to a (preferably async) copy 343 * engine, to use for TTM buffer moves. 344 */ 345 runm = nvif_fifo_runlist_ce(device); 346 if (!runm) { 347 NV_DEBUG(drm, "no ce runlist\n"); 348 return; 349 } 350 351 ret = nouveau_channel_new(&drm->client, true, runm, NvDmaFB, NvDmaTT, &drm->cechan); 352 if (ret) 353 NV_ERROR(drm, "failed to create ce channel, %d\n", ret); 354 } 355 356 static void 357 nouveau_accel_gr_fini(struct nouveau_drm *drm) 358 { 359 nouveau_channel_idle(drm->channel); 360 nvif_object_dtor(&drm->ntfy); 361 nvkm_gpuobj_del(&drm->notify); 362 nouveau_channel_del(&drm->channel); 363 } 364 365 static void 366 nouveau_accel_gr_init(struct nouveau_drm *drm) 367 { 368 struct nvif_device *device = &drm->client.device; 369 u64 runm; 370 int ret; 371 372 /* Allocate channel that has access to the graphics engine. */ 373 runm = nvif_fifo_runlist(device, NV_DEVICE_HOST_RUNLIST_ENGINES_GR); 374 if (!runm) { 375 NV_DEBUG(drm, "no gr runlist\n"); 376 return; 377 } 378 379 ret = nouveau_channel_new(&drm->client, false, runm, NvDmaFB, NvDmaTT, &drm->channel); 380 if (ret) { 381 NV_ERROR(drm, "failed to create kernel channel, %d\n", ret); 382 nouveau_accel_gr_fini(drm); 383 return; 384 } 385 386 /* A SW class is used on pre-NV50 HW to assist with handling the 387 * synchronisation of page flips, as well as to implement fences 388 * on TNT/TNT2 HW that lacks any kind of support in host. 389 */ 390 if (!drm->channel->nvsw.client && device->info.family < NV_DEVICE_INFO_V0_TESLA) { 391 ret = nvif_object_ctor(&drm->channel->user, "drmNvsw", 392 NVDRM_NVSW, nouveau_abi16_swclass(drm), 393 NULL, 0, &drm->channel->nvsw); 394 395 if (ret == 0 && device->info.chipset >= 0x11) { 396 ret = nvif_object_ctor(&drm->channel->user, "drmBlit", 397 0x005f, 0x009f, 398 NULL, 0, &drm->channel->blit); 399 } 400 401 if (ret == 0) { 402 struct nvif_push *push = &drm->channel->chan.push; 403 404 ret = PUSH_WAIT(push, 8); 405 if (ret == 0) { 406 if (device->info.chipset >= 0x11) { 407 PUSH_NVSQ(push, NV05F, 0x0000, drm->channel->blit.handle); 408 PUSH_NVSQ(push, NV09F, 0x0120, 0, 409 0x0124, 1, 410 0x0128, 2); 411 } 412 PUSH_NVSQ(push, NV_SW, 0x0000, drm->channel->nvsw.handle); 413 } 414 } 415 416 if (ret) { 417 NV_ERROR(drm, "failed to allocate sw or blit class, %d\n", ret); 418 nouveau_accel_gr_fini(drm); 419 return; 420 } 421 } 422 423 /* NvMemoryToMemoryFormat requires a notifier ctxdma for some reason, 424 * even if notification is never requested, so, allocate a ctxdma on 425 * any GPU where it's possible we'll end up using M2MF for BO moves. 426 */ 427 if (device->info.family < NV_DEVICE_INFO_V0_FERMI) { 428 ret = nvkm_gpuobj_new(nvxx_device(drm), 32, 0, false, NULL, &drm->notify); 429 if (ret) { 430 NV_ERROR(drm, "failed to allocate notifier, %d\n", ret); 431 nouveau_accel_gr_fini(drm); 432 return; 433 } 434 435 ret = nvif_object_ctor(&drm->channel->user, "drmM2mfNtfy", 436 NvNotify0, NV_DMA_IN_MEMORY, 437 &(struct nv_dma_v0) { 438 .target = NV_DMA_V0_TARGET_VRAM, 439 .access = NV_DMA_V0_ACCESS_RDWR, 440 .start = drm->notify->addr, 441 .limit = drm->notify->addr + 31 442 }, sizeof(struct nv_dma_v0), 443 &drm->ntfy); 444 if (ret) { 445 nouveau_accel_gr_fini(drm); 446 return; 447 } 448 } 449 } 450 451 static void 452 nouveau_accel_fini(struct nouveau_drm *drm) 453 { 454 nouveau_accel_ce_fini(drm); 455 nouveau_accel_gr_fini(drm); 456 if (drm->fence) 457 nouveau_fence(drm)->dtor(drm); 458 nouveau_channels_fini(drm); 459 } 460 461 static void 462 nouveau_accel_init(struct nouveau_drm *drm) 463 { 464 struct nvif_device *device = &drm->client.device; 465 struct nvif_sclass *sclass; 466 int ret, i, n; 467 468 if (nouveau_noaccel) 469 return; 470 471 /* Initialise global support for channels, and synchronisation. */ 472 ret = nouveau_channels_init(drm); 473 if (ret) 474 return; 475 476 /*XXX: this is crap, but the fence/channel stuff is a little 477 * backwards in some places. this will be fixed. 478 */ 479 ret = n = nvif_object_sclass_get(&device->object, &sclass); 480 if (ret < 0) 481 return; 482 483 for (ret = -ENOSYS, i = 0; i < n; i++) { 484 switch (sclass[i].oclass) { 485 case NV03_CHANNEL_DMA: 486 ret = nv04_fence_create(drm); 487 break; 488 case NV10_CHANNEL_DMA: 489 ret = nv10_fence_create(drm); 490 break; 491 case NV17_CHANNEL_DMA: 492 case NV40_CHANNEL_DMA: 493 ret = nv17_fence_create(drm); 494 break; 495 case NV50_CHANNEL_GPFIFO: 496 ret = nv50_fence_create(drm); 497 break; 498 case G82_CHANNEL_GPFIFO: 499 ret = nv84_fence_create(drm); 500 break; 501 case FERMI_CHANNEL_GPFIFO: 502 case KEPLER_CHANNEL_GPFIFO_A: 503 case KEPLER_CHANNEL_GPFIFO_B: 504 case MAXWELL_CHANNEL_GPFIFO_A: 505 case PASCAL_CHANNEL_GPFIFO_A: 506 case VOLTA_CHANNEL_GPFIFO_A: 507 case TURING_CHANNEL_GPFIFO_A: 508 case AMPERE_CHANNEL_GPFIFO_A: 509 case AMPERE_CHANNEL_GPFIFO_B: 510 ret = nvc0_fence_create(drm); 511 break; 512 default: 513 break; 514 } 515 } 516 517 nvif_object_sclass_put(&sclass); 518 if (ret) { 519 NV_ERROR(drm, "failed to initialise sync subsystem, %d\n", ret); 520 nouveau_accel_fini(drm); 521 return; 522 } 523 524 /* Volta requires access to a doorbell register for kickoff. */ 525 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_VOLTA) { 526 ret = nvif_user_ctor(device, "drmUsermode"); 527 if (ret) 528 return; 529 } 530 531 /* Allocate channels we need to support various functions. */ 532 nouveau_accel_gr_init(drm); 533 nouveau_accel_ce_init(drm); 534 535 /* Initialise accelerated TTM buffer moves. */ 536 nouveau_bo_move_init(drm); 537 } 538 539 static void __printf(2, 3) 540 nouveau_drm_errorf(struct nvif_object *object, const char *fmt, ...) 541 { 542 struct nouveau_drm *drm = container_of(object->parent, typeof(*drm), parent); 543 struct va_format vaf; 544 va_list va; 545 546 va_start(va, fmt); 547 vaf.fmt = fmt; 548 vaf.va = &va; 549 NV_ERROR(drm, "%pV", &vaf); 550 va_end(va); 551 } 552 553 static void __printf(2, 3) 554 nouveau_drm_debugf(struct nvif_object *object, const char *fmt, ...) 555 { 556 struct nouveau_drm *drm = container_of(object->parent, typeof(*drm), parent); 557 struct va_format vaf; 558 va_list va; 559 560 va_start(va, fmt); 561 vaf.fmt = fmt; 562 vaf.va = &va; 563 NV_DEBUG(drm, "%pV", &vaf); 564 va_end(va); 565 } 566 567 static const struct nvif_parent_func 568 nouveau_parent = { 569 .debugf = nouveau_drm_debugf, 570 .errorf = nouveau_drm_errorf, 571 }; 572 573 static void 574 nouveau_drm_device_fini(struct nouveau_drm *drm) 575 { 576 struct drm_device *dev = drm->dev; 577 struct nouveau_cli *cli, *temp_cli; 578 579 if (nouveau_pmops_runtime()) { 580 pm_runtime_get_sync(dev->dev); 581 pm_runtime_forbid(dev->dev); 582 } 583 584 nouveau_led_fini(dev); 585 nouveau_dmem_fini(drm); 586 nouveau_svm_fini(drm); 587 nouveau_hwmon_fini(dev); 588 nouveau_debugfs_fini(drm); 589 590 if (dev->mode_config.num_crtc) 591 nouveau_display_fini(dev, false, false); 592 nouveau_display_destroy(dev); 593 594 nouveau_accel_fini(drm); 595 nouveau_bios_takedown(dev); 596 597 nouveau_ttm_fini(drm); 598 nouveau_vga_fini(drm); 599 600 /* 601 * There may be existing clients from as-yet unclosed files. For now, 602 * clean them up here rather than deferring until the file is closed, 603 * but this likely not correct if we want to support hot-unplugging 604 * properly. 605 */ 606 mutex_lock(&drm->clients_lock); 607 list_for_each_entry_safe(cli, temp_cli, &drm->clients, head) { 608 list_del(&cli->head); 609 mutex_lock(&cli->mutex); 610 if (cli->abi16) 611 nouveau_abi16_fini(cli->abi16); 612 mutex_unlock(&cli->mutex); 613 nouveau_cli_fini(cli); 614 kfree(cli); 615 } 616 mutex_unlock(&drm->clients_lock); 617 618 nouveau_cli_fini(&drm->client); 619 destroy_workqueue(drm->sched_wq); 620 mutex_destroy(&drm->clients_lock); 621 } 622 623 static int 624 nouveau_drm_device_init(struct nouveau_drm *drm) 625 { 626 struct drm_device *dev = drm->dev; 627 int ret; 628 629 drm->sched_wq = alloc_workqueue("nouveau_sched_wq_shared", 0, 630 WQ_MAX_ACTIVE); 631 if (!drm->sched_wq) 632 return -ENOMEM; 633 634 ret = nouveau_cli_init(drm, "DRM", &drm->client); 635 if (ret) 636 goto fail_wq; 637 638 INIT_LIST_HEAD(&drm->clients); 639 mutex_init(&drm->clients_lock); 640 spin_lock_init(&drm->tile.lock); 641 642 /* workaround an odd issue on nvc1 by disabling the device's 643 * nosnoop capability. hopefully won't cause issues until a 644 * better fix is found - assuming there is one... 645 */ 646 if (drm->client.device.info.chipset == 0xc1) 647 nvif_mask(&drm->client.device.object, 0x00088080, 0x00000800, 0x00000000); 648 649 nouveau_vga_init(drm); 650 651 ret = nouveau_ttm_init(drm); 652 if (ret) 653 goto fail_ttm; 654 655 ret = nouveau_bios_init(dev); 656 if (ret) 657 goto fail_bios; 658 659 nouveau_accel_init(drm); 660 661 ret = nouveau_display_create(dev); 662 if (ret) 663 goto fail_dispctor; 664 665 if (dev->mode_config.num_crtc) { 666 ret = nouveau_display_init(dev, false, false); 667 if (ret) 668 goto fail_dispinit; 669 } 670 671 nouveau_debugfs_init(drm); 672 nouveau_hwmon_init(dev); 673 nouveau_svm_init(drm); 674 nouveau_dmem_init(drm); 675 nouveau_led_init(dev); 676 677 if (nouveau_pmops_runtime()) { 678 pm_runtime_use_autosuspend(dev->dev); 679 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 680 pm_runtime_set_active(dev->dev); 681 pm_runtime_allow(dev->dev); 682 pm_runtime_mark_last_busy(dev->dev); 683 pm_runtime_put(dev->dev); 684 } 685 686 ret = drm_dev_register(drm->dev, 0); 687 if (ret) { 688 nouveau_drm_device_fini(drm); 689 return ret; 690 } 691 692 return 0; 693 fail_dispinit: 694 nouveau_display_destroy(dev); 695 fail_dispctor: 696 nouveau_accel_fini(drm); 697 nouveau_bios_takedown(dev); 698 fail_bios: 699 nouveau_ttm_fini(drm); 700 fail_ttm: 701 nouveau_vga_fini(drm); 702 nouveau_cli_fini(&drm->client); 703 fail_wq: 704 destroy_workqueue(drm->sched_wq); 705 return ret; 706 } 707 708 static void 709 nouveau_drm_device_del(struct nouveau_drm *drm) 710 { 711 if (drm->dev) 712 drm_dev_put(drm->dev); 713 714 nvif_mmu_dtor(&drm->mmu); 715 nvif_device_dtor(&drm->device); 716 nvif_client_dtor(&drm->_client); 717 nvif_parent_dtor(&drm->parent); 718 719 mutex_destroy(&drm->client_mutex); 720 kfree(drm); 721 } 722 723 static struct nouveau_drm * 724 nouveau_drm_device_new(const struct drm_driver *drm_driver, struct device *parent, 725 struct nvkm_device *device) 726 { 727 static const struct nvif_mclass 728 mmus[] = { 729 { NVIF_CLASS_MMU_GF100, -1 }, 730 { NVIF_CLASS_MMU_NV50 , -1 }, 731 { NVIF_CLASS_MMU_NV04 , -1 }, 732 {} 733 }; 734 struct nouveau_drm *drm; 735 int ret; 736 737 drm = kzalloc(sizeof(*drm), GFP_KERNEL); 738 if (!drm) 739 return ERR_PTR(-ENOMEM); 740 741 drm->nvkm = device; 742 743 drm->dev = drm_dev_alloc(drm_driver, parent); 744 if (IS_ERR(drm->dev)) { 745 ret = PTR_ERR(drm->dev); 746 goto done; 747 } 748 749 drm->dev->dev_private = drm; 750 dev_set_drvdata(parent, drm); 751 752 nvif_parent_ctor(&nouveau_parent, &drm->parent); 753 mutex_init(&drm->client_mutex); 754 drm->_client.object.parent = &drm->parent; 755 756 ret = nvif_driver_init(NULL, nouveau_config, nouveau_debug, "drm", 757 nouveau_name(drm->dev), &drm->_client); 758 if (ret) 759 goto done; 760 761 ret = nvif_device_ctor(&drm->_client, "drmDevice", &drm->device); 762 if (ret) { 763 NV_ERROR(drm, "Device allocation failed: %d\n", ret); 764 goto done; 765 } 766 767 ret = nvif_device_map(&drm->device); 768 if (ret) { 769 NV_ERROR(drm, "Failed to map PRI: %d\n", ret); 770 goto done; 771 } 772 773 ret = nvif_mclass(&drm->device.object, mmus); 774 if (ret < 0) { 775 NV_ERROR(drm, "No supported MMU class\n"); 776 goto done; 777 } 778 779 ret = nvif_mmu_ctor(&drm->device.object, "drmMmu", mmus[ret].oclass, &drm->mmu); 780 if (ret) { 781 NV_ERROR(drm, "MMU allocation failed: %d\n", ret); 782 goto done; 783 } 784 785 done: 786 if (ret) { 787 nouveau_drm_device_del(drm); 788 drm = NULL; 789 } 790 791 return ret ? ERR_PTR(ret) : drm; 792 } 793 794 /* 795 * On some Intel PCIe bridge controllers doing a 796 * D0 -> D3hot -> D3cold -> D0 sequence causes Nvidia GPUs to not reappear. 797 * Skipping the intermediate D3hot step seems to make it work again. This is 798 * probably caused by not meeting the expectation the involved AML code has 799 * when the GPU is put into D3hot state before invoking it. 800 * 801 * This leads to various manifestations of this issue: 802 * - AML code execution to power on the GPU hits an infinite loop (as the 803 * code waits on device memory to change). 804 * - kernel crashes, as all PCI reads return -1, which most code isn't able 805 * to handle well enough. 806 * 807 * In all cases dmesg will contain at least one line like this: 808 * 'nouveau 0000:01:00.0: Refused to change power state, currently in D3' 809 * followed by a lot of nouveau timeouts. 810 * 811 * In the \_SB.PCI0.PEG0.PG00._OFF code deeper down writes bit 0x80 to the not 812 * documented PCI config space register 0x248 of the Intel PCIe bridge 813 * controller (0x1901) in order to change the state of the PCIe link between 814 * the PCIe port and the GPU. There are alternative code paths using other 815 * registers, which seem to work fine (executed pre Windows 8): 816 * - 0xbc bit 0x20 (publicly available documentation claims 'reserved') 817 * - 0xb0 bit 0x10 (link disable) 818 * Changing the conditions inside the firmware by poking into the relevant 819 * addresses does resolve the issue, but it seemed to be ACPI private memory 820 * and not any device accessible memory at all, so there is no portable way of 821 * changing the conditions. 822 * On a XPS 9560 that means bits [0,3] on \CPEX need to be cleared. 823 * 824 * The only systems where this behavior can be seen are hybrid graphics laptops 825 * with a secondary Nvidia Maxwell, Pascal or Turing GPU. It's unclear whether 826 * this issue only occurs in combination with listed Intel PCIe bridge 827 * controllers and the mentioned GPUs or other devices as well. 828 * 829 * documentation on the PCIe bridge controller can be found in the 830 * "7th Generation Intel® Processor Families for H Platforms Datasheet Volume 2" 831 * Section "12 PCI Express* Controller (x16) Registers" 832 */ 833 834 static void quirk_broken_nv_runpm(struct pci_dev *pdev) 835 { 836 struct nouveau_drm *drm = pci_get_drvdata(pdev); 837 struct pci_dev *bridge = pci_upstream_bridge(pdev); 838 839 if (!bridge || bridge->vendor != PCI_VENDOR_ID_INTEL) 840 return; 841 842 switch (bridge->device) { 843 case 0x1901: 844 drm->old_pm_cap = pdev->pm_cap; 845 pdev->pm_cap = 0; 846 NV_INFO(drm, "Disabling PCI power management to avoid bug\n"); 847 break; 848 } 849 } 850 851 static int nouveau_drm_probe(struct pci_dev *pdev, 852 const struct pci_device_id *pent) 853 { 854 struct nvkm_device *device; 855 struct nouveau_drm *drm; 856 const struct drm_format_info *format; 857 int ret; 858 859 if (vga_switcheroo_client_probe_defer(pdev)) 860 return -EPROBE_DEFER; 861 862 /* We need to check that the chipset is supported before booting 863 * fbdev off the hardware, as there's no way to put it back. 864 */ 865 ret = nvkm_device_pci_new(pdev, nouveau_config, nouveau_debug, &device); 866 if (ret) 867 return ret; 868 869 /* Remove conflicting drivers (vesafb, efifb etc). */ 870 ret = aperture_remove_conflicting_pci_devices(pdev, driver_pci.name); 871 if (ret) 872 return ret; 873 874 pci_set_master(pdev); 875 876 if (nouveau_atomic) 877 driver_pci.driver_features |= DRIVER_ATOMIC; 878 879 drm = nouveau_drm_device_new(&driver_pci, &pdev->dev, device); 880 if (IS_ERR(drm)) { 881 ret = PTR_ERR(drm); 882 goto fail_nvkm; 883 } 884 885 ret = pci_enable_device(pdev); 886 if (ret) 887 goto fail_drm; 888 889 ret = nouveau_drm_device_init(drm); 890 if (ret) 891 goto fail_pci; 892 893 if (drm->client.device.info.ram_size <= 32 * 1024 * 1024) 894 format = drm_format_info(DRM_FORMAT_C8); 895 else 896 format = NULL; 897 898 drm_client_setup(drm->dev, format); 899 900 quirk_broken_nv_runpm(pdev); 901 return 0; 902 903 fail_pci: 904 pci_disable_device(pdev); 905 fail_drm: 906 nouveau_drm_device_del(drm); 907 fail_nvkm: 908 nvkm_device_del(&device); 909 return ret; 910 } 911 912 void 913 nouveau_drm_device_remove(struct nouveau_drm *drm) 914 { 915 struct nvkm_device *device = drm->nvkm; 916 917 drm_dev_unplug(drm->dev); 918 919 nouveau_drm_device_fini(drm); 920 nouveau_drm_device_del(drm); 921 nvkm_device_del(&device); 922 } 923 924 static void 925 nouveau_drm_remove(struct pci_dev *pdev) 926 { 927 struct nouveau_drm *drm = pci_get_drvdata(pdev); 928 929 /* revert our workaround */ 930 if (drm->old_pm_cap) 931 pdev->pm_cap = drm->old_pm_cap; 932 nouveau_drm_device_remove(drm); 933 pci_disable_device(pdev); 934 } 935 936 static int 937 nouveau_do_suspend(struct nouveau_drm *drm, bool runtime) 938 { 939 struct drm_device *dev = drm->dev; 940 struct ttm_resource_manager *man; 941 int ret; 942 943 nouveau_svm_suspend(drm); 944 nouveau_dmem_suspend(drm); 945 nouveau_led_suspend(dev); 946 947 if (dev->mode_config.num_crtc) { 948 NV_DEBUG(drm, "suspending display...\n"); 949 ret = nouveau_display_suspend(dev, runtime); 950 if (ret) 951 return ret; 952 } 953 954 NV_DEBUG(drm, "evicting buffers...\n"); 955 956 man = ttm_manager_type(&drm->ttm.bdev, TTM_PL_VRAM); 957 ttm_resource_manager_evict_all(&drm->ttm.bdev, man); 958 959 NV_DEBUG(drm, "waiting for kernel channels to go idle...\n"); 960 if (drm->cechan) { 961 ret = nouveau_channel_idle(drm->cechan); 962 if (ret) 963 goto fail_display; 964 } 965 966 if (drm->channel) { 967 ret = nouveau_channel_idle(drm->channel); 968 if (ret) 969 goto fail_display; 970 } 971 972 NV_DEBUG(drm, "suspending fence...\n"); 973 if (drm->fence && nouveau_fence(drm)->suspend) { 974 if (!nouveau_fence(drm)->suspend(drm)) { 975 ret = -ENOMEM; 976 goto fail_display; 977 } 978 } 979 980 NV_DEBUG(drm, "suspending object tree...\n"); 981 ret = nvif_client_suspend(&drm->_client); 982 if (ret) 983 goto fail_client; 984 985 return 0; 986 987 fail_client: 988 if (drm->fence && nouveau_fence(drm)->resume) 989 nouveau_fence(drm)->resume(drm); 990 991 fail_display: 992 if (dev->mode_config.num_crtc) { 993 NV_DEBUG(drm, "resuming display...\n"); 994 nouveau_display_resume(dev, runtime); 995 } 996 return ret; 997 } 998 999 static int 1000 nouveau_do_resume(struct nouveau_drm *drm, bool runtime) 1001 { 1002 struct drm_device *dev = drm->dev; 1003 int ret = 0; 1004 1005 NV_DEBUG(drm, "resuming object tree...\n"); 1006 ret = nvif_client_resume(&drm->_client); 1007 if (ret) { 1008 NV_ERROR(drm, "Client resume failed with error: %d\n", ret); 1009 return ret; 1010 } 1011 1012 NV_DEBUG(drm, "resuming fence...\n"); 1013 if (drm->fence && nouveau_fence(drm)->resume) 1014 nouveau_fence(drm)->resume(drm); 1015 1016 nouveau_run_vbios_init(dev); 1017 1018 if (dev->mode_config.num_crtc) { 1019 NV_DEBUG(drm, "resuming display...\n"); 1020 nouveau_display_resume(dev, runtime); 1021 } 1022 1023 nouveau_led_resume(dev); 1024 nouveau_dmem_resume(drm); 1025 nouveau_svm_resume(drm); 1026 return 0; 1027 } 1028 1029 int 1030 nouveau_pmops_suspend(struct device *dev) 1031 { 1032 struct pci_dev *pdev = to_pci_dev(dev); 1033 struct nouveau_drm *drm = pci_get_drvdata(pdev); 1034 int ret; 1035 1036 if (drm->dev->switch_power_state == DRM_SWITCH_POWER_OFF || 1037 drm->dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF) 1038 return 0; 1039 1040 ret = nouveau_do_suspend(drm, false); 1041 if (ret) 1042 return ret; 1043 1044 pci_save_state(pdev); 1045 pci_disable_device(pdev); 1046 pci_set_power_state(pdev, PCI_D3hot); 1047 udelay(200); 1048 return 0; 1049 } 1050 1051 int 1052 nouveau_pmops_resume(struct device *dev) 1053 { 1054 struct pci_dev *pdev = to_pci_dev(dev); 1055 struct nouveau_drm *drm = pci_get_drvdata(pdev); 1056 int ret; 1057 1058 if (drm->dev->switch_power_state == DRM_SWITCH_POWER_OFF || 1059 drm->dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF) 1060 return 0; 1061 1062 pci_set_power_state(pdev, PCI_D0); 1063 pci_restore_state(pdev); 1064 ret = pci_enable_device(pdev); 1065 if (ret) 1066 return ret; 1067 pci_set_master(pdev); 1068 1069 ret = nouveau_do_resume(drm, false); 1070 1071 /* Monitors may have been connected / disconnected during suspend */ 1072 nouveau_display_hpd_resume(drm); 1073 1074 return ret; 1075 } 1076 1077 static int 1078 nouveau_pmops_freeze(struct device *dev) 1079 { 1080 struct nouveau_drm *drm = dev_get_drvdata(dev); 1081 1082 return nouveau_do_suspend(drm, false); 1083 } 1084 1085 static int 1086 nouveau_pmops_thaw(struct device *dev) 1087 { 1088 struct nouveau_drm *drm = dev_get_drvdata(dev); 1089 1090 return nouveau_do_resume(drm, false); 1091 } 1092 1093 bool 1094 nouveau_pmops_runtime(void) 1095 { 1096 if (nouveau_runtime_pm == -1) 1097 return nouveau_is_optimus() || nouveau_is_v1_dsm(); 1098 return nouveau_runtime_pm == 1; 1099 } 1100 1101 static int 1102 nouveau_pmops_runtime_suspend(struct device *dev) 1103 { 1104 struct pci_dev *pdev = to_pci_dev(dev); 1105 struct nouveau_drm *drm = pci_get_drvdata(pdev); 1106 int ret; 1107 1108 if (!nouveau_pmops_runtime()) { 1109 pm_runtime_forbid(dev); 1110 return -EBUSY; 1111 } 1112 1113 nouveau_switcheroo_optimus_dsm(); 1114 ret = nouveau_do_suspend(drm, true); 1115 pci_save_state(pdev); 1116 pci_disable_device(pdev); 1117 pci_ignore_hotplug(pdev); 1118 pci_set_power_state(pdev, PCI_D3cold); 1119 drm->dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 1120 return ret; 1121 } 1122 1123 static int 1124 nouveau_pmops_runtime_resume(struct device *dev) 1125 { 1126 struct pci_dev *pdev = to_pci_dev(dev); 1127 struct nouveau_drm *drm = pci_get_drvdata(pdev); 1128 struct nvif_device *device = &drm->client.device; 1129 int ret; 1130 1131 if (!nouveau_pmops_runtime()) { 1132 pm_runtime_forbid(dev); 1133 return -EBUSY; 1134 } 1135 1136 pci_set_power_state(pdev, PCI_D0); 1137 pci_restore_state(pdev); 1138 ret = pci_enable_device(pdev); 1139 if (ret) 1140 return ret; 1141 pci_set_master(pdev); 1142 1143 ret = nouveau_do_resume(drm, true); 1144 if (ret) { 1145 NV_ERROR(drm, "resume failed with: %d\n", ret); 1146 return ret; 1147 } 1148 1149 /* do magic */ 1150 nvif_mask(&device->object, 0x088488, (1 << 25), (1 << 25)); 1151 drm->dev->switch_power_state = DRM_SWITCH_POWER_ON; 1152 1153 /* Monitors may have been connected / disconnected during suspend */ 1154 nouveau_display_hpd_resume(drm); 1155 1156 return ret; 1157 } 1158 1159 static int 1160 nouveau_pmops_runtime_idle(struct device *dev) 1161 { 1162 if (!nouveau_pmops_runtime()) { 1163 pm_runtime_forbid(dev); 1164 return -EBUSY; 1165 } 1166 1167 pm_runtime_mark_last_busy(dev); 1168 pm_runtime_autosuspend(dev); 1169 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 1170 return 1; 1171 } 1172 1173 static int 1174 nouveau_drm_open(struct drm_device *dev, struct drm_file *fpriv) 1175 { 1176 struct nouveau_drm *drm = nouveau_drm(dev); 1177 struct nouveau_cli *cli; 1178 char name[32], tmpname[TASK_COMM_LEN]; 1179 int ret; 1180 1181 /* need to bring up power immediately if opening device */ 1182 ret = pm_runtime_get_sync(dev->dev); 1183 if (ret < 0 && ret != -EACCES) { 1184 pm_runtime_put_autosuspend(dev->dev); 1185 return ret; 1186 } 1187 1188 get_task_comm(tmpname, current); 1189 rcu_read_lock(); 1190 snprintf(name, sizeof(name), "%s[%d]", 1191 tmpname, pid_nr(rcu_dereference(fpriv->pid))); 1192 rcu_read_unlock(); 1193 1194 if (!(cli = kzalloc(sizeof(*cli), GFP_KERNEL))) { 1195 ret = -ENOMEM; 1196 goto done; 1197 } 1198 1199 ret = nouveau_cli_init(drm, name, cli); 1200 if (ret) 1201 goto done; 1202 1203 fpriv->driver_priv = cli; 1204 1205 mutex_lock(&drm->clients_lock); 1206 list_add(&cli->head, &drm->clients); 1207 mutex_unlock(&drm->clients_lock); 1208 1209 done: 1210 if (ret && cli) { 1211 nouveau_cli_fini(cli); 1212 kfree(cli); 1213 } 1214 1215 pm_runtime_mark_last_busy(dev->dev); 1216 pm_runtime_put_autosuspend(dev->dev); 1217 return ret; 1218 } 1219 1220 static void 1221 nouveau_drm_postclose(struct drm_device *dev, struct drm_file *fpriv) 1222 { 1223 struct nouveau_cli *cli = nouveau_cli(fpriv); 1224 struct nouveau_drm *drm = nouveau_drm(dev); 1225 int dev_index; 1226 1227 /* 1228 * The device is gone, and as it currently stands all clients are 1229 * cleaned up in the removal codepath. In the future this may change 1230 * so that we can support hot-unplugging, but for now we immediately 1231 * return to avoid a double-free situation. 1232 */ 1233 if (!drm_dev_enter(dev, &dev_index)) 1234 return; 1235 1236 pm_runtime_get_sync(dev->dev); 1237 1238 mutex_lock(&cli->mutex); 1239 if (cli->abi16) 1240 nouveau_abi16_fini(cli->abi16); 1241 mutex_unlock(&cli->mutex); 1242 1243 mutex_lock(&drm->clients_lock); 1244 list_del(&cli->head); 1245 mutex_unlock(&drm->clients_lock); 1246 1247 nouveau_cli_fini(cli); 1248 kfree(cli); 1249 pm_runtime_mark_last_busy(dev->dev); 1250 pm_runtime_put_autosuspend(dev->dev); 1251 drm_dev_exit(dev_index); 1252 } 1253 1254 static const struct drm_ioctl_desc 1255 nouveau_ioctls[] = { 1256 DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_RENDER_ALLOW), 1257 DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1258 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_RENDER_ALLOW), 1259 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_RENDER_ALLOW), 1260 DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_RENDER_ALLOW), 1261 DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_RENDER_ALLOW), 1262 DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_RENDER_ALLOW), 1263 DRM_IOCTL_DEF_DRV(NOUVEAU_SVM_INIT, nouveau_svmm_init, DRM_RENDER_ALLOW), 1264 DRM_IOCTL_DEF_DRV(NOUVEAU_SVM_BIND, nouveau_svmm_bind, DRM_RENDER_ALLOW), 1265 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_RENDER_ALLOW), 1266 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_RENDER_ALLOW), 1267 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_RENDER_ALLOW), 1268 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_RENDER_ALLOW), 1269 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_RENDER_ALLOW), 1270 DRM_IOCTL_DEF_DRV(NOUVEAU_VM_INIT, nouveau_uvmm_ioctl_vm_init, DRM_RENDER_ALLOW), 1271 DRM_IOCTL_DEF_DRV(NOUVEAU_VM_BIND, nouveau_uvmm_ioctl_vm_bind, DRM_RENDER_ALLOW), 1272 DRM_IOCTL_DEF_DRV(NOUVEAU_EXEC, nouveau_exec_ioctl_exec, DRM_RENDER_ALLOW), 1273 }; 1274 1275 long 1276 nouveau_drm_ioctl(struct file *file, unsigned int cmd, unsigned long arg) 1277 { 1278 struct drm_file *filp = file->private_data; 1279 struct drm_device *dev = filp->minor->dev; 1280 long ret; 1281 1282 ret = pm_runtime_get_sync(dev->dev); 1283 if (ret < 0 && ret != -EACCES) { 1284 pm_runtime_put_autosuspend(dev->dev); 1285 return ret; 1286 } 1287 1288 switch (_IOC_NR(cmd) - DRM_COMMAND_BASE) { 1289 case DRM_NOUVEAU_NVIF: 1290 ret = nouveau_abi16_ioctl(filp, (void __user *)arg, _IOC_SIZE(cmd)); 1291 break; 1292 default: 1293 ret = drm_ioctl(file, cmd, arg); 1294 break; 1295 } 1296 1297 pm_runtime_mark_last_busy(dev->dev); 1298 pm_runtime_put_autosuspend(dev->dev); 1299 return ret; 1300 } 1301 1302 static const struct file_operations 1303 nouveau_driver_fops = { 1304 .owner = THIS_MODULE, 1305 .open = drm_open, 1306 .release = drm_release, 1307 .unlocked_ioctl = nouveau_drm_ioctl, 1308 .mmap = drm_gem_mmap, 1309 .poll = drm_poll, 1310 .read = drm_read, 1311 #if defined(CONFIG_COMPAT) 1312 .compat_ioctl = nouveau_compat_ioctl, 1313 #endif 1314 .llseek = noop_llseek, 1315 .fop_flags = FOP_UNSIGNED_OFFSET, 1316 }; 1317 1318 static struct drm_driver 1319 driver_stub = { 1320 .driver_features = DRIVER_GEM | 1321 DRIVER_SYNCOBJ | DRIVER_SYNCOBJ_TIMELINE | 1322 DRIVER_GEM_GPUVA | 1323 DRIVER_MODESET | 1324 DRIVER_RENDER, 1325 .open = nouveau_drm_open, 1326 .postclose = nouveau_drm_postclose, 1327 1328 #if defined(CONFIG_DEBUG_FS) 1329 .debugfs_init = nouveau_drm_debugfs_init, 1330 #endif 1331 1332 .ioctls = nouveau_ioctls, 1333 .num_ioctls = ARRAY_SIZE(nouveau_ioctls), 1334 .fops = &nouveau_driver_fops, 1335 1336 .gem_prime_import_sg_table = nouveau_gem_prime_import_sg_table, 1337 1338 .dumb_create = nouveau_display_dumb_create, 1339 .dumb_map_offset = drm_gem_ttm_dumb_map_offset, 1340 1341 DRM_FBDEV_TTM_DRIVER_OPS, 1342 1343 .name = DRIVER_NAME, 1344 .desc = DRIVER_DESC, 1345 .major = DRIVER_MAJOR, 1346 .minor = DRIVER_MINOR, 1347 .patchlevel = DRIVER_PATCHLEVEL, 1348 }; 1349 1350 static struct pci_device_id 1351 nouveau_drm_pci_table[] = { 1352 { 1353 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), 1354 .class = PCI_BASE_CLASS_DISPLAY << 16, 1355 .class_mask = 0xff << 16, 1356 }, 1357 { 1358 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID), 1359 .class = PCI_BASE_CLASS_DISPLAY << 16, 1360 .class_mask = 0xff << 16, 1361 }, 1362 {} 1363 }; 1364 1365 static void nouveau_display_options(void) 1366 { 1367 DRM_DEBUG_DRIVER("Loading Nouveau with parameters:\n"); 1368 1369 DRM_DEBUG_DRIVER("... tv_disable : %d\n", nouveau_tv_disable); 1370 DRM_DEBUG_DRIVER("... ignorelid : %d\n", nouveau_ignorelid); 1371 DRM_DEBUG_DRIVER("... duallink : %d\n", nouveau_duallink); 1372 DRM_DEBUG_DRIVER("... config : %s\n", nouveau_config); 1373 DRM_DEBUG_DRIVER("... debug : %s\n", nouveau_debug); 1374 DRM_DEBUG_DRIVER("... noaccel : %d\n", nouveau_noaccel); 1375 DRM_DEBUG_DRIVER("... modeset : %d\n", nouveau_modeset); 1376 DRM_DEBUG_DRIVER("... runpm : %d\n", nouveau_runtime_pm); 1377 DRM_DEBUG_DRIVER("... vram_pushbuf : %d\n", nouveau_vram_pushbuf); 1378 DRM_DEBUG_DRIVER("... hdmimhz : %d\n", nouveau_hdmimhz); 1379 } 1380 1381 static const struct dev_pm_ops nouveau_pm_ops = { 1382 .suspend = nouveau_pmops_suspend, 1383 .resume = nouveau_pmops_resume, 1384 .freeze = nouveau_pmops_freeze, 1385 .thaw = nouveau_pmops_thaw, 1386 .poweroff = nouveau_pmops_freeze, 1387 .restore = nouveau_pmops_resume, 1388 .runtime_suspend = nouveau_pmops_runtime_suspend, 1389 .runtime_resume = nouveau_pmops_runtime_resume, 1390 .runtime_idle = nouveau_pmops_runtime_idle, 1391 }; 1392 1393 static struct pci_driver 1394 nouveau_drm_pci_driver = { 1395 .name = "nouveau", 1396 .id_table = nouveau_drm_pci_table, 1397 .probe = nouveau_drm_probe, 1398 .remove = nouveau_drm_remove, 1399 .driver.pm = &nouveau_pm_ops, 1400 }; 1401 1402 struct drm_device * 1403 nouveau_platform_device_create(const struct nvkm_device_tegra_func *func, 1404 struct platform_device *pdev, 1405 struct nvkm_device **pdevice) 1406 { 1407 struct nouveau_drm *drm; 1408 int err; 1409 1410 err = nvkm_device_tegra_new(func, pdev, nouveau_config, nouveau_debug, pdevice); 1411 if (err) 1412 goto err_free; 1413 1414 drm = nouveau_drm_device_new(&driver_platform, &pdev->dev, *pdevice); 1415 if (IS_ERR(drm)) { 1416 err = PTR_ERR(drm); 1417 goto err_free; 1418 } 1419 1420 err = nouveau_drm_device_init(drm); 1421 if (err) 1422 goto err_put; 1423 1424 return drm->dev; 1425 1426 err_put: 1427 nouveau_drm_device_del(drm); 1428 err_free: 1429 nvkm_device_del(pdevice); 1430 1431 return ERR_PTR(err); 1432 } 1433 1434 static int __init 1435 nouveau_drm_init(void) 1436 { 1437 int ret; 1438 1439 driver_pci = driver_stub; 1440 driver_platform = driver_stub; 1441 1442 nouveau_display_options(); 1443 1444 if (nouveau_modeset == -1) { 1445 if (drm_firmware_drivers_only()) 1446 nouveau_modeset = 0; 1447 } 1448 1449 if (!nouveau_modeset) 1450 return 0; 1451 1452 ret = nouveau_module_debugfs_init(); 1453 if (ret) 1454 return ret; 1455 1456 #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER 1457 platform_driver_register(&nouveau_platform_driver); 1458 #endif 1459 1460 nouveau_register_dsm_handler(); 1461 nouveau_backlight_ctor(); 1462 1463 #ifdef CONFIG_PCI 1464 ret = pci_register_driver(&nouveau_drm_pci_driver); 1465 if (ret) { 1466 nouveau_module_debugfs_fini(); 1467 return ret; 1468 } 1469 #endif 1470 1471 return 0; 1472 } 1473 1474 static void __exit 1475 nouveau_drm_exit(void) 1476 { 1477 if (!nouveau_modeset) 1478 return; 1479 1480 #ifdef CONFIG_PCI 1481 pci_unregister_driver(&nouveau_drm_pci_driver); 1482 #endif 1483 nouveau_backlight_dtor(); 1484 nouveau_unregister_dsm_handler(); 1485 1486 #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER 1487 platform_driver_unregister(&nouveau_platform_driver); 1488 #endif 1489 if (IS_ENABLED(CONFIG_DRM_NOUVEAU_SVM)) 1490 mmu_notifier_synchronize(); 1491 1492 #ifdef CONFIG_DEBUG_FS 1493 nvif_log_shutdown(&gsp_logs); 1494 #endif 1495 1496 nouveau_module_debugfs_fini(); 1497 } 1498 1499 module_init(nouveau_drm_init); 1500 module_exit(nouveau_drm_exit); 1501 1502 MODULE_DEVICE_TABLE(pci, nouveau_drm_pci_table); 1503 MODULE_AUTHOR(DRIVER_AUTHOR); 1504 MODULE_DESCRIPTION(DRIVER_DESC); 1505 MODULE_LICENSE("GPL and additional rights"); 1506