1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 25 #include <linux/console.h> 26 #include <linux/delay.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/vga_switcheroo.h> 31 #include <linux/mmu_notifier.h> 32 33 #include <drm/drm_aperture.h> 34 #include <drm/drm_crtc_helper.h> 35 #include <drm/drm_gem_ttm_helper.h> 36 #include <drm/drm_ioctl.h> 37 #include <drm/drm_vblank.h> 38 39 #include <core/gpuobj.h> 40 #include <core/option.h> 41 #include <core/pci.h> 42 #include <core/tegra.h> 43 44 #include <nvif/driver.h> 45 #include <nvif/fifo.h> 46 #include <nvif/push006c.h> 47 #include <nvif/user.h> 48 49 #include <nvif/class.h> 50 #include <nvif/cl0002.h> 51 #include <nvif/cla06f.h> 52 53 #include "nouveau_drv.h" 54 #include "nouveau_dma.h" 55 #include "nouveau_ttm.h" 56 #include "nouveau_gem.h" 57 #include "nouveau_vga.h" 58 #include "nouveau_led.h" 59 #include "nouveau_hwmon.h" 60 #include "nouveau_acpi.h" 61 #include "nouveau_bios.h" 62 #include "nouveau_ioctl.h" 63 #include "nouveau_abi16.h" 64 #include "nouveau_fbcon.h" 65 #include "nouveau_fence.h" 66 #include "nouveau_debugfs.h" 67 #include "nouveau_usif.h" 68 #include "nouveau_connector.h" 69 #include "nouveau_platform.h" 70 #include "nouveau_svm.h" 71 #include "nouveau_dmem.h" 72 73 MODULE_PARM_DESC(config, "option string to pass to driver core"); 74 static char *nouveau_config; 75 module_param_named(config, nouveau_config, charp, 0400); 76 77 MODULE_PARM_DESC(debug, "debug string to pass to driver core"); 78 static char *nouveau_debug; 79 module_param_named(debug, nouveau_debug, charp, 0400); 80 81 MODULE_PARM_DESC(noaccel, "disable kernel/abi16 acceleration"); 82 static int nouveau_noaccel = 0; 83 module_param_named(noaccel, nouveau_noaccel, int, 0400); 84 85 MODULE_PARM_DESC(modeset, "enable driver (default: auto, " 86 "0 = disabled, 1 = enabled, 2 = headless)"); 87 int nouveau_modeset = -1; 88 module_param_named(modeset, nouveau_modeset, int, 0400); 89 90 MODULE_PARM_DESC(atomic, "Expose atomic ioctl (default: disabled)"); 91 static int nouveau_atomic = 0; 92 module_param_named(atomic, nouveau_atomic, int, 0400); 93 94 MODULE_PARM_DESC(runpm, "disable (0), force enable (1), optimus only default (-1)"); 95 static int nouveau_runtime_pm = -1; 96 module_param_named(runpm, nouveau_runtime_pm, int, 0400); 97 98 static struct drm_driver driver_stub; 99 static struct drm_driver driver_pci; 100 static struct drm_driver driver_platform; 101 102 static u64 103 nouveau_pci_name(struct pci_dev *pdev) 104 { 105 u64 name = (u64)pci_domain_nr(pdev->bus) << 32; 106 name |= pdev->bus->number << 16; 107 name |= PCI_SLOT(pdev->devfn) << 8; 108 return name | PCI_FUNC(pdev->devfn); 109 } 110 111 static u64 112 nouveau_platform_name(struct platform_device *platformdev) 113 { 114 return platformdev->id; 115 } 116 117 static u64 118 nouveau_name(struct drm_device *dev) 119 { 120 if (dev_is_pci(dev->dev)) 121 return nouveau_pci_name(to_pci_dev(dev->dev)); 122 else 123 return nouveau_platform_name(to_platform_device(dev->dev)); 124 } 125 126 static inline bool 127 nouveau_cli_work_ready(struct dma_fence *fence) 128 { 129 if (!dma_fence_is_signaled(fence)) 130 return false; 131 dma_fence_put(fence); 132 return true; 133 } 134 135 static void 136 nouveau_cli_work(struct work_struct *w) 137 { 138 struct nouveau_cli *cli = container_of(w, typeof(*cli), work); 139 struct nouveau_cli_work *work, *wtmp; 140 mutex_lock(&cli->lock); 141 list_for_each_entry_safe(work, wtmp, &cli->worker, head) { 142 if (!work->fence || nouveau_cli_work_ready(work->fence)) { 143 list_del(&work->head); 144 work->func(work); 145 } 146 } 147 mutex_unlock(&cli->lock); 148 } 149 150 static void 151 nouveau_cli_work_fence(struct dma_fence *fence, struct dma_fence_cb *cb) 152 { 153 struct nouveau_cli_work *work = container_of(cb, typeof(*work), cb); 154 schedule_work(&work->cli->work); 155 } 156 157 void 158 nouveau_cli_work_queue(struct nouveau_cli *cli, struct dma_fence *fence, 159 struct nouveau_cli_work *work) 160 { 161 work->fence = dma_fence_get(fence); 162 work->cli = cli; 163 mutex_lock(&cli->lock); 164 list_add_tail(&work->head, &cli->worker); 165 if (dma_fence_add_callback(fence, &work->cb, nouveau_cli_work_fence)) 166 nouveau_cli_work_fence(fence, &work->cb); 167 mutex_unlock(&cli->lock); 168 } 169 170 static void 171 nouveau_cli_fini(struct nouveau_cli *cli) 172 { 173 /* All our channels are dead now, which means all the fences they 174 * own are signalled, and all callback functions have been called. 175 * 176 * So, after flushing the workqueue, there should be nothing left. 177 */ 178 flush_work(&cli->work); 179 WARN_ON(!list_empty(&cli->worker)); 180 181 usif_client_fini(cli); 182 nouveau_vmm_fini(&cli->svm); 183 nouveau_vmm_fini(&cli->vmm); 184 nvif_mmu_dtor(&cli->mmu); 185 nvif_device_dtor(&cli->device); 186 mutex_lock(&cli->drm->master.lock); 187 nvif_client_dtor(&cli->base); 188 mutex_unlock(&cli->drm->master.lock); 189 } 190 191 static int 192 nouveau_cli_init(struct nouveau_drm *drm, const char *sname, 193 struct nouveau_cli *cli) 194 { 195 static const struct nvif_mclass 196 mems[] = { 197 { NVIF_CLASS_MEM_GF100, -1 }, 198 { NVIF_CLASS_MEM_NV50 , -1 }, 199 { NVIF_CLASS_MEM_NV04 , -1 }, 200 {} 201 }; 202 static const struct nvif_mclass 203 mmus[] = { 204 { NVIF_CLASS_MMU_GF100, -1 }, 205 { NVIF_CLASS_MMU_NV50 , -1 }, 206 { NVIF_CLASS_MMU_NV04 , -1 }, 207 {} 208 }; 209 static const struct nvif_mclass 210 vmms[] = { 211 { NVIF_CLASS_VMM_GP100, -1 }, 212 { NVIF_CLASS_VMM_GM200, -1 }, 213 { NVIF_CLASS_VMM_GF100, -1 }, 214 { NVIF_CLASS_VMM_NV50 , -1 }, 215 { NVIF_CLASS_VMM_NV04 , -1 }, 216 {} 217 }; 218 u64 device = nouveau_name(drm->dev); 219 int ret; 220 221 snprintf(cli->name, sizeof(cli->name), "%s", sname); 222 cli->drm = drm; 223 mutex_init(&cli->mutex); 224 usif_client_init(cli); 225 226 INIT_WORK(&cli->work, nouveau_cli_work); 227 INIT_LIST_HEAD(&cli->worker); 228 mutex_init(&cli->lock); 229 230 if (cli == &drm->master) { 231 ret = nvif_driver_init(NULL, nouveau_config, nouveau_debug, 232 cli->name, device, &cli->base); 233 } else { 234 mutex_lock(&drm->master.lock); 235 ret = nvif_client_ctor(&drm->master.base, cli->name, device, 236 &cli->base); 237 mutex_unlock(&drm->master.lock); 238 } 239 if (ret) { 240 NV_PRINTK(err, cli, "Client allocation failed: %d\n", ret); 241 goto done; 242 } 243 244 ret = nvif_device_ctor(&cli->base.object, "drmDevice", 0, NV_DEVICE, 245 &(struct nv_device_v0) { 246 .device = ~0, 247 }, sizeof(struct nv_device_v0), 248 &cli->device); 249 if (ret) { 250 NV_PRINTK(err, cli, "Device allocation failed: %d\n", ret); 251 goto done; 252 } 253 254 ret = nvif_mclass(&cli->device.object, mmus); 255 if (ret < 0) { 256 NV_PRINTK(err, cli, "No supported MMU class\n"); 257 goto done; 258 } 259 260 ret = nvif_mmu_ctor(&cli->device.object, "drmMmu", mmus[ret].oclass, 261 &cli->mmu); 262 if (ret) { 263 NV_PRINTK(err, cli, "MMU allocation failed: %d\n", ret); 264 goto done; 265 } 266 267 ret = nvif_mclass(&cli->mmu.object, vmms); 268 if (ret < 0) { 269 NV_PRINTK(err, cli, "No supported VMM class\n"); 270 goto done; 271 } 272 273 ret = nouveau_vmm_init(cli, vmms[ret].oclass, &cli->vmm); 274 if (ret) { 275 NV_PRINTK(err, cli, "VMM allocation failed: %d\n", ret); 276 goto done; 277 } 278 279 ret = nvif_mclass(&cli->mmu.object, mems); 280 if (ret < 0) { 281 NV_PRINTK(err, cli, "No supported MEM class\n"); 282 goto done; 283 } 284 285 cli->mem = &mems[ret]; 286 return 0; 287 done: 288 if (ret) 289 nouveau_cli_fini(cli); 290 return ret; 291 } 292 293 static void 294 nouveau_accel_ce_fini(struct nouveau_drm *drm) 295 { 296 nouveau_channel_idle(drm->cechan); 297 nvif_object_dtor(&drm->ttm.copy); 298 nouveau_channel_del(&drm->cechan); 299 } 300 301 static void 302 nouveau_accel_ce_init(struct nouveau_drm *drm) 303 { 304 struct nvif_device *device = &drm->client.device; 305 int ret = 0; 306 307 /* Allocate channel that has access to a (preferably async) copy 308 * engine, to use for TTM buffer moves. 309 */ 310 if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) { 311 ret = nouveau_channel_new(drm, device, 312 nvif_fifo_runlist_ce(device), 0, 313 true, &drm->cechan); 314 } else 315 if (device->info.chipset >= 0xa3 && 316 device->info.chipset != 0xaa && 317 device->info.chipset != 0xac) { 318 /* Prior to Kepler, there's only a single runlist, so all 319 * engines can be accessed from any channel. 320 * 321 * We still want to use a separate channel though. 322 */ 323 ret = nouveau_channel_new(drm, device, NvDmaFB, NvDmaTT, false, 324 &drm->cechan); 325 } 326 327 if (ret) 328 NV_ERROR(drm, "failed to create ce channel, %d\n", ret); 329 } 330 331 static void 332 nouveau_accel_gr_fini(struct nouveau_drm *drm) 333 { 334 nouveau_channel_idle(drm->channel); 335 nvif_object_dtor(&drm->ntfy); 336 nvkm_gpuobj_del(&drm->notify); 337 nouveau_channel_del(&drm->channel); 338 } 339 340 static void 341 nouveau_accel_gr_init(struct nouveau_drm *drm) 342 { 343 struct nvif_device *device = &drm->client.device; 344 u32 arg0, arg1; 345 int ret; 346 347 /* Allocate channel that has access to the graphics engine. */ 348 if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) { 349 arg0 = nvif_fifo_runlist(device, NV_DEVICE_HOST_RUNLIST_ENGINES_GR); 350 arg1 = 1; 351 } else { 352 arg0 = NvDmaFB; 353 arg1 = NvDmaTT; 354 } 355 356 ret = nouveau_channel_new(drm, device, arg0, arg1, false, 357 &drm->channel); 358 if (ret) { 359 NV_ERROR(drm, "failed to create kernel channel, %d\n", ret); 360 nouveau_accel_gr_fini(drm); 361 return; 362 } 363 364 /* A SW class is used on pre-NV50 HW to assist with handling the 365 * synchronisation of page flips, as well as to implement fences 366 * on TNT/TNT2 HW that lacks any kind of support in host. 367 */ 368 if (!drm->channel->nvsw.client && device->info.family < NV_DEVICE_INFO_V0_TESLA) { 369 ret = nvif_object_ctor(&drm->channel->user, "drmNvsw", 370 NVDRM_NVSW, nouveau_abi16_swclass(drm), 371 NULL, 0, &drm->channel->nvsw); 372 if (ret == 0) { 373 struct nvif_push *push = drm->channel->chan.push; 374 ret = PUSH_WAIT(push, 2); 375 if (ret == 0) 376 PUSH_NVSQ(push, NV_SW, 0x0000, drm->channel->nvsw.handle); 377 } 378 379 if (ret) { 380 NV_ERROR(drm, "failed to allocate sw class, %d\n", ret); 381 nouveau_accel_gr_fini(drm); 382 return; 383 } 384 } 385 386 /* NvMemoryToMemoryFormat requires a notifier ctxdma for some reason, 387 * even if notification is never requested, so, allocate a ctxdma on 388 * any GPU where it's possible we'll end up using M2MF for BO moves. 389 */ 390 if (device->info.family < NV_DEVICE_INFO_V0_FERMI) { 391 ret = nvkm_gpuobj_new(nvxx_device(device), 32, 0, false, NULL, 392 &drm->notify); 393 if (ret) { 394 NV_ERROR(drm, "failed to allocate notifier, %d\n", ret); 395 nouveau_accel_gr_fini(drm); 396 return; 397 } 398 399 ret = nvif_object_ctor(&drm->channel->user, "drmM2mfNtfy", 400 NvNotify0, NV_DMA_IN_MEMORY, 401 &(struct nv_dma_v0) { 402 .target = NV_DMA_V0_TARGET_VRAM, 403 .access = NV_DMA_V0_ACCESS_RDWR, 404 .start = drm->notify->addr, 405 .limit = drm->notify->addr + 31 406 }, sizeof(struct nv_dma_v0), 407 &drm->ntfy); 408 if (ret) { 409 nouveau_accel_gr_fini(drm); 410 return; 411 } 412 } 413 } 414 415 static void 416 nouveau_accel_fini(struct nouveau_drm *drm) 417 { 418 nouveau_accel_ce_fini(drm); 419 nouveau_accel_gr_fini(drm); 420 if (drm->fence) 421 nouveau_fence(drm)->dtor(drm); 422 } 423 424 static void 425 nouveau_accel_init(struct nouveau_drm *drm) 426 { 427 struct nvif_device *device = &drm->client.device; 428 struct nvif_sclass *sclass; 429 int ret, i, n; 430 431 if (nouveau_noaccel) 432 return; 433 434 /* Initialise global support for channels, and synchronisation. */ 435 ret = nouveau_channels_init(drm); 436 if (ret) 437 return; 438 439 /*XXX: this is crap, but the fence/channel stuff is a little 440 * backwards in some places. this will be fixed. 441 */ 442 ret = n = nvif_object_sclass_get(&device->object, &sclass); 443 if (ret < 0) 444 return; 445 446 for (ret = -ENOSYS, i = 0; i < n; i++) { 447 switch (sclass[i].oclass) { 448 case NV03_CHANNEL_DMA: 449 ret = nv04_fence_create(drm); 450 break; 451 case NV10_CHANNEL_DMA: 452 ret = nv10_fence_create(drm); 453 break; 454 case NV17_CHANNEL_DMA: 455 case NV40_CHANNEL_DMA: 456 ret = nv17_fence_create(drm); 457 break; 458 case NV50_CHANNEL_GPFIFO: 459 ret = nv50_fence_create(drm); 460 break; 461 case G82_CHANNEL_GPFIFO: 462 ret = nv84_fence_create(drm); 463 break; 464 case FERMI_CHANNEL_GPFIFO: 465 case KEPLER_CHANNEL_GPFIFO_A: 466 case KEPLER_CHANNEL_GPFIFO_B: 467 case MAXWELL_CHANNEL_GPFIFO_A: 468 case PASCAL_CHANNEL_GPFIFO_A: 469 case VOLTA_CHANNEL_GPFIFO_A: 470 case TURING_CHANNEL_GPFIFO_A: 471 ret = nvc0_fence_create(drm); 472 break; 473 default: 474 break; 475 } 476 } 477 478 nvif_object_sclass_put(&sclass); 479 if (ret) { 480 NV_ERROR(drm, "failed to initialise sync subsystem, %d\n", ret); 481 nouveau_accel_fini(drm); 482 return; 483 } 484 485 /* Volta requires access to a doorbell register for kickoff. */ 486 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_VOLTA) { 487 ret = nvif_user_ctor(device, "drmUsermode"); 488 if (ret) 489 return; 490 } 491 492 /* Allocate channels we need to support various functions. */ 493 nouveau_accel_gr_init(drm); 494 nouveau_accel_ce_init(drm); 495 496 /* Initialise accelerated TTM buffer moves. */ 497 nouveau_bo_move_init(drm); 498 } 499 500 static void __printf(2, 3) 501 nouveau_drm_errorf(struct nvif_object *object, const char *fmt, ...) 502 { 503 struct nouveau_drm *drm = container_of(object->parent, typeof(*drm), parent); 504 struct va_format vaf; 505 va_list va; 506 507 va_start(va, fmt); 508 vaf.fmt = fmt; 509 vaf.va = &va; 510 NV_ERROR(drm, "%pV", &vaf); 511 va_end(va); 512 } 513 514 static void __printf(2, 3) 515 nouveau_drm_debugf(struct nvif_object *object, const char *fmt, ...) 516 { 517 struct nouveau_drm *drm = container_of(object->parent, typeof(*drm), parent); 518 struct va_format vaf; 519 va_list va; 520 521 va_start(va, fmt); 522 vaf.fmt = fmt; 523 vaf.va = &va; 524 NV_DEBUG(drm, "%pV", &vaf); 525 va_end(va); 526 } 527 528 static const struct nvif_parent_func 529 nouveau_parent = { 530 .debugf = nouveau_drm_debugf, 531 .errorf = nouveau_drm_errorf, 532 }; 533 534 static int 535 nouveau_drm_device_init(struct drm_device *dev) 536 { 537 struct nouveau_drm *drm; 538 int ret; 539 540 if (!(drm = kzalloc(sizeof(*drm), GFP_KERNEL))) 541 return -ENOMEM; 542 dev->dev_private = drm; 543 drm->dev = dev; 544 545 nvif_parent_ctor(&nouveau_parent, &drm->parent); 546 drm->master.base.object.parent = &drm->parent; 547 548 ret = nouveau_cli_init(drm, "DRM-master", &drm->master); 549 if (ret) 550 goto fail_alloc; 551 552 ret = nouveau_cli_init(drm, "DRM", &drm->client); 553 if (ret) 554 goto fail_master; 555 556 dev->irq_enabled = true; 557 558 nvxx_client(&drm->client.base)->debug = 559 nvkm_dbgopt(nouveau_debug, "DRM"); 560 561 INIT_LIST_HEAD(&drm->clients); 562 spin_lock_init(&drm->tile.lock); 563 564 /* workaround an odd issue on nvc1 by disabling the device's 565 * nosnoop capability. hopefully won't cause issues until a 566 * better fix is found - assuming there is one... 567 */ 568 if (drm->client.device.info.chipset == 0xc1) 569 nvif_mask(&drm->client.device.object, 0x00088080, 0x00000800, 0x00000000); 570 571 nouveau_vga_init(drm); 572 573 ret = nouveau_ttm_init(drm); 574 if (ret) 575 goto fail_ttm; 576 577 ret = nouveau_bios_init(dev); 578 if (ret) 579 goto fail_bios; 580 581 nouveau_accel_init(drm); 582 583 ret = nouveau_display_create(dev); 584 if (ret) 585 goto fail_dispctor; 586 587 if (dev->mode_config.num_crtc) { 588 ret = nouveau_display_init(dev, false, false); 589 if (ret) 590 goto fail_dispinit; 591 } 592 593 nouveau_debugfs_init(drm); 594 nouveau_hwmon_init(dev); 595 nouveau_svm_init(drm); 596 nouveau_dmem_init(drm); 597 nouveau_fbcon_init(dev); 598 nouveau_led_init(dev); 599 600 if (nouveau_pmops_runtime()) { 601 pm_runtime_use_autosuspend(dev->dev); 602 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 603 pm_runtime_set_active(dev->dev); 604 pm_runtime_allow(dev->dev); 605 pm_runtime_mark_last_busy(dev->dev); 606 pm_runtime_put(dev->dev); 607 } 608 609 return 0; 610 611 fail_dispinit: 612 nouveau_display_destroy(dev); 613 fail_dispctor: 614 nouveau_accel_fini(drm); 615 nouveau_bios_takedown(dev); 616 fail_bios: 617 nouveau_ttm_fini(drm); 618 fail_ttm: 619 nouveau_vga_fini(drm); 620 nouveau_cli_fini(&drm->client); 621 fail_master: 622 nouveau_cli_fini(&drm->master); 623 fail_alloc: 624 nvif_parent_dtor(&drm->parent); 625 kfree(drm); 626 return ret; 627 } 628 629 static void 630 nouveau_drm_device_fini(struct drm_device *dev) 631 { 632 struct nouveau_drm *drm = nouveau_drm(dev); 633 634 if (nouveau_pmops_runtime()) { 635 pm_runtime_get_sync(dev->dev); 636 pm_runtime_forbid(dev->dev); 637 } 638 639 nouveau_led_fini(dev); 640 nouveau_fbcon_fini(dev); 641 nouveau_dmem_fini(drm); 642 nouveau_svm_fini(drm); 643 nouveau_hwmon_fini(dev); 644 nouveau_debugfs_fini(drm); 645 646 if (dev->mode_config.num_crtc) 647 nouveau_display_fini(dev, false, false); 648 nouveau_display_destroy(dev); 649 650 nouveau_accel_fini(drm); 651 nouveau_bios_takedown(dev); 652 653 nouveau_ttm_fini(drm); 654 nouveau_vga_fini(drm); 655 656 nouveau_cli_fini(&drm->client); 657 nouveau_cli_fini(&drm->master); 658 nvif_parent_dtor(&drm->parent); 659 kfree(drm); 660 } 661 662 /* 663 * On some Intel PCIe bridge controllers doing a 664 * D0 -> D3hot -> D3cold -> D0 sequence causes Nvidia GPUs to not reappear. 665 * Skipping the intermediate D3hot step seems to make it work again. This is 666 * probably caused by not meeting the expectation the involved AML code has 667 * when the GPU is put into D3hot state before invoking it. 668 * 669 * This leads to various manifestations of this issue: 670 * - AML code execution to power on the GPU hits an infinite loop (as the 671 * code waits on device memory to change). 672 * - kernel crashes, as all PCI reads return -1, which most code isn't able 673 * to handle well enough. 674 * 675 * In all cases dmesg will contain at least one line like this: 676 * 'nouveau 0000:01:00.0: Refused to change power state, currently in D3' 677 * followed by a lot of nouveau timeouts. 678 * 679 * In the \_SB.PCI0.PEG0.PG00._OFF code deeper down writes bit 0x80 to the not 680 * documented PCI config space register 0x248 of the Intel PCIe bridge 681 * controller (0x1901) in order to change the state of the PCIe link between 682 * the PCIe port and the GPU. There are alternative code paths using other 683 * registers, which seem to work fine (executed pre Windows 8): 684 * - 0xbc bit 0x20 (publicly available documentation claims 'reserved') 685 * - 0xb0 bit 0x10 (link disable) 686 * Changing the conditions inside the firmware by poking into the relevant 687 * addresses does resolve the issue, but it seemed to be ACPI private memory 688 * and not any device accessible memory at all, so there is no portable way of 689 * changing the conditions. 690 * On a XPS 9560 that means bits [0,3] on \CPEX need to be cleared. 691 * 692 * The only systems where this behavior can be seen are hybrid graphics laptops 693 * with a secondary Nvidia Maxwell, Pascal or Turing GPU. It's unclear whether 694 * this issue only occurs in combination with listed Intel PCIe bridge 695 * controllers and the mentioned GPUs or other devices as well. 696 * 697 * documentation on the PCIe bridge controller can be found in the 698 * "7th Generation Intel® Processor Families for H Platforms Datasheet Volume 2" 699 * Section "12 PCI Express* Controller (x16) Registers" 700 */ 701 702 static void quirk_broken_nv_runpm(struct pci_dev *pdev) 703 { 704 struct drm_device *dev = pci_get_drvdata(pdev); 705 struct nouveau_drm *drm = nouveau_drm(dev); 706 struct pci_dev *bridge = pci_upstream_bridge(pdev); 707 708 if (!bridge || bridge->vendor != PCI_VENDOR_ID_INTEL) 709 return; 710 711 switch (bridge->device) { 712 case 0x1901: 713 drm->old_pm_cap = pdev->pm_cap; 714 pdev->pm_cap = 0; 715 NV_INFO(drm, "Disabling PCI power management to avoid bug\n"); 716 break; 717 } 718 } 719 720 static int nouveau_drm_probe(struct pci_dev *pdev, 721 const struct pci_device_id *pent) 722 { 723 struct nvkm_device *device; 724 struct drm_device *drm_dev; 725 int ret; 726 727 if (vga_switcheroo_client_probe_defer(pdev)) 728 return -EPROBE_DEFER; 729 730 /* We need to check that the chipset is supported before booting 731 * fbdev off the hardware, as there's no way to put it back. 732 */ 733 ret = nvkm_device_pci_new(pdev, nouveau_config, "error", 734 true, false, 0, &device); 735 if (ret) 736 return ret; 737 738 nvkm_device_del(&device); 739 740 /* Remove conflicting drivers (vesafb, efifb etc). */ 741 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, "nouveaufb"); 742 if (ret) 743 return ret; 744 745 ret = nvkm_device_pci_new(pdev, nouveau_config, nouveau_debug, 746 true, true, ~0ULL, &device); 747 if (ret) 748 return ret; 749 750 pci_set_master(pdev); 751 752 if (nouveau_atomic) 753 driver_pci.driver_features |= DRIVER_ATOMIC; 754 755 drm_dev = drm_dev_alloc(&driver_pci, &pdev->dev); 756 if (IS_ERR(drm_dev)) { 757 ret = PTR_ERR(drm_dev); 758 goto fail_nvkm; 759 } 760 761 ret = pci_enable_device(pdev); 762 if (ret) 763 goto fail_drm; 764 765 pci_set_drvdata(pdev, drm_dev); 766 767 ret = nouveau_drm_device_init(drm_dev); 768 if (ret) 769 goto fail_pci; 770 771 ret = drm_dev_register(drm_dev, pent->driver_data); 772 if (ret) 773 goto fail_drm_dev_init; 774 775 quirk_broken_nv_runpm(pdev); 776 return 0; 777 778 fail_drm_dev_init: 779 nouveau_drm_device_fini(drm_dev); 780 fail_pci: 781 pci_disable_device(pdev); 782 fail_drm: 783 drm_dev_put(drm_dev); 784 fail_nvkm: 785 nvkm_device_del(&device); 786 return ret; 787 } 788 789 void 790 nouveau_drm_device_remove(struct drm_device *dev) 791 { 792 struct nouveau_drm *drm = nouveau_drm(dev); 793 struct nvkm_client *client; 794 struct nvkm_device *device; 795 796 drm_dev_unregister(dev); 797 798 dev->irq_enabled = false; 799 client = nvxx_client(&drm->client.base); 800 device = nvkm_device_find(client->device); 801 802 nouveau_drm_device_fini(dev); 803 drm_dev_put(dev); 804 nvkm_device_del(&device); 805 } 806 807 static void 808 nouveau_drm_remove(struct pci_dev *pdev) 809 { 810 struct drm_device *dev = pci_get_drvdata(pdev); 811 struct nouveau_drm *drm = nouveau_drm(dev); 812 813 /* revert our workaround */ 814 if (drm->old_pm_cap) 815 pdev->pm_cap = drm->old_pm_cap; 816 nouveau_drm_device_remove(dev); 817 pci_disable_device(pdev); 818 } 819 820 static int 821 nouveau_do_suspend(struct drm_device *dev, bool runtime) 822 { 823 struct nouveau_drm *drm = nouveau_drm(dev); 824 struct ttm_resource_manager *man; 825 int ret; 826 827 nouveau_svm_suspend(drm); 828 nouveau_dmem_suspend(drm); 829 nouveau_led_suspend(dev); 830 831 if (dev->mode_config.num_crtc) { 832 NV_DEBUG(drm, "suspending console...\n"); 833 nouveau_fbcon_set_suspend(dev, 1); 834 NV_DEBUG(drm, "suspending display...\n"); 835 ret = nouveau_display_suspend(dev, runtime); 836 if (ret) 837 return ret; 838 } 839 840 NV_DEBUG(drm, "evicting buffers...\n"); 841 842 man = ttm_manager_type(&drm->ttm.bdev, TTM_PL_VRAM); 843 ttm_resource_manager_evict_all(&drm->ttm.bdev, man); 844 845 NV_DEBUG(drm, "waiting for kernel channels to go idle...\n"); 846 if (drm->cechan) { 847 ret = nouveau_channel_idle(drm->cechan); 848 if (ret) 849 goto fail_display; 850 } 851 852 if (drm->channel) { 853 ret = nouveau_channel_idle(drm->channel); 854 if (ret) 855 goto fail_display; 856 } 857 858 NV_DEBUG(drm, "suspending fence...\n"); 859 if (drm->fence && nouveau_fence(drm)->suspend) { 860 if (!nouveau_fence(drm)->suspend(drm)) { 861 ret = -ENOMEM; 862 goto fail_display; 863 } 864 } 865 866 NV_DEBUG(drm, "suspending object tree...\n"); 867 ret = nvif_client_suspend(&drm->master.base); 868 if (ret) 869 goto fail_client; 870 871 return 0; 872 873 fail_client: 874 if (drm->fence && nouveau_fence(drm)->resume) 875 nouveau_fence(drm)->resume(drm); 876 877 fail_display: 878 if (dev->mode_config.num_crtc) { 879 NV_DEBUG(drm, "resuming display...\n"); 880 nouveau_display_resume(dev, runtime); 881 } 882 return ret; 883 } 884 885 static int 886 nouveau_do_resume(struct drm_device *dev, bool runtime) 887 { 888 int ret = 0; 889 struct nouveau_drm *drm = nouveau_drm(dev); 890 891 NV_DEBUG(drm, "resuming object tree...\n"); 892 ret = nvif_client_resume(&drm->master.base); 893 if (ret) { 894 NV_ERROR(drm, "Client resume failed with error: %d\n", ret); 895 return ret; 896 } 897 898 NV_DEBUG(drm, "resuming fence...\n"); 899 if (drm->fence && nouveau_fence(drm)->resume) 900 nouveau_fence(drm)->resume(drm); 901 902 nouveau_run_vbios_init(dev); 903 904 if (dev->mode_config.num_crtc) { 905 NV_DEBUG(drm, "resuming display...\n"); 906 nouveau_display_resume(dev, runtime); 907 NV_DEBUG(drm, "resuming console...\n"); 908 nouveau_fbcon_set_suspend(dev, 0); 909 } 910 911 nouveau_led_resume(dev); 912 nouveau_dmem_resume(drm); 913 nouveau_svm_resume(drm); 914 return 0; 915 } 916 917 int 918 nouveau_pmops_suspend(struct device *dev) 919 { 920 struct pci_dev *pdev = to_pci_dev(dev); 921 struct drm_device *drm_dev = pci_get_drvdata(pdev); 922 int ret; 923 924 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF || 925 drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF) 926 return 0; 927 928 ret = nouveau_do_suspend(drm_dev, false); 929 if (ret) 930 return ret; 931 932 pci_save_state(pdev); 933 pci_disable_device(pdev); 934 pci_set_power_state(pdev, PCI_D3hot); 935 udelay(200); 936 return 0; 937 } 938 939 int 940 nouveau_pmops_resume(struct device *dev) 941 { 942 struct pci_dev *pdev = to_pci_dev(dev); 943 struct drm_device *drm_dev = pci_get_drvdata(pdev); 944 int ret; 945 946 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF || 947 drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF) 948 return 0; 949 950 pci_set_power_state(pdev, PCI_D0); 951 pci_restore_state(pdev); 952 ret = pci_enable_device(pdev); 953 if (ret) 954 return ret; 955 pci_set_master(pdev); 956 957 ret = nouveau_do_resume(drm_dev, false); 958 959 /* Monitors may have been connected / disconnected during suspend */ 960 nouveau_display_hpd_resume(drm_dev); 961 962 return ret; 963 } 964 965 static int 966 nouveau_pmops_freeze(struct device *dev) 967 { 968 struct pci_dev *pdev = to_pci_dev(dev); 969 struct drm_device *drm_dev = pci_get_drvdata(pdev); 970 return nouveau_do_suspend(drm_dev, false); 971 } 972 973 static int 974 nouveau_pmops_thaw(struct device *dev) 975 { 976 struct pci_dev *pdev = to_pci_dev(dev); 977 struct drm_device *drm_dev = pci_get_drvdata(pdev); 978 return nouveau_do_resume(drm_dev, false); 979 } 980 981 bool 982 nouveau_pmops_runtime(void) 983 { 984 if (nouveau_runtime_pm == -1) 985 return nouveau_is_optimus() || nouveau_is_v1_dsm(); 986 return nouveau_runtime_pm == 1; 987 } 988 989 static int 990 nouveau_pmops_runtime_suspend(struct device *dev) 991 { 992 struct pci_dev *pdev = to_pci_dev(dev); 993 struct drm_device *drm_dev = pci_get_drvdata(pdev); 994 int ret; 995 996 if (!nouveau_pmops_runtime()) { 997 pm_runtime_forbid(dev); 998 return -EBUSY; 999 } 1000 1001 nouveau_switcheroo_optimus_dsm(); 1002 ret = nouveau_do_suspend(drm_dev, true); 1003 pci_save_state(pdev); 1004 pci_disable_device(pdev); 1005 pci_ignore_hotplug(pdev); 1006 pci_set_power_state(pdev, PCI_D3cold); 1007 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 1008 return ret; 1009 } 1010 1011 static int 1012 nouveau_pmops_runtime_resume(struct device *dev) 1013 { 1014 struct pci_dev *pdev = to_pci_dev(dev); 1015 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1016 struct nouveau_drm *drm = nouveau_drm(drm_dev); 1017 struct nvif_device *device = &nouveau_drm(drm_dev)->client.device; 1018 int ret; 1019 1020 if (!nouveau_pmops_runtime()) { 1021 pm_runtime_forbid(dev); 1022 return -EBUSY; 1023 } 1024 1025 pci_set_power_state(pdev, PCI_D0); 1026 pci_restore_state(pdev); 1027 ret = pci_enable_device(pdev); 1028 if (ret) 1029 return ret; 1030 pci_set_master(pdev); 1031 1032 ret = nouveau_do_resume(drm_dev, true); 1033 if (ret) { 1034 NV_ERROR(drm, "resume failed with: %d\n", ret); 1035 return ret; 1036 } 1037 1038 /* do magic */ 1039 nvif_mask(&device->object, 0x088488, (1 << 25), (1 << 25)); 1040 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 1041 1042 /* Monitors may have been connected / disconnected during suspend */ 1043 nouveau_display_hpd_resume(drm_dev); 1044 1045 return ret; 1046 } 1047 1048 static int 1049 nouveau_pmops_runtime_idle(struct device *dev) 1050 { 1051 if (!nouveau_pmops_runtime()) { 1052 pm_runtime_forbid(dev); 1053 return -EBUSY; 1054 } 1055 1056 pm_runtime_mark_last_busy(dev); 1057 pm_runtime_autosuspend(dev); 1058 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 1059 return 1; 1060 } 1061 1062 static int 1063 nouveau_drm_open(struct drm_device *dev, struct drm_file *fpriv) 1064 { 1065 struct nouveau_drm *drm = nouveau_drm(dev); 1066 struct nouveau_cli *cli; 1067 char name[32], tmpname[TASK_COMM_LEN]; 1068 int ret; 1069 1070 /* need to bring up power immediately if opening device */ 1071 ret = pm_runtime_get_sync(dev->dev); 1072 if (ret < 0 && ret != -EACCES) { 1073 pm_runtime_put_autosuspend(dev->dev); 1074 return ret; 1075 } 1076 1077 get_task_comm(tmpname, current); 1078 snprintf(name, sizeof(name), "%s[%d]", tmpname, pid_nr(fpriv->pid)); 1079 1080 if (!(cli = kzalloc(sizeof(*cli), GFP_KERNEL))) { 1081 ret = -ENOMEM; 1082 goto done; 1083 } 1084 1085 ret = nouveau_cli_init(drm, name, cli); 1086 if (ret) 1087 goto done; 1088 1089 cli->base.super = false; 1090 1091 fpriv->driver_priv = cli; 1092 1093 mutex_lock(&drm->client.mutex); 1094 list_add(&cli->head, &drm->clients); 1095 mutex_unlock(&drm->client.mutex); 1096 1097 done: 1098 if (ret && cli) { 1099 nouveau_cli_fini(cli); 1100 kfree(cli); 1101 } 1102 1103 pm_runtime_mark_last_busy(dev->dev); 1104 pm_runtime_put_autosuspend(dev->dev); 1105 return ret; 1106 } 1107 1108 static void 1109 nouveau_drm_postclose(struct drm_device *dev, struct drm_file *fpriv) 1110 { 1111 struct nouveau_cli *cli = nouveau_cli(fpriv); 1112 struct nouveau_drm *drm = nouveau_drm(dev); 1113 1114 pm_runtime_get_sync(dev->dev); 1115 1116 mutex_lock(&cli->mutex); 1117 if (cli->abi16) 1118 nouveau_abi16_fini(cli->abi16); 1119 mutex_unlock(&cli->mutex); 1120 1121 mutex_lock(&drm->client.mutex); 1122 list_del(&cli->head); 1123 mutex_unlock(&drm->client.mutex); 1124 1125 nouveau_cli_fini(cli); 1126 kfree(cli); 1127 pm_runtime_mark_last_busy(dev->dev); 1128 pm_runtime_put_autosuspend(dev->dev); 1129 } 1130 1131 static const struct drm_ioctl_desc 1132 nouveau_ioctls[] = { 1133 DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_RENDER_ALLOW), 1134 DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1135 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_RENDER_ALLOW), 1136 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_RENDER_ALLOW), 1137 DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_RENDER_ALLOW), 1138 DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_RENDER_ALLOW), 1139 DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_RENDER_ALLOW), 1140 DRM_IOCTL_DEF_DRV(NOUVEAU_SVM_INIT, nouveau_svmm_init, DRM_RENDER_ALLOW), 1141 DRM_IOCTL_DEF_DRV(NOUVEAU_SVM_BIND, nouveau_svmm_bind, DRM_RENDER_ALLOW), 1142 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_RENDER_ALLOW), 1143 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_RENDER_ALLOW), 1144 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_RENDER_ALLOW), 1145 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_RENDER_ALLOW), 1146 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_RENDER_ALLOW), 1147 }; 1148 1149 long 1150 nouveau_drm_ioctl(struct file *file, unsigned int cmd, unsigned long arg) 1151 { 1152 struct drm_file *filp = file->private_data; 1153 struct drm_device *dev = filp->minor->dev; 1154 long ret; 1155 1156 ret = pm_runtime_get_sync(dev->dev); 1157 if (ret < 0 && ret != -EACCES) { 1158 pm_runtime_put_autosuspend(dev->dev); 1159 return ret; 1160 } 1161 1162 switch (_IOC_NR(cmd) - DRM_COMMAND_BASE) { 1163 case DRM_NOUVEAU_NVIF: 1164 ret = usif_ioctl(filp, (void __user *)arg, _IOC_SIZE(cmd)); 1165 break; 1166 default: 1167 ret = drm_ioctl(file, cmd, arg); 1168 break; 1169 } 1170 1171 pm_runtime_mark_last_busy(dev->dev); 1172 pm_runtime_put_autosuspend(dev->dev); 1173 return ret; 1174 } 1175 1176 static const struct file_operations 1177 nouveau_driver_fops = { 1178 .owner = THIS_MODULE, 1179 .open = drm_open, 1180 .release = drm_release, 1181 .unlocked_ioctl = nouveau_drm_ioctl, 1182 .mmap = drm_gem_mmap, 1183 .poll = drm_poll, 1184 .read = drm_read, 1185 #if defined(CONFIG_COMPAT) 1186 .compat_ioctl = nouveau_compat_ioctl, 1187 #endif 1188 .llseek = noop_llseek, 1189 }; 1190 1191 static struct drm_driver 1192 driver_stub = { 1193 .driver_features = 1194 DRIVER_GEM | DRIVER_MODESET | DRIVER_RENDER 1195 #if defined(CONFIG_NOUVEAU_LEGACY_CTX_SUPPORT) 1196 | DRIVER_KMS_LEGACY_CONTEXT 1197 #endif 1198 , 1199 1200 .open = nouveau_drm_open, 1201 .postclose = nouveau_drm_postclose, 1202 .lastclose = nouveau_vga_lastclose, 1203 1204 #if defined(CONFIG_DEBUG_FS) 1205 .debugfs_init = nouveau_drm_debugfs_init, 1206 #endif 1207 1208 .ioctls = nouveau_ioctls, 1209 .num_ioctls = ARRAY_SIZE(nouveau_ioctls), 1210 .fops = &nouveau_driver_fops, 1211 1212 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 1213 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 1214 .gem_prime_import_sg_table = nouveau_gem_prime_import_sg_table, 1215 .gem_prime_mmap = drm_gem_prime_mmap, 1216 1217 .dumb_create = nouveau_display_dumb_create, 1218 .dumb_map_offset = drm_gem_ttm_dumb_map_offset, 1219 1220 .name = DRIVER_NAME, 1221 .desc = DRIVER_DESC, 1222 #ifdef GIT_REVISION 1223 .date = GIT_REVISION, 1224 #else 1225 .date = DRIVER_DATE, 1226 #endif 1227 .major = DRIVER_MAJOR, 1228 .minor = DRIVER_MINOR, 1229 .patchlevel = DRIVER_PATCHLEVEL, 1230 }; 1231 1232 static struct pci_device_id 1233 nouveau_drm_pci_table[] = { 1234 { 1235 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), 1236 .class = PCI_BASE_CLASS_DISPLAY << 16, 1237 .class_mask = 0xff << 16, 1238 }, 1239 { 1240 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID), 1241 .class = PCI_BASE_CLASS_DISPLAY << 16, 1242 .class_mask = 0xff << 16, 1243 }, 1244 {} 1245 }; 1246 1247 static void nouveau_display_options(void) 1248 { 1249 DRM_DEBUG_DRIVER("Loading Nouveau with parameters:\n"); 1250 1251 DRM_DEBUG_DRIVER("... tv_disable : %d\n", nouveau_tv_disable); 1252 DRM_DEBUG_DRIVER("... ignorelid : %d\n", nouveau_ignorelid); 1253 DRM_DEBUG_DRIVER("... duallink : %d\n", nouveau_duallink); 1254 DRM_DEBUG_DRIVER("... nofbaccel : %d\n", nouveau_nofbaccel); 1255 DRM_DEBUG_DRIVER("... config : %s\n", nouveau_config); 1256 DRM_DEBUG_DRIVER("... debug : %s\n", nouveau_debug); 1257 DRM_DEBUG_DRIVER("... noaccel : %d\n", nouveau_noaccel); 1258 DRM_DEBUG_DRIVER("... modeset : %d\n", nouveau_modeset); 1259 DRM_DEBUG_DRIVER("... runpm : %d\n", nouveau_runtime_pm); 1260 DRM_DEBUG_DRIVER("... vram_pushbuf : %d\n", nouveau_vram_pushbuf); 1261 DRM_DEBUG_DRIVER("... hdmimhz : %d\n", nouveau_hdmimhz); 1262 } 1263 1264 static const struct dev_pm_ops nouveau_pm_ops = { 1265 .suspend = nouveau_pmops_suspend, 1266 .resume = nouveau_pmops_resume, 1267 .freeze = nouveau_pmops_freeze, 1268 .thaw = nouveau_pmops_thaw, 1269 .poweroff = nouveau_pmops_freeze, 1270 .restore = nouveau_pmops_resume, 1271 .runtime_suspend = nouveau_pmops_runtime_suspend, 1272 .runtime_resume = nouveau_pmops_runtime_resume, 1273 .runtime_idle = nouveau_pmops_runtime_idle, 1274 }; 1275 1276 static struct pci_driver 1277 nouveau_drm_pci_driver = { 1278 .name = "nouveau", 1279 .id_table = nouveau_drm_pci_table, 1280 .probe = nouveau_drm_probe, 1281 .remove = nouveau_drm_remove, 1282 .driver.pm = &nouveau_pm_ops, 1283 }; 1284 1285 struct drm_device * 1286 nouveau_platform_device_create(const struct nvkm_device_tegra_func *func, 1287 struct platform_device *pdev, 1288 struct nvkm_device **pdevice) 1289 { 1290 struct drm_device *drm; 1291 int err; 1292 1293 err = nvkm_device_tegra_new(func, pdev, nouveau_config, nouveau_debug, 1294 true, true, ~0ULL, pdevice); 1295 if (err) 1296 goto err_free; 1297 1298 drm = drm_dev_alloc(&driver_platform, &pdev->dev); 1299 if (IS_ERR(drm)) { 1300 err = PTR_ERR(drm); 1301 goto err_free; 1302 } 1303 1304 err = nouveau_drm_device_init(drm); 1305 if (err) 1306 goto err_put; 1307 1308 platform_set_drvdata(pdev, drm); 1309 1310 return drm; 1311 1312 err_put: 1313 drm_dev_put(drm); 1314 err_free: 1315 nvkm_device_del(pdevice); 1316 1317 return ERR_PTR(err); 1318 } 1319 1320 static int __init 1321 nouveau_drm_init(void) 1322 { 1323 driver_pci = driver_stub; 1324 driver_platform = driver_stub; 1325 1326 nouveau_display_options(); 1327 1328 if (nouveau_modeset == -1) { 1329 if (vgacon_text_force()) 1330 nouveau_modeset = 0; 1331 } 1332 1333 if (!nouveau_modeset) 1334 return 0; 1335 1336 #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER 1337 platform_driver_register(&nouveau_platform_driver); 1338 #endif 1339 1340 nouveau_register_dsm_handler(); 1341 nouveau_backlight_ctor(); 1342 1343 #ifdef CONFIG_PCI 1344 return pci_register_driver(&nouveau_drm_pci_driver); 1345 #else 1346 return 0; 1347 #endif 1348 } 1349 1350 static void __exit 1351 nouveau_drm_exit(void) 1352 { 1353 if (!nouveau_modeset) 1354 return; 1355 1356 #ifdef CONFIG_PCI 1357 pci_unregister_driver(&nouveau_drm_pci_driver); 1358 #endif 1359 nouveau_backlight_dtor(); 1360 nouveau_unregister_dsm_handler(); 1361 1362 #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER 1363 platform_driver_unregister(&nouveau_platform_driver); 1364 #endif 1365 if (IS_ENABLED(CONFIG_DRM_NOUVEAU_SVM)) 1366 mmu_notifier_synchronize(); 1367 } 1368 1369 module_init(nouveau_drm_init); 1370 module_exit(nouveau_drm_exit); 1371 1372 MODULE_DEVICE_TABLE(pci, nouveau_drm_pci_table); 1373 MODULE_AUTHOR(DRIVER_AUTHOR); 1374 MODULE_DESCRIPTION(DRIVER_DESC); 1375 MODULE_LICENSE("GPL and additional rights"); 1376