1 /* 2 * Copyright 2009 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 25 #include "drmP.h" 26 27 #include "nouveau_drv.h" 28 #include "nouveau_i2c.h" 29 #include "nouveau_connector.h" 30 #include "nouveau_encoder.h" 31 #include "nouveau_crtc.h" 32 #include "nouveau_gpio.h" 33 34 /****************************************************************************** 35 * aux channel util functions 36 *****************************************************************************/ 37 #define AUX_DBG(fmt, args...) do { \ 38 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_AUXCH) { \ 39 NV_PRINTK(KERN_DEBUG, dev, "AUXCH(%d): " fmt, ch, ##args); \ 40 } \ 41 } while (0) 42 #define AUX_ERR(fmt, args...) NV_ERROR(dev, "AUXCH(%d): " fmt, ch, ##args) 43 44 static void 45 auxch_fini(struct drm_device *dev, int ch) 46 { 47 nv_mask(dev, 0x00e4e4 + (ch * 0x50), 0x00310000, 0x00000000); 48 } 49 50 static int 51 auxch_init(struct drm_device *dev, int ch) 52 { 53 const u32 unksel = 1; /* nfi which to use, or if it matters.. */ 54 const u32 ureq = unksel ? 0x00100000 : 0x00200000; 55 const u32 urep = unksel ? 0x01000000 : 0x02000000; 56 u32 ctrl, timeout; 57 58 /* wait up to 1ms for any previous transaction to be done... */ 59 timeout = 1000; 60 do { 61 ctrl = nv_rd32(dev, 0x00e4e4 + (ch * 0x50)); 62 udelay(1); 63 if (!timeout--) { 64 AUX_ERR("begin idle timeout 0x%08x", ctrl); 65 return -EBUSY; 66 } 67 } while (ctrl & 0x03010000); 68 69 /* set some magic, and wait up to 1ms for it to appear */ 70 nv_mask(dev, 0x00e4e4 + (ch * 0x50), 0x00300000, ureq); 71 timeout = 1000; 72 do { 73 ctrl = nv_rd32(dev, 0x00e4e4 + (ch * 0x50)); 74 udelay(1); 75 if (!timeout--) { 76 AUX_ERR("magic wait 0x%08x\n", ctrl); 77 auxch_fini(dev, ch); 78 return -EBUSY; 79 } 80 } while ((ctrl & 0x03000000) != urep); 81 82 return 0; 83 } 84 85 static int 86 auxch_tx(struct drm_device *dev, int ch, u8 type, u32 addr, u8 *data, u8 size) 87 { 88 u32 ctrl, stat, timeout, retries; 89 u32 xbuf[4] = {}; 90 int ret, i; 91 92 AUX_DBG("%d: 0x%08x %d\n", type, addr, size); 93 94 ret = auxch_init(dev, ch); 95 if (ret) 96 goto out; 97 98 stat = nv_rd32(dev, 0x00e4e8 + (ch * 0x50)); 99 if (!(stat & 0x10000000)) { 100 AUX_DBG("sink not detected\n"); 101 ret = -ENXIO; 102 goto out; 103 } 104 105 if (!(type & 1)) { 106 memcpy(xbuf, data, size); 107 for (i = 0; i < 16; i += 4) { 108 AUX_DBG("wr 0x%08x\n", xbuf[i / 4]); 109 nv_wr32(dev, 0x00e4c0 + (ch * 0x50) + i, xbuf[i / 4]); 110 } 111 } 112 113 ctrl = nv_rd32(dev, 0x00e4e4 + (ch * 0x50)); 114 ctrl &= ~0x0001f0ff; 115 ctrl |= type << 12; 116 ctrl |= size - 1; 117 nv_wr32(dev, 0x00e4e0 + (ch * 0x50), addr); 118 119 /* retry transaction a number of times on failure... */ 120 ret = -EREMOTEIO; 121 for (retries = 0; retries < 32; retries++) { 122 /* reset, and delay a while if this is a retry */ 123 nv_wr32(dev, 0x00e4e4 + (ch * 0x50), 0x80000000 | ctrl); 124 nv_wr32(dev, 0x00e4e4 + (ch * 0x50), 0x00000000 | ctrl); 125 if (retries) 126 udelay(400); 127 128 /* transaction request, wait up to 1ms for it to complete */ 129 nv_wr32(dev, 0x00e4e4 + (ch * 0x50), 0x00010000 | ctrl); 130 131 timeout = 1000; 132 do { 133 ctrl = nv_rd32(dev, 0x00e4e4 + (ch * 0x50)); 134 udelay(1); 135 if (!timeout--) { 136 AUX_ERR("tx req timeout 0x%08x\n", ctrl); 137 goto out; 138 } 139 } while (ctrl & 0x00010000); 140 141 /* read status, and check if transaction completed ok */ 142 stat = nv_mask(dev, 0x00e4e8 + (ch * 0x50), 0, 0); 143 if (!(stat & 0x000f0f00)) { 144 ret = 0; 145 break; 146 } 147 148 AUX_DBG("%02d 0x%08x 0x%08x\n", retries, ctrl, stat); 149 } 150 151 if (type & 1) { 152 for (i = 0; i < 16; i += 4) { 153 xbuf[i / 4] = nv_rd32(dev, 0x00e4d0 + (ch * 0x50) + i); 154 AUX_DBG("rd 0x%08x\n", xbuf[i / 4]); 155 } 156 memcpy(data, xbuf, size); 157 } 158 159 out: 160 auxch_fini(dev, ch); 161 return ret; 162 } 163 164 static u32 165 dp_link_bw_get(struct drm_device *dev, int or, int link) 166 { 167 u32 ctrl = nv_rd32(dev, 0x614300 + (or * 0x800)); 168 if (!(ctrl & 0x000c0000)) 169 return 162000; 170 return 270000; 171 } 172 173 static int 174 dp_lane_count_get(struct drm_device *dev, int or, int link) 175 { 176 u32 ctrl = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link)); 177 switch (ctrl & 0x000f0000) { 178 case 0x00010000: return 1; 179 case 0x00030000: return 2; 180 default: 181 return 4; 182 } 183 } 184 185 void 186 nouveau_dp_tu_update(struct drm_device *dev, int or, int link, u32 clk, u32 bpp) 187 { 188 const u32 symbol = 100000; 189 int bestTU = 0, bestVTUi = 0, bestVTUf = 0, bestVTUa = 0; 190 int TU, VTUi, VTUf, VTUa; 191 u64 link_data_rate, link_ratio, unk; 192 u32 best_diff = 64 * symbol; 193 u32 link_nr, link_bw, r; 194 195 /* calculate packed data rate for each lane */ 196 link_nr = dp_lane_count_get(dev, or, link); 197 link_data_rate = (clk * bpp / 8) / link_nr; 198 199 /* calculate ratio of packed data rate to link symbol rate */ 200 link_bw = dp_link_bw_get(dev, or, link); 201 link_ratio = link_data_rate * symbol; 202 r = do_div(link_ratio, link_bw); 203 204 for (TU = 64; TU >= 32; TU--) { 205 /* calculate average number of valid symbols in each TU */ 206 u32 tu_valid = link_ratio * TU; 207 u32 calc, diff; 208 209 /* find a hw representation for the fraction.. */ 210 VTUi = tu_valid / symbol; 211 calc = VTUi * symbol; 212 diff = tu_valid - calc; 213 if (diff) { 214 if (diff >= (symbol / 2)) { 215 VTUf = symbol / (symbol - diff); 216 if (symbol - (VTUf * diff)) 217 VTUf++; 218 219 if (VTUf <= 15) { 220 VTUa = 1; 221 calc += symbol - (symbol / VTUf); 222 } else { 223 VTUa = 0; 224 VTUf = 1; 225 calc += symbol; 226 } 227 } else { 228 VTUa = 0; 229 VTUf = min((int)(symbol / diff), 15); 230 calc += symbol / VTUf; 231 } 232 233 diff = calc - tu_valid; 234 } else { 235 /* no remainder, but the hw doesn't like the fractional 236 * part to be zero. decrement the integer part and 237 * have the fraction add a whole symbol back 238 */ 239 VTUa = 0; 240 VTUf = 1; 241 VTUi--; 242 } 243 244 if (diff < best_diff) { 245 best_diff = diff; 246 bestTU = TU; 247 bestVTUa = VTUa; 248 bestVTUf = VTUf; 249 bestVTUi = VTUi; 250 if (diff == 0) 251 break; 252 } 253 } 254 255 if (!bestTU) { 256 NV_ERROR(dev, "DP: unable to find suitable config\n"); 257 return; 258 } 259 260 /* XXX close to vbios numbers, but not right */ 261 unk = (symbol - link_ratio) * bestTU; 262 unk *= link_ratio; 263 r = do_div(unk, symbol); 264 r = do_div(unk, symbol); 265 unk += 6; 266 267 nv_mask(dev, NV50_SOR_DP_CTRL(or, link), 0x000001fc, bestTU << 2); 268 nv_mask(dev, NV50_SOR_DP_SCFG(or, link), 0x010f7f3f, bestVTUa << 24 | 269 bestVTUf << 16 | 270 bestVTUi << 8 | 271 unk); 272 } 273 274 u8 * 275 nouveau_dp_bios_data(struct drm_device *dev, struct dcb_entry *dcb, u8 **entry) 276 { 277 struct bit_entry d; 278 u8 *table; 279 int i; 280 281 if (bit_table(dev, 'd', &d)) { 282 NV_ERROR(dev, "BIT 'd' table not found\n"); 283 return NULL; 284 } 285 286 if (d.version != 1) { 287 NV_ERROR(dev, "BIT 'd' table version %d unknown\n", d.version); 288 return NULL; 289 } 290 291 table = ROMPTR(dev, d.data[0]); 292 if (!table) { 293 NV_ERROR(dev, "displayport table pointer invalid\n"); 294 return NULL; 295 } 296 297 switch (table[0]) { 298 case 0x20: 299 case 0x21: 300 case 0x30: 301 break; 302 default: 303 NV_ERROR(dev, "displayport table 0x%02x unknown\n", table[0]); 304 return NULL; 305 } 306 307 for (i = 0; i < table[3]; i++) { 308 *entry = ROMPTR(dev, table[table[1] + (i * table[2])]); 309 if (*entry && bios_encoder_match(dcb, ROM32((*entry)[0]))) 310 return table; 311 } 312 313 NV_ERROR(dev, "displayport encoder table not found\n"); 314 return NULL; 315 } 316 317 /****************************************************************************** 318 * link training 319 *****************************************************************************/ 320 struct dp_state { 321 struct dcb_entry *dcb; 322 u8 *table; 323 u8 *entry; 324 int auxch; 325 int crtc; 326 int or; 327 int link; 328 u8 *dpcd; 329 int link_nr; 330 u32 link_bw; 331 u8 stat[6]; 332 u8 conf[4]; 333 }; 334 335 static void 336 dp_set_link_config(struct drm_device *dev, struct dp_state *dp) 337 { 338 int or = dp->or, link = dp->link; 339 u8 *entry, sink[2]; 340 u32 dp_ctrl; 341 u16 script; 342 343 NV_DEBUG_KMS(dev, "%d lanes at %d KB/s\n", dp->link_nr, dp->link_bw); 344 345 /* set selected link rate on source */ 346 switch (dp->link_bw) { 347 case 270000: 348 nv_mask(dev, 0x614300 + (or * 0x800), 0x000c0000, 0x00040000); 349 sink[0] = DP_LINK_BW_2_7; 350 break; 351 default: 352 nv_mask(dev, 0x614300 + (or * 0x800), 0x000c0000, 0x00000000); 353 sink[0] = DP_LINK_BW_1_62; 354 break; 355 } 356 357 /* offset +0x0a of each dp encoder table entry is a pointer to another 358 * table, that has (among other things) pointers to more scripts that 359 * need to be executed, this time depending on link speed. 360 */ 361 entry = ROMPTR(dev, dp->entry[10]); 362 if (entry) { 363 if (dp->table[0] < 0x30) { 364 while (dp->link_bw < (ROM16(entry[0]) * 10)) 365 entry += 4; 366 script = ROM16(entry[2]); 367 } else { 368 while (dp->link_bw < (entry[0] * 27000)) 369 entry += 3; 370 script = ROM16(entry[1]); 371 } 372 373 nouveau_bios_run_init_table(dev, script, dp->dcb, dp->crtc); 374 } 375 376 /* configure lane count on the source */ 377 dp_ctrl = ((1 << dp->link_nr) - 1) << 16; 378 sink[1] = dp->link_nr; 379 if (dp->dpcd[2] & DP_ENHANCED_FRAME_CAP) { 380 dp_ctrl |= 0x00004000; 381 sink[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 382 } 383 384 nv_mask(dev, NV50_SOR_DP_CTRL(or, link), 0x001f4000, dp_ctrl); 385 386 /* inform the sink of the new configuration */ 387 auxch_tx(dev, dp->auxch, 8, DP_LINK_BW_SET, sink, 2); 388 } 389 390 static void 391 dp_set_training_pattern(struct drm_device *dev, struct dp_state *dp, u8 tp) 392 { 393 u8 sink_tp; 394 395 NV_DEBUG_KMS(dev, "training pattern %d\n", tp); 396 397 nv_mask(dev, NV50_SOR_DP_CTRL(dp->or, dp->link), 0x0f000000, tp << 24); 398 399 auxch_tx(dev, dp->auxch, 9, DP_TRAINING_PATTERN_SET, &sink_tp, 1); 400 sink_tp &= ~DP_TRAINING_PATTERN_MASK; 401 sink_tp |= tp; 402 auxch_tx(dev, dp->auxch, 8, DP_TRAINING_PATTERN_SET, &sink_tp, 1); 403 } 404 405 static const u8 nv50_lane_map[] = { 16, 8, 0, 24 }; 406 static const u8 nvaf_lane_map[] = { 24, 16, 8, 0 }; 407 408 static int 409 dp_link_train_commit(struct drm_device *dev, struct dp_state *dp) 410 { 411 struct drm_nouveau_private *dev_priv = dev->dev_private; 412 u32 mask = 0, drv = 0, pre = 0, unk = 0; 413 const u8 *shifts; 414 int link = dp->link; 415 int or = dp->or; 416 int i; 417 418 if (dev_priv->chipset != 0xaf) 419 shifts = nv50_lane_map; 420 else 421 shifts = nvaf_lane_map; 422 423 for (i = 0; i < dp->link_nr; i++) { 424 u8 *conf = dp->entry + dp->table[4]; 425 u8 lane = (dp->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf; 426 u8 lpre = (lane & 0x0c) >> 2; 427 u8 lvsw = (lane & 0x03) >> 0; 428 429 mask |= 0xff << shifts[i]; 430 unk |= 1 << (shifts[i] >> 3); 431 432 dp->conf[i] = (lpre << 3) | lvsw; 433 if (lvsw == DP_TRAIN_VOLTAGE_SWING_1200) 434 dp->conf[i] |= DP_TRAIN_MAX_SWING_REACHED; 435 if (lpre == DP_TRAIN_PRE_EMPHASIS_9_5) 436 dp->conf[i] |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 437 438 NV_DEBUG_KMS(dev, "config lane %d %02x\n", i, dp->conf[i]); 439 440 if (dp->table[0] < 0x30) { 441 u8 *last = conf + (dp->entry[4] * dp->table[5]); 442 while (lvsw != conf[0] || lpre != conf[1]) { 443 conf += dp->table[5]; 444 if (conf >= last) 445 return -EINVAL; 446 } 447 448 conf += 2; 449 } else { 450 /* no lookup table anymore, set entries for each 451 * combination of voltage swing and pre-emphasis 452 * level allowed by the DP spec. 453 */ 454 switch (lvsw) { 455 case 0: lpre += 0; break; 456 case 1: lpre += 4; break; 457 case 2: lpre += 7; break; 458 case 3: lpre += 9; break; 459 } 460 461 conf = conf + (lpre * dp->table[5]); 462 conf++; 463 } 464 465 drv |= conf[0] << shifts[i]; 466 pre |= conf[1] << shifts[i]; 467 unk = (unk & ~0x0000ff00) | (conf[2] << 8); 468 } 469 470 nv_mask(dev, NV50_SOR_DP_UNK118(or, link), mask, drv); 471 nv_mask(dev, NV50_SOR_DP_UNK120(or, link), mask, pre); 472 nv_mask(dev, NV50_SOR_DP_UNK130(or, link), 0x0000ff0f, unk); 473 474 return auxch_tx(dev, dp->auxch, 8, DP_TRAINING_LANE0_SET, dp->conf, 4); 475 } 476 477 static int 478 dp_link_train_update(struct drm_device *dev, struct dp_state *dp, u32 delay) 479 { 480 int ret; 481 482 udelay(delay); 483 484 ret = auxch_tx(dev, dp->auxch, 9, DP_LANE0_1_STATUS, dp->stat, 6); 485 if (ret) 486 return ret; 487 488 NV_DEBUG_KMS(dev, "status %02x %02x %02x %02x %02x %02x\n", 489 dp->stat[0], dp->stat[1], dp->stat[2], dp->stat[3], 490 dp->stat[4], dp->stat[5]); 491 return 0; 492 } 493 494 static int 495 dp_link_train_cr(struct drm_device *dev, struct dp_state *dp) 496 { 497 bool cr_done = false, abort = false; 498 int voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 499 int tries = 0, i; 500 501 dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_1); 502 503 do { 504 if (dp_link_train_commit(dev, dp) || 505 dp_link_train_update(dev, dp, 100)) 506 break; 507 508 cr_done = true; 509 for (i = 0; i < dp->link_nr; i++) { 510 u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf; 511 if (!(lane & DP_LANE_CR_DONE)) { 512 cr_done = false; 513 if (dp->conf[i] & DP_TRAIN_MAX_SWING_REACHED) 514 abort = true; 515 break; 516 } 517 } 518 519 if ((dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) { 520 voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 521 tries = 0; 522 } 523 } while (!cr_done && !abort && ++tries < 5); 524 525 return cr_done ? 0 : -1; 526 } 527 528 static int 529 dp_link_train_eq(struct drm_device *dev, struct dp_state *dp) 530 { 531 bool eq_done, cr_done = true; 532 int tries = 0, i; 533 534 dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_2); 535 536 do { 537 if (dp_link_train_update(dev, dp, 400)) 538 break; 539 540 eq_done = !!(dp->stat[2] & DP_INTERLANE_ALIGN_DONE); 541 for (i = 0; i < dp->link_nr && eq_done; i++) { 542 u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf; 543 if (!(lane & DP_LANE_CR_DONE)) 544 cr_done = false; 545 if (!(lane & DP_LANE_CHANNEL_EQ_DONE) || 546 !(lane & DP_LANE_SYMBOL_LOCKED)) 547 eq_done = false; 548 } 549 550 if (dp_link_train_commit(dev, dp)) 551 break; 552 } while (!eq_done && cr_done && ++tries <= 5); 553 554 return eq_done ? 0 : -1; 555 } 556 557 bool 558 nouveau_dp_link_train(struct drm_encoder *encoder, u32 datarate) 559 { 560 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 561 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 562 struct nouveau_connector *nv_connector = 563 nouveau_encoder_connector_get(nv_encoder); 564 struct drm_device *dev = encoder->dev; 565 struct nouveau_i2c_chan *auxch; 566 const u32 bw_list[] = { 270000, 162000, 0 }; 567 const u32 *link_bw = bw_list; 568 struct dp_state dp; 569 570 auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index); 571 if (!auxch) 572 return false; 573 574 dp.table = nouveau_dp_bios_data(dev, nv_encoder->dcb, &dp.entry); 575 if (!dp.table) 576 return -EINVAL; 577 578 dp.dcb = nv_encoder->dcb; 579 dp.crtc = nv_crtc->index; 580 dp.auxch = auxch->drive; 581 dp.or = nv_encoder->or; 582 dp.link = !(nv_encoder->dcb->sorconf.link & 1); 583 dp.dpcd = nv_encoder->dp.dpcd; 584 585 /* some sinks toggle hotplug in response to some of the actions 586 * we take during link training (DP_SET_POWER is one), we need 587 * to ignore them for the moment to avoid races. 588 */ 589 nouveau_gpio_irq(dev, 0, nv_connector->hpd, 0xff, false); 590 591 /* enable down-spreading, if possible */ 592 if (dp.table[1] >= 16) { 593 u16 script = ROM16(dp.entry[14]); 594 if (nv_encoder->dp.dpcd[3] & 1) 595 script = ROM16(dp.entry[12]); 596 597 nouveau_bios_run_init_table(dev, script, dp.dcb, dp.crtc); 598 } 599 600 /* execute pre-train script from vbios */ 601 nouveau_bios_run_init_table(dev, ROM16(dp.entry[6]), dp.dcb, dp.crtc); 602 603 /* start off at highest link rate supported by encoder and display */ 604 while (*link_bw > nv_encoder->dp.link_bw) 605 link_bw++; 606 607 while (link_bw[0]) { 608 /* find minimum required lane count at this link rate */ 609 dp.link_nr = nv_encoder->dp.link_nr; 610 while ((dp.link_nr >> 1) * link_bw[0] > datarate) 611 dp.link_nr >>= 1; 612 613 /* drop link rate to minimum with this lane count */ 614 while ((link_bw[1] * dp.link_nr) > datarate) 615 link_bw++; 616 dp.link_bw = link_bw[0]; 617 618 /* program selected link configuration */ 619 dp_set_link_config(dev, &dp); 620 621 /* attempt to train the link at this configuration */ 622 memset(dp.stat, 0x00, sizeof(dp.stat)); 623 if (!dp_link_train_cr(dev, &dp) && 624 !dp_link_train_eq(dev, &dp)) 625 break; 626 627 /* retry at lower rate */ 628 link_bw++; 629 } 630 631 /* finish link training */ 632 dp_set_training_pattern(dev, &dp, DP_TRAINING_PATTERN_DISABLE); 633 634 /* execute post-train script from vbios */ 635 nouveau_bios_run_init_table(dev, ROM16(dp.entry[8]), dp.dcb, dp.crtc); 636 637 /* re-enable hotplug detect */ 638 nouveau_gpio_irq(dev, 0, nv_connector->hpd, 0xff, true); 639 return true; 640 } 641 642 bool 643 nouveau_dp_detect(struct drm_encoder *encoder) 644 { 645 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 646 struct drm_device *dev = encoder->dev; 647 struct nouveau_i2c_chan *auxch; 648 u8 *dpcd = nv_encoder->dp.dpcd; 649 int ret; 650 651 auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index); 652 if (!auxch) 653 return false; 654 655 ret = auxch_tx(dev, auxch->drive, 9, DP_DPCD_REV, dpcd, 8); 656 if (ret) 657 return false; 658 659 nv_encoder->dp.link_bw = 27000 * dpcd[1]; 660 nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK; 661 662 NV_DEBUG_KMS(dev, "display: %dx%d dpcd 0x%02x\n", 663 nv_encoder->dp.link_nr, nv_encoder->dp.link_bw, dpcd[0]); 664 NV_DEBUG_KMS(dev, "encoder: %dx%d\n", 665 nv_encoder->dcb->dpconf.link_nr, 666 nv_encoder->dcb->dpconf.link_bw); 667 668 if (nv_encoder->dcb->dpconf.link_nr < nv_encoder->dp.link_nr) 669 nv_encoder->dp.link_nr = nv_encoder->dcb->dpconf.link_nr; 670 if (nv_encoder->dcb->dpconf.link_bw < nv_encoder->dp.link_bw) 671 nv_encoder->dp.link_bw = nv_encoder->dcb->dpconf.link_bw; 672 673 NV_DEBUG_KMS(dev, "maximum: %dx%d\n", 674 nv_encoder->dp.link_nr, nv_encoder->dp.link_bw); 675 676 return true; 677 } 678 679 int 680 nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 681 uint8_t *data, int data_nr) 682 { 683 return auxch_tx(auxch->dev, auxch->drive, cmd, addr, data, data_nr); 684 } 685 686 static int 687 nouveau_dp_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) 688 { 689 struct nouveau_i2c_chan *auxch = (struct nouveau_i2c_chan *)adap; 690 struct i2c_msg *msg = msgs; 691 int ret, mcnt = num; 692 693 while (mcnt--) { 694 u8 remaining = msg->len; 695 u8 *ptr = msg->buf; 696 697 while (remaining) { 698 u8 cnt = (remaining > 16) ? 16 : remaining; 699 u8 cmd; 700 701 if (msg->flags & I2C_M_RD) 702 cmd = AUX_I2C_READ; 703 else 704 cmd = AUX_I2C_WRITE; 705 706 if (mcnt || remaining > 16) 707 cmd |= AUX_I2C_MOT; 708 709 ret = nouveau_dp_auxch(auxch, cmd, msg->addr, ptr, cnt); 710 if (ret < 0) 711 return ret; 712 713 ptr += cnt; 714 remaining -= cnt; 715 } 716 717 msg++; 718 } 719 720 return num; 721 } 722 723 static u32 724 nouveau_dp_i2c_func(struct i2c_adapter *adap) 725 { 726 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 727 } 728 729 const struct i2c_algorithm nouveau_dp_i2c_algo = { 730 .master_xfer = nouveau_dp_i2c_xfer, 731 .functionality = nouveau_dp_i2c_func 732 }; 733