1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 25 #include <nvif/os.h> 26 #include <nvif/class.h> 27 #include <nvif/cl0002.h> 28 #include <nvif/cl006b.h> 29 #include <nvif/cl506f.h> 30 #include <nvif/cl906f.h> 31 #include <nvif/cla06f.h> 32 #include <nvif/clc36f.h> 33 #include <nvif/ioctl.h> 34 35 /*XXX*/ 36 #include <core/client.h> 37 38 #include "nouveau_drv.h" 39 #include "nouveau_dma.h" 40 #include "nouveau_bo.h" 41 #include "nouveau_chan.h" 42 #include "nouveau_fence.h" 43 #include "nouveau_abi16.h" 44 #include "nouveau_vmm.h" 45 46 MODULE_PARM_DESC(vram_pushbuf, "Create DMA push buffers in VRAM"); 47 int nouveau_vram_pushbuf; 48 module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400); 49 50 static int 51 nouveau_channel_killed(struct nvif_notify *ntfy) 52 { 53 struct nouveau_channel *chan = container_of(ntfy, typeof(*chan), kill); 54 struct nouveau_cli *cli = (void *)chan->user.client; 55 NV_PRINTK(warn, cli, "channel %d killed!\n", chan->chid); 56 atomic_set(&chan->killed, 1); 57 return NVIF_NOTIFY_DROP; 58 } 59 60 int 61 nouveau_channel_idle(struct nouveau_channel *chan) 62 { 63 if (likely(chan && chan->fence && !atomic_read(&chan->killed))) { 64 struct nouveau_cli *cli = (void *)chan->user.client; 65 struct nouveau_fence *fence = NULL; 66 int ret; 67 68 ret = nouveau_fence_new(chan, false, &fence); 69 if (!ret) { 70 ret = nouveau_fence_wait(fence, false, false); 71 nouveau_fence_unref(&fence); 72 } 73 74 if (ret) { 75 NV_PRINTK(err, cli, "failed to idle channel %d [%s]\n", 76 chan->chid, nvxx_client(&cli->base)->name); 77 return ret; 78 } 79 } 80 return 0; 81 } 82 83 void 84 nouveau_channel_del(struct nouveau_channel **pchan) 85 { 86 struct nouveau_channel *chan = *pchan; 87 if (chan) { 88 struct nouveau_cli *cli = (void *)chan->user.client; 89 bool super; 90 91 if (cli) { 92 super = cli->base.super; 93 cli->base.super = true; 94 } 95 96 if (chan->fence) 97 nouveau_fence(chan->drm)->context_del(chan); 98 nvif_object_fini(&chan->nvsw); 99 nvif_object_fini(&chan->gart); 100 nvif_object_fini(&chan->vram); 101 nvif_notify_fini(&chan->kill); 102 nvif_object_fini(&chan->user); 103 nvif_object_fini(&chan->push.ctxdma); 104 nouveau_vma_del(&chan->push.vma); 105 nouveau_bo_unmap(chan->push.buffer); 106 if (chan->push.buffer && chan->push.buffer->pin_refcnt) 107 nouveau_bo_unpin(chan->push.buffer); 108 nouveau_bo_ref(NULL, &chan->push.buffer); 109 kfree(chan); 110 111 if (cli) 112 cli->base.super = super; 113 } 114 *pchan = NULL; 115 } 116 117 static int 118 nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device, 119 u32 size, struct nouveau_channel **pchan) 120 { 121 struct nouveau_cli *cli = (void *)device->object.client; 122 struct nv_dma_v0 args = {}; 123 struct nouveau_channel *chan; 124 u32 target; 125 int ret; 126 127 chan = *pchan = kzalloc(sizeof(*chan), GFP_KERNEL); 128 if (!chan) 129 return -ENOMEM; 130 131 chan->device = device; 132 chan->drm = drm; 133 atomic_set(&chan->killed, 0); 134 135 /* allocate memory for dma push buffer */ 136 target = TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED; 137 if (nouveau_vram_pushbuf) 138 target = TTM_PL_FLAG_VRAM; 139 140 ret = nouveau_bo_new(cli, size, 0, target, 0, 0, NULL, NULL, 141 &chan->push.buffer); 142 if (ret == 0) { 143 ret = nouveau_bo_pin(chan->push.buffer, target, false); 144 if (ret == 0) 145 ret = nouveau_bo_map(chan->push.buffer); 146 } 147 148 if (ret) { 149 nouveau_channel_del(pchan); 150 return ret; 151 } 152 153 /* create dma object covering the *entire* memory space that the 154 * pushbuf lives in, this is because the GEM code requires that 155 * we be able to call out to other (indirect) push buffers 156 */ 157 chan->push.addr = chan->push.buffer->bo.offset; 158 159 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) { 160 ret = nouveau_vma_new(chan->push.buffer, &cli->vmm, 161 &chan->push.vma); 162 if (ret) { 163 nouveau_channel_del(pchan); 164 return ret; 165 } 166 167 chan->push.addr = chan->push.vma->addr; 168 169 if (device->info.family >= NV_DEVICE_INFO_V0_FERMI) 170 return 0; 171 172 args.target = NV_DMA_V0_TARGET_VM; 173 args.access = NV_DMA_V0_ACCESS_VM; 174 args.start = 0; 175 args.limit = cli->vmm.vmm.limit - 1; 176 } else 177 if (chan->push.buffer->bo.mem.mem_type == TTM_PL_VRAM) { 178 if (device->info.family == NV_DEVICE_INFO_V0_TNT) { 179 /* nv04 vram pushbuf hack, retarget to its location in 180 * the framebuffer bar rather than direct vram access.. 181 * nfi why this exists, it came from the -nv ddx. 182 */ 183 args.target = NV_DMA_V0_TARGET_PCI; 184 args.access = NV_DMA_V0_ACCESS_RDWR; 185 args.start = nvxx_device(device)->func-> 186 resource_addr(nvxx_device(device), 1); 187 args.limit = args.start + device->info.ram_user - 1; 188 } else { 189 args.target = NV_DMA_V0_TARGET_VRAM; 190 args.access = NV_DMA_V0_ACCESS_RDWR; 191 args.start = 0; 192 args.limit = device->info.ram_user - 1; 193 } 194 } else { 195 if (chan->drm->agp.bridge) { 196 args.target = NV_DMA_V0_TARGET_AGP; 197 args.access = NV_DMA_V0_ACCESS_RDWR; 198 args.start = chan->drm->agp.base; 199 args.limit = chan->drm->agp.base + 200 chan->drm->agp.size - 1; 201 } else { 202 args.target = NV_DMA_V0_TARGET_VM; 203 args.access = NV_DMA_V0_ACCESS_RDWR; 204 args.start = 0; 205 args.limit = cli->vmm.vmm.limit - 1; 206 } 207 } 208 209 ret = nvif_object_init(&device->object, 0, NV_DMA_FROM_MEMORY, 210 &args, sizeof(args), &chan->push.ctxdma); 211 if (ret) { 212 nouveau_channel_del(pchan); 213 return ret; 214 } 215 216 return 0; 217 } 218 219 static int 220 nouveau_channel_ind(struct nouveau_drm *drm, struct nvif_device *device, 221 u64 runlist, bool priv, struct nouveau_channel **pchan) 222 { 223 struct nouveau_cli *cli = (void *)device->object.client; 224 static const u16 oclasses[] = { TURING_CHANNEL_GPFIFO_A, 225 VOLTA_CHANNEL_GPFIFO_A, 226 PASCAL_CHANNEL_GPFIFO_A, 227 MAXWELL_CHANNEL_GPFIFO_A, 228 KEPLER_CHANNEL_GPFIFO_B, 229 KEPLER_CHANNEL_GPFIFO_A, 230 FERMI_CHANNEL_GPFIFO, 231 G82_CHANNEL_GPFIFO, 232 NV50_CHANNEL_GPFIFO, 233 0 }; 234 const u16 *oclass = oclasses; 235 union { 236 struct nv50_channel_gpfifo_v0 nv50; 237 struct fermi_channel_gpfifo_v0 fermi; 238 struct kepler_channel_gpfifo_a_v0 kepler; 239 struct volta_channel_gpfifo_a_v0 volta; 240 } args; 241 struct nouveau_channel *chan; 242 u32 size; 243 int ret; 244 245 /* allocate dma push buffer */ 246 ret = nouveau_channel_prep(drm, device, 0x12000, &chan); 247 *pchan = chan; 248 if (ret) 249 return ret; 250 251 /* create channel object */ 252 do { 253 if (oclass[0] >= VOLTA_CHANNEL_GPFIFO_A) { 254 args.volta.version = 0; 255 args.volta.ilength = 0x02000; 256 args.volta.ioffset = 0x10000 + chan->push.addr; 257 args.volta.runlist = runlist; 258 args.volta.vmm = nvif_handle(&cli->vmm.vmm.object); 259 args.volta.priv = priv; 260 size = sizeof(args.volta); 261 } else 262 if (oclass[0] >= KEPLER_CHANNEL_GPFIFO_A) { 263 args.kepler.version = 0; 264 args.kepler.ilength = 0x02000; 265 args.kepler.ioffset = 0x10000 + chan->push.addr; 266 args.kepler.runlist = runlist; 267 args.kepler.vmm = nvif_handle(&cli->vmm.vmm.object); 268 args.kepler.priv = priv; 269 size = sizeof(args.kepler); 270 } else 271 if (oclass[0] >= FERMI_CHANNEL_GPFIFO) { 272 args.fermi.version = 0; 273 args.fermi.ilength = 0x02000; 274 args.fermi.ioffset = 0x10000 + chan->push.addr; 275 args.fermi.vmm = nvif_handle(&cli->vmm.vmm.object); 276 size = sizeof(args.fermi); 277 } else { 278 args.nv50.version = 0; 279 args.nv50.ilength = 0x02000; 280 args.nv50.ioffset = 0x10000 + chan->push.addr; 281 args.nv50.pushbuf = nvif_handle(&chan->push.ctxdma); 282 args.nv50.vmm = nvif_handle(&cli->vmm.vmm.object); 283 size = sizeof(args.nv50); 284 } 285 286 ret = nvif_object_init(&device->object, 0, *oclass++, 287 &args, size, &chan->user); 288 if (ret == 0) { 289 if (chan->user.oclass >= VOLTA_CHANNEL_GPFIFO_A) { 290 chan->chid = args.volta.chid; 291 chan->inst = args.volta.inst; 292 chan->token = args.volta.token; 293 } else 294 if (chan->user.oclass >= KEPLER_CHANNEL_GPFIFO_A) { 295 chan->chid = args.kepler.chid; 296 chan->inst = args.kepler.inst; 297 } else 298 if (chan->user.oclass >= FERMI_CHANNEL_GPFIFO) { 299 chan->chid = args.fermi.chid; 300 } else { 301 chan->chid = args.nv50.chid; 302 } 303 return ret; 304 } 305 } while (*oclass); 306 307 nouveau_channel_del(pchan); 308 return ret; 309 } 310 311 static int 312 nouveau_channel_dma(struct nouveau_drm *drm, struct nvif_device *device, 313 struct nouveau_channel **pchan) 314 { 315 static const u16 oclasses[] = { NV40_CHANNEL_DMA, 316 NV17_CHANNEL_DMA, 317 NV10_CHANNEL_DMA, 318 NV03_CHANNEL_DMA, 319 0 }; 320 const u16 *oclass = oclasses; 321 struct nv03_channel_dma_v0 args; 322 struct nouveau_channel *chan; 323 int ret; 324 325 /* allocate dma push buffer */ 326 ret = nouveau_channel_prep(drm, device, 0x10000, &chan); 327 *pchan = chan; 328 if (ret) 329 return ret; 330 331 /* create channel object */ 332 args.version = 0; 333 args.pushbuf = nvif_handle(&chan->push.ctxdma); 334 args.offset = chan->push.addr; 335 336 do { 337 ret = nvif_object_init(&device->object, 0, *oclass++, 338 &args, sizeof(args), &chan->user); 339 if (ret == 0) { 340 chan->chid = args.chid; 341 return ret; 342 } 343 } while (ret && *oclass); 344 345 nouveau_channel_del(pchan); 346 return ret; 347 } 348 349 static int 350 nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) 351 { 352 struct nvif_device *device = chan->device; 353 struct nouveau_cli *cli = (void *)chan->user.client; 354 struct nouveau_drm *drm = chan->drm; 355 struct nv_dma_v0 args = {}; 356 int ret, i; 357 358 nvif_object_map(&chan->user, NULL, 0); 359 360 if (chan->user.oclass >= FERMI_CHANNEL_GPFIFO) { 361 ret = nvif_notify_init(&chan->user, nouveau_channel_killed, 362 true, NV906F_V0_NTFY_KILLED, 363 NULL, 0, 0, &chan->kill); 364 if (ret == 0) 365 ret = nvif_notify_get(&chan->kill); 366 if (ret) { 367 NV_ERROR(drm, "Failed to request channel kill " 368 "notification: %d\n", ret); 369 return ret; 370 } 371 } 372 373 /* allocate dma objects to cover all allowed vram, and gart */ 374 if (device->info.family < NV_DEVICE_INFO_V0_FERMI) { 375 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) { 376 args.target = NV_DMA_V0_TARGET_VM; 377 args.access = NV_DMA_V0_ACCESS_VM; 378 args.start = 0; 379 args.limit = cli->vmm.vmm.limit - 1; 380 } else { 381 args.target = NV_DMA_V0_TARGET_VRAM; 382 args.access = NV_DMA_V0_ACCESS_RDWR; 383 args.start = 0; 384 args.limit = device->info.ram_user - 1; 385 } 386 387 ret = nvif_object_init(&chan->user, vram, NV_DMA_IN_MEMORY, 388 &args, sizeof(args), &chan->vram); 389 if (ret) 390 return ret; 391 392 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) { 393 args.target = NV_DMA_V0_TARGET_VM; 394 args.access = NV_DMA_V0_ACCESS_VM; 395 args.start = 0; 396 args.limit = cli->vmm.vmm.limit - 1; 397 } else 398 if (chan->drm->agp.bridge) { 399 args.target = NV_DMA_V0_TARGET_AGP; 400 args.access = NV_DMA_V0_ACCESS_RDWR; 401 args.start = chan->drm->agp.base; 402 args.limit = chan->drm->agp.base + 403 chan->drm->agp.size - 1; 404 } else { 405 args.target = NV_DMA_V0_TARGET_VM; 406 args.access = NV_DMA_V0_ACCESS_RDWR; 407 args.start = 0; 408 args.limit = cli->vmm.vmm.limit - 1; 409 } 410 411 ret = nvif_object_init(&chan->user, gart, NV_DMA_IN_MEMORY, 412 &args, sizeof(args), &chan->gart); 413 if (ret) 414 return ret; 415 } 416 417 /* initialise dma tracking parameters */ 418 switch (chan->user.oclass & 0x00ff) { 419 case 0x006b: 420 case 0x006e: 421 chan->user_put = 0x40; 422 chan->user_get = 0x44; 423 chan->dma.max = (0x10000 / 4) - 2; 424 break; 425 default: 426 chan->user_put = 0x40; 427 chan->user_get = 0x44; 428 chan->user_get_hi = 0x60; 429 chan->dma.ib_base = 0x10000 / 4; 430 chan->dma.ib_max = (0x02000 / 8) - 1; 431 chan->dma.ib_put = 0; 432 chan->dma.ib_free = chan->dma.ib_max - chan->dma.ib_put; 433 chan->dma.max = chan->dma.ib_base; 434 break; 435 } 436 437 chan->dma.put = 0; 438 chan->dma.cur = chan->dma.put; 439 chan->dma.free = chan->dma.max - chan->dma.cur; 440 441 ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS); 442 if (ret) 443 return ret; 444 445 for (i = 0; i < NOUVEAU_DMA_SKIPS; i++) 446 OUT_RING(chan, 0x00000000); 447 448 /* allocate software object class (used for fences on <= nv05) */ 449 if (device->info.family < NV_DEVICE_INFO_V0_CELSIUS) { 450 ret = nvif_object_init(&chan->user, 0x006e, 451 NVIF_CLASS_SW_NV04, 452 NULL, 0, &chan->nvsw); 453 if (ret) 454 return ret; 455 456 ret = RING_SPACE(chan, 2); 457 if (ret) 458 return ret; 459 460 BEGIN_NV04(chan, NvSubSw, 0x0000, 1); 461 OUT_RING (chan, chan->nvsw.handle); 462 FIRE_RING (chan); 463 } 464 465 /* initialise synchronisation */ 466 return nouveau_fence(chan->drm)->context_new(chan); 467 } 468 469 int 470 nouveau_channel_new(struct nouveau_drm *drm, struct nvif_device *device, 471 u32 arg0, u32 arg1, bool priv, 472 struct nouveau_channel **pchan) 473 { 474 struct nouveau_cli *cli = (void *)device->object.client; 475 bool super; 476 int ret; 477 478 /* hack until fencenv50 is fixed, and agp access relaxed */ 479 super = cli->base.super; 480 cli->base.super = true; 481 482 ret = nouveau_channel_ind(drm, device, arg0, priv, pchan); 483 if (ret) { 484 NV_PRINTK(dbg, cli, "ib channel create, %d\n", ret); 485 ret = nouveau_channel_dma(drm, device, pchan); 486 if (ret) { 487 NV_PRINTK(dbg, cli, "dma channel create, %d\n", ret); 488 goto done; 489 } 490 } 491 492 ret = nouveau_channel_init(*pchan, arg0, arg1); 493 if (ret) { 494 NV_PRINTK(err, cli, "channel failed to initialise, %d\n", ret); 495 nouveau_channel_del(pchan); 496 } 497 498 done: 499 cli->base.super = super; 500 return ret; 501 } 502 503 int 504 nouveau_channels_init(struct nouveau_drm *drm) 505 { 506 struct { 507 struct nv_device_info_v1 m; 508 struct { 509 struct nv_device_info_v1_data channels; 510 } v; 511 } args = { 512 .m.version = 1, 513 .m.count = sizeof(args.v) / sizeof(args.v.channels), 514 .v.channels.mthd = NV_DEVICE_FIFO_CHANNELS, 515 }; 516 struct nvif_object *device = &drm->client.device.object; 517 int ret; 518 519 ret = nvif_object_mthd(device, NV_DEVICE_V0_INFO, &args, sizeof(args)); 520 if (ret || args.v.channels.mthd == NV_DEVICE_INFO_INVALID) 521 return -ENODEV; 522 523 drm->chan.nr = args.v.channels.data; 524 drm->chan.context_base = dma_fence_context_alloc(drm->chan.nr); 525 return 0; 526 } 527