1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include <nvif/push006c.h> 25 26 #include <nvif/class.h> 27 #include <nvif/cl0002.h> 28 #include <nvif/if0020.h> 29 30 #include "nouveau_drv.h" 31 #include "nouveau_dma.h" 32 #include "nouveau_bo.h" 33 #include "nouveau_chan.h" 34 #include "nouveau_fence.h" 35 #include "nouveau_abi16.h" 36 #include "nouveau_vmm.h" 37 #include "nouveau_svm.h" 38 39 MODULE_PARM_DESC(vram_pushbuf, "Create DMA push buffers in VRAM"); 40 int nouveau_vram_pushbuf; 41 module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400); 42 43 void 44 nouveau_channel_kill(struct nouveau_channel *chan) 45 { 46 atomic_set(&chan->killed, 1); 47 if (chan->fence) 48 nouveau_fence_context_kill(chan->fence, -ENODEV); 49 } 50 51 static int 52 nouveau_channel_killed(struct nvif_event *event, void *repv, u32 repc) 53 { 54 struct nouveau_channel *chan = container_of(event, typeof(*chan), kill); 55 struct nouveau_cli *cli = chan->cli; 56 57 NV_PRINTK(warn, cli, "channel %d killed!\n", chan->chid); 58 59 if (unlikely(!atomic_read(&chan->killed))) 60 nouveau_channel_kill(chan); 61 62 return NVIF_EVENT_DROP; 63 } 64 65 int 66 nouveau_channel_idle(struct nouveau_channel *chan) 67 { 68 if (likely(chan && chan->fence && !atomic_read(&chan->killed))) { 69 struct nouveau_cli *cli = chan->cli; 70 struct nouveau_fence *fence = NULL; 71 int ret; 72 73 ret = nouveau_fence_new(&fence, chan); 74 if (!ret) { 75 ret = nouveau_fence_wait(fence, false, false); 76 nouveau_fence_unref(&fence); 77 } 78 79 if (ret) { 80 NV_PRINTK(err, cli, "failed to idle channel %d [%s]\n", 81 chan->chid, cli->name); 82 return ret; 83 } 84 } 85 return 0; 86 } 87 88 void 89 nouveau_channel_del(struct nouveau_channel **pchan) 90 { 91 struct nouveau_channel *chan = *pchan; 92 if (chan) { 93 if (chan->fence) 94 nouveau_fence(chan->cli->drm)->context_del(chan); 95 96 if (nvif_object_constructed(&chan->user)) 97 nouveau_svmm_part(chan->vmm->svmm, chan->inst); 98 99 nvif_object_dtor(&chan->blit); 100 nvif_object_dtor(&chan->nvsw); 101 nvif_object_dtor(&chan->gart); 102 nvif_object_dtor(&chan->vram); 103 nvif_event_dtor(&chan->kill); 104 nvif_object_dtor(&chan->user); 105 nvif_mem_dtor(&chan->mem_userd); 106 nvif_object_dtor(&chan->push.ctxdma); 107 nouveau_vma_del(&chan->push.vma); 108 nouveau_bo_unmap(chan->push.buffer); 109 if (chan->push.buffer && chan->push.buffer->bo.pin_count) 110 nouveau_bo_unpin(chan->push.buffer); 111 nouveau_bo_fini(chan->push.buffer); 112 kfree(chan); 113 } 114 *pchan = NULL; 115 } 116 117 static void 118 nouveau_channel_kick(struct nvif_push *push) 119 { 120 struct nouveau_channel *chan = container_of(push, typeof(*chan), chan.push); 121 chan->dma.cur = chan->dma.cur + (chan->chan.push.cur - chan->chan.push.bgn); 122 FIRE_RING(chan); 123 chan->chan.push.bgn = chan->chan.push.cur; 124 } 125 126 static int 127 nouveau_channel_wait(struct nvif_push *push, u32 size) 128 { 129 struct nouveau_channel *chan = container_of(push, typeof(*chan), chan.push); 130 int ret; 131 chan->dma.cur = chan->dma.cur + (chan->chan.push.cur - chan->chan.push.bgn); 132 ret = RING_SPACE(chan, size); 133 if (ret == 0) { 134 chan->chan.push.bgn = chan->chan.push.mem.object.map.ptr; 135 chan->chan.push.bgn = chan->chan.push.bgn + chan->dma.cur; 136 chan->chan.push.cur = chan->chan.push.bgn; 137 chan->chan.push.end = chan->chan.push.bgn + size; 138 } 139 return ret; 140 } 141 142 static int 143 nouveau_channel_prep(struct nouveau_cli *cli, 144 u32 size, struct nouveau_channel **pchan) 145 { 146 struct nouveau_drm *drm = cli->drm; 147 struct nvif_device *device = &cli->device; 148 struct nv_dma_v0 args = {}; 149 struct nouveau_channel *chan; 150 u32 target; 151 int ret; 152 153 chan = *pchan = kzalloc(sizeof(*chan), GFP_KERNEL); 154 if (!chan) 155 return -ENOMEM; 156 157 chan->cli = cli; 158 chan->vmm = nouveau_cli_vmm(cli); 159 atomic_set(&chan->killed, 0); 160 161 /* allocate memory for dma push buffer */ 162 target = NOUVEAU_GEM_DOMAIN_GART | NOUVEAU_GEM_DOMAIN_COHERENT; 163 if (nouveau_vram_pushbuf) 164 target = NOUVEAU_GEM_DOMAIN_VRAM; 165 166 ret = nouveau_bo_new(cli, size, 0, target, 0, 0, NULL, NULL, 167 &chan->push.buffer); 168 if (ret == 0) { 169 ret = nouveau_bo_pin(chan->push.buffer, target, false); 170 if (ret == 0) 171 ret = nouveau_bo_map(chan->push.buffer); 172 } 173 174 if (ret) { 175 nouveau_channel_del(pchan); 176 return ret; 177 } 178 179 chan->chan.push.mem.object.parent = cli->base.object.parent; 180 chan->chan.push.mem.object.client = &cli->base; 181 chan->chan.push.mem.object.name = "chanPush"; 182 chan->chan.push.mem.object.map.ptr = chan->push.buffer->kmap.virtual; 183 chan->chan.push.wait = nouveau_channel_wait; 184 chan->chan.push.kick = nouveau_channel_kick; 185 186 /* create dma object covering the *entire* memory space that the 187 * pushbuf lives in, this is because the GEM code requires that 188 * we be able to call out to other (indirect) push buffers 189 */ 190 chan->push.addr = chan->push.buffer->offset; 191 192 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) { 193 ret = nouveau_vma_new(chan->push.buffer, chan->vmm, 194 &chan->push.vma); 195 if (ret) { 196 nouveau_channel_del(pchan); 197 return ret; 198 } 199 200 chan->push.addr = chan->push.vma->addr; 201 202 if (device->info.family >= NV_DEVICE_INFO_V0_FERMI) 203 return 0; 204 205 args.target = NV_DMA_V0_TARGET_VM; 206 args.access = NV_DMA_V0_ACCESS_VM; 207 args.start = 0; 208 args.limit = chan->vmm->vmm.limit - 1; 209 } else 210 if (chan->push.buffer->bo.resource->mem_type == TTM_PL_VRAM) { 211 if (device->info.family == NV_DEVICE_INFO_V0_TNT) { 212 /* nv04 vram pushbuf hack, retarget to its location in 213 * the framebuffer bar rather than direct vram access.. 214 * nfi why this exists, it came from the -nv ddx. 215 */ 216 args.target = NV_DMA_V0_TARGET_PCI; 217 args.access = NV_DMA_V0_ACCESS_RDWR; 218 args.start = nvxx_device(drm)->func->resource_addr(nvxx_device(drm), 1); 219 args.limit = args.start + device->info.ram_user - 1; 220 } else { 221 args.target = NV_DMA_V0_TARGET_VRAM; 222 args.access = NV_DMA_V0_ACCESS_RDWR; 223 args.start = 0; 224 args.limit = device->info.ram_user - 1; 225 } 226 } else { 227 if (drm->agp.bridge) { 228 args.target = NV_DMA_V0_TARGET_AGP; 229 args.access = NV_DMA_V0_ACCESS_RDWR; 230 args.start = drm->agp.base; 231 args.limit = drm->agp.base + drm->agp.size - 1; 232 } else { 233 args.target = NV_DMA_V0_TARGET_VM; 234 args.access = NV_DMA_V0_ACCESS_RDWR; 235 args.start = 0; 236 args.limit = chan->vmm->vmm.limit - 1; 237 } 238 } 239 240 ret = nvif_object_ctor(&device->object, "abi16PushCtxDma", 0, 241 NV_DMA_FROM_MEMORY, &args, sizeof(args), 242 &chan->push.ctxdma); 243 if (ret) { 244 nouveau_channel_del(pchan); 245 return ret; 246 } 247 248 return 0; 249 } 250 251 static int 252 nouveau_channel_ctor(struct nouveau_cli *cli, bool priv, u64 runm, 253 struct nouveau_channel **pchan) 254 { 255 const struct nvif_mclass hosts[] = { 256 { AMPERE_CHANNEL_GPFIFO_B, 0 }, 257 { AMPERE_CHANNEL_GPFIFO_A, 0 }, 258 { TURING_CHANNEL_GPFIFO_A, 0 }, 259 { VOLTA_CHANNEL_GPFIFO_A, 0 }, 260 { PASCAL_CHANNEL_GPFIFO_A, 0 }, 261 { MAXWELL_CHANNEL_GPFIFO_A, 0 }, 262 { KEPLER_CHANNEL_GPFIFO_B, 0 }, 263 { KEPLER_CHANNEL_GPFIFO_A, 0 }, 264 { FERMI_CHANNEL_GPFIFO , 0 }, 265 { G82_CHANNEL_GPFIFO , 0 }, 266 { NV50_CHANNEL_GPFIFO , 0 }, 267 { NV40_CHANNEL_DMA , 0 }, 268 { NV17_CHANNEL_DMA , 0 }, 269 { NV10_CHANNEL_DMA , 0 }, 270 { NV03_CHANNEL_DMA , 0 }, 271 {} 272 }; 273 DEFINE_RAW_FLEX(struct nvif_chan_v0, args, name, TASK_COMM_LEN + 16); 274 struct nvif_device *device = &cli->device; 275 struct nouveau_channel *chan; 276 const u64 plength = 0x10000; 277 const u64 ioffset = plength; 278 const u64 ilength = 0x02000; 279 int cid, ret; 280 u64 size; 281 282 cid = nvif_mclass(&device->object, hosts); 283 if (cid < 0) 284 return cid; 285 286 if (hosts[cid].oclass < NV50_CHANNEL_GPFIFO) 287 size = plength; 288 else 289 size = ioffset + ilength; 290 291 /* allocate dma push buffer */ 292 ret = nouveau_channel_prep(cli, size, &chan); 293 *pchan = chan; 294 if (ret) 295 return ret; 296 297 /* create channel object */ 298 args->version = 0; 299 args->namelen = __member_size(args->name); 300 args->runlist = __ffs64(runm); 301 args->runq = 0; 302 args->priv = priv; 303 args->devm = BIT(0); 304 if (hosts[cid].oclass < NV50_CHANNEL_GPFIFO) { 305 args->vmm = 0; 306 args->ctxdma = nvif_handle(&chan->push.ctxdma); 307 args->offset = chan->push.addr; 308 args->length = 0; 309 } else { 310 args->vmm = nvif_handle(&chan->vmm->vmm.object); 311 if (hosts[cid].oclass < FERMI_CHANNEL_GPFIFO) 312 args->ctxdma = nvif_handle(&chan->push.ctxdma); 313 else 314 args->ctxdma = 0; 315 args->offset = ioffset + chan->push.addr; 316 args->length = ilength; 317 } 318 args->huserd = 0; 319 args->ouserd = 0; 320 321 /* allocate userd */ 322 if (hosts[cid].oclass >= VOLTA_CHANNEL_GPFIFO_A) { 323 ret = nvif_mem_ctor(&cli->mmu, "abi16ChanUSERD", NVIF_CLASS_MEM_GF100, 324 NVIF_MEM_VRAM | NVIF_MEM_COHERENT | NVIF_MEM_MAPPABLE, 325 0, PAGE_SIZE, NULL, 0, &chan->mem_userd); 326 if (ret) 327 return ret; 328 329 args->huserd = nvif_handle(&chan->mem_userd.object); 330 args->ouserd = 0; 331 332 chan->userd = &chan->mem_userd.object; 333 } else { 334 chan->userd = &chan->user; 335 } 336 337 snprintf(args->name, __member_size(args->name), "%s[%d]", 338 current->comm, task_pid_nr(current)); 339 340 ret = nvif_object_ctor(&device->object, "abi16ChanUser", 0, hosts[cid].oclass, 341 args, __struct_size(args), &chan->user); 342 if (ret) { 343 nouveau_channel_del(pchan); 344 return ret; 345 } 346 347 chan->runlist = args->runlist; 348 chan->chid = args->chid; 349 chan->inst = args->inst; 350 chan->token = args->token; 351 return 0; 352 } 353 354 static int 355 nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) 356 { 357 struct nouveau_cli *cli = chan->cli; 358 struct nouveau_drm *drm = cli->drm; 359 struct nvif_device *device = &cli->device; 360 struct nv_dma_v0 args = {}; 361 int ret, i; 362 363 ret = nvif_object_map(chan->userd, NULL, 0); 364 if (ret) 365 return ret; 366 367 if (chan->user.oclass >= FERMI_CHANNEL_GPFIFO) { 368 DEFINE_RAW_FLEX(struct nvif_event_v0, args, data, 369 sizeof(struct nvif_chan_event_v0)); 370 struct nvif_chan_event_v0 *host = 371 (struct nvif_chan_event_v0 *)args->data; 372 373 host->version = 0; 374 host->type = NVIF_CHAN_EVENT_V0_KILLED; 375 376 ret = nvif_event_ctor(&chan->user, "abi16ChanKilled", chan->chid, 377 nouveau_channel_killed, false, 378 args, __struct_size(args), &chan->kill); 379 if (ret == 0) 380 ret = nvif_event_allow(&chan->kill); 381 if (ret) { 382 NV_ERROR(drm, "Failed to request channel kill " 383 "notification: %d\n", ret); 384 return ret; 385 } 386 } 387 388 /* allocate dma objects to cover all allowed vram, and gart */ 389 if (device->info.family < NV_DEVICE_INFO_V0_FERMI) { 390 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) { 391 args.target = NV_DMA_V0_TARGET_VM; 392 args.access = NV_DMA_V0_ACCESS_VM; 393 args.start = 0; 394 args.limit = chan->vmm->vmm.limit - 1; 395 } else { 396 args.target = NV_DMA_V0_TARGET_VRAM; 397 args.access = NV_DMA_V0_ACCESS_RDWR; 398 args.start = 0; 399 args.limit = device->info.ram_user - 1; 400 } 401 402 ret = nvif_object_ctor(&chan->user, "abi16ChanVramCtxDma", vram, 403 NV_DMA_IN_MEMORY, &args, sizeof(args), 404 &chan->vram); 405 if (ret) 406 return ret; 407 408 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) { 409 args.target = NV_DMA_V0_TARGET_VM; 410 args.access = NV_DMA_V0_ACCESS_VM; 411 args.start = 0; 412 args.limit = chan->vmm->vmm.limit - 1; 413 } else 414 if (drm->agp.bridge) { 415 args.target = NV_DMA_V0_TARGET_AGP; 416 args.access = NV_DMA_V0_ACCESS_RDWR; 417 args.start = drm->agp.base; 418 args.limit = drm->agp.base + drm->agp.size - 1; 419 } else { 420 args.target = NV_DMA_V0_TARGET_VM; 421 args.access = NV_DMA_V0_ACCESS_RDWR; 422 args.start = 0; 423 args.limit = chan->vmm->vmm.limit - 1; 424 } 425 426 ret = nvif_object_ctor(&chan->user, "abi16ChanGartCtxDma", gart, 427 NV_DMA_IN_MEMORY, &args, sizeof(args), 428 &chan->gart); 429 if (ret) 430 return ret; 431 } 432 433 /* initialise dma tracking parameters */ 434 switch (chan->user.oclass) { 435 case NV03_CHANNEL_DMA: 436 case NV10_CHANNEL_DMA: 437 case NV17_CHANNEL_DMA: 438 case NV40_CHANNEL_DMA: 439 chan->user_put = 0x40; 440 chan->user_get = 0x44; 441 chan->dma.max = (0x10000 / 4) - 2; 442 break; 443 default: 444 chan->user_put = 0x40; 445 chan->user_get = 0x44; 446 chan->user_get_hi = 0x60; 447 chan->dma.ib_base = 0x10000 / 4; 448 chan->dma.ib_max = NV50_DMA_IB_MAX; 449 chan->dma.ib_put = 0; 450 chan->dma.ib_free = chan->dma.ib_max - chan->dma.ib_put; 451 chan->dma.max = chan->dma.ib_base; 452 break; 453 } 454 455 chan->dma.put = 0; 456 chan->dma.cur = chan->dma.put; 457 chan->dma.free = chan->dma.max - chan->dma.cur; 458 459 ret = PUSH_WAIT(&chan->chan.push, NOUVEAU_DMA_SKIPS); 460 if (ret) 461 return ret; 462 463 for (i = 0; i < NOUVEAU_DMA_SKIPS; i++) 464 PUSH_DATA(&chan->chan.push, 0x00000000); 465 466 /* allocate software object class (used for fences on <= nv05) */ 467 if (device->info.family < NV_DEVICE_INFO_V0_CELSIUS) { 468 ret = nvif_object_ctor(&chan->user, "abi16NvswFence", 0x006e, 469 NVIF_CLASS_SW_NV04, 470 NULL, 0, &chan->nvsw); 471 if (ret) 472 return ret; 473 474 ret = PUSH_WAIT(&chan->chan.push, 2); 475 if (ret) 476 return ret; 477 478 PUSH_NVSQ(&chan->chan.push, NV_SW, 0x0000, chan->nvsw.handle); 479 PUSH_KICK(&chan->chan.push); 480 } 481 482 /* initialise synchronisation */ 483 return nouveau_fence(drm)->context_new(chan); 484 } 485 486 int 487 nouveau_channel_new(struct nouveau_cli *cli, 488 bool priv, u64 runm, u32 vram, u32 gart, struct nouveau_channel **pchan) 489 { 490 int ret; 491 492 ret = nouveau_channel_ctor(cli, priv, runm, pchan); 493 if (ret) { 494 NV_PRINTK(dbg, cli, "channel create, %d\n", ret); 495 return ret; 496 } 497 498 ret = nouveau_channel_init(*pchan, vram, gart); 499 if (ret) { 500 NV_PRINTK(err, cli, "channel failed to initialise, %d\n", ret); 501 nouveau_channel_del(pchan); 502 return ret; 503 } 504 505 ret = nouveau_svmm_join((*pchan)->vmm->svmm, (*pchan)->inst); 506 if (ret) 507 nouveau_channel_del(pchan); 508 509 return ret; 510 } 511 512 void 513 nouveau_channels_fini(struct nouveau_drm *drm) 514 { 515 kfree(drm->runl); 516 } 517 518 int 519 nouveau_channels_init(struct nouveau_drm *drm) 520 { 521 DEFINE_RAW_FLEX(struct nv_device_info_v1, args, data, 2); 522 struct nv_device_info_v1_data *channels = &args->data[0]; 523 struct nv_device_info_v1_data *runlists = &args->data[1]; 524 struct nvif_object *device = &drm->client.device.object; 525 int ret, i; 526 527 args->version = 1; 528 args->count = __member_size(args->data) / sizeof(*args->data); 529 channels->mthd = NV_DEVICE_HOST_CHANNELS; 530 runlists->mthd = NV_DEVICE_HOST_RUNLISTS; 531 532 ret = nvif_object_mthd(device, NV_DEVICE_V0_INFO, args, 533 __struct_size(args)); 534 if (ret || 535 runlists->mthd == NV_DEVICE_INFO_INVALID || !runlists->data || 536 channels->mthd == NV_DEVICE_INFO_INVALID) 537 return -ENODEV; 538 539 drm->chan_nr = drm->chan_total = channels->data; 540 drm->runl_nr = fls64(runlists->data); 541 drm->runl = kcalloc(drm->runl_nr, sizeof(*drm->runl), GFP_KERNEL); 542 if (!drm->runl) 543 return -ENOMEM; 544 545 if (drm->chan_nr == 0) { 546 for (i = 0; i < drm->runl_nr; i++) { 547 if (!(runlists->data & BIT(i))) 548 continue; 549 550 channels->mthd = NV_DEVICE_HOST_RUNLIST_CHANNELS; 551 channels->data = i; 552 553 ret = nvif_object_mthd(device, NV_DEVICE_V0_INFO, args, 554 __struct_size(args)); 555 if (ret || channels->mthd == NV_DEVICE_INFO_INVALID) 556 return -ENODEV; 557 558 drm->runl[i].chan_nr = channels->data; 559 drm->runl[i].chan_id_base = drm->chan_total; 560 drm->runl[i].context_base = dma_fence_context_alloc(drm->runl[i].chan_nr); 561 562 drm->chan_total += drm->runl[i].chan_nr; 563 } 564 } else { 565 drm->runl[0].context_base = dma_fence_context_alloc(drm->chan_nr); 566 for (i = 1; i < drm->runl_nr; i++) 567 drm->runl[i].context_base = drm->runl[0].context_base; 568 569 } 570 571 return 0; 572 } 573