1 /* 2 * Copyright 2007 Dave Airlied 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 /* 25 * Authors: Dave Airlied <airlied@linux.ie> 26 * Ben Skeggs <darktama@iinet.net.au> 27 * Jeremy Kolb <jkolb@brandeis.edu> 28 */ 29 30 #include "drmP.h" 31 32 #include "nouveau_drm.h" 33 #include "nouveau_drv.h" 34 #include "nouveau_dma.h" 35 36 #include <linux/log2.h> 37 #include <linux/slab.h> 38 39 static void 40 nouveau_bo_del_ttm(struct ttm_buffer_object *bo) 41 { 42 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); 43 struct drm_device *dev = dev_priv->dev; 44 struct nouveau_bo *nvbo = nouveau_bo(bo); 45 46 ttm_bo_kunmap(&nvbo->kmap); 47 48 if (unlikely(nvbo->gem)) 49 DRM_ERROR("bo %p still attached to GEM object\n", bo); 50 51 if (nvbo->tile) 52 nv10_mem_expire_tiling(dev, nvbo->tile, NULL); 53 54 spin_lock(&dev_priv->ttm.bo_list_lock); 55 list_del(&nvbo->head); 56 spin_unlock(&dev_priv->ttm.bo_list_lock); 57 kfree(nvbo); 58 } 59 60 static void 61 nouveau_bo_fixup_align(struct drm_device *dev, 62 uint32_t tile_mode, uint32_t tile_flags, 63 int *align, int *size) 64 { 65 struct drm_nouveau_private *dev_priv = dev->dev_private; 66 67 /* 68 * Some of the tile_flags have a periodic structure of N*4096 bytes, 69 * align to to that as well as the page size. Align the size to the 70 * appropriate boundaries. This does imply that sizes are rounded up 71 * 3-7 pages, so be aware of this and do not waste memory by allocating 72 * many small buffers. 73 */ 74 if (dev_priv->card_type == NV_50) { 75 uint32_t block_size = dev_priv->vram_size >> 15; 76 int i; 77 78 switch (tile_flags) { 79 case 0x1800: 80 case 0x2800: 81 case 0x4800: 82 case 0x7a00: 83 if (is_power_of_2(block_size)) { 84 for (i = 1; i < 10; i++) { 85 *align = 12 * i * block_size; 86 if (!(*align % 65536)) 87 break; 88 } 89 } else { 90 for (i = 1; i < 10; i++) { 91 *align = 8 * i * block_size; 92 if (!(*align % 65536)) 93 break; 94 } 95 } 96 *size = roundup(*size, *align); 97 break; 98 default: 99 break; 100 } 101 102 } else { 103 if (tile_mode) { 104 if (dev_priv->chipset >= 0x40) { 105 *align = 65536; 106 *size = roundup(*size, 64 * tile_mode); 107 108 } else if (dev_priv->chipset >= 0x30) { 109 *align = 32768; 110 *size = roundup(*size, 64 * tile_mode); 111 112 } else if (dev_priv->chipset >= 0x20) { 113 *align = 16384; 114 *size = roundup(*size, 64 * tile_mode); 115 116 } else if (dev_priv->chipset >= 0x10) { 117 *align = 16384; 118 *size = roundup(*size, 32 * tile_mode); 119 } 120 } 121 } 122 123 /* ALIGN works only on powers of two. */ 124 *size = roundup(*size, PAGE_SIZE); 125 126 if (dev_priv->card_type == NV_50) { 127 *size = roundup(*size, 65536); 128 *align = max(65536, *align); 129 } 130 } 131 132 int 133 nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan, 134 int size, int align, uint32_t flags, uint32_t tile_mode, 135 uint32_t tile_flags, bool no_vm, bool mappable, 136 struct nouveau_bo **pnvbo) 137 { 138 struct drm_nouveau_private *dev_priv = dev->dev_private; 139 struct nouveau_bo *nvbo; 140 int ret = 0; 141 142 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL); 143 if (!nvbo) 144 return -ENOMEM; 145 INIT_LIST_HEAD(&nvbo->head); 146 INIT_LIST_HEAD(&nvbo->entry); 147 nvbo->mappable = mappable; 148 nvbo->no_vm = no_vm; 149 nvbo->tile_mode = tile_mode; 150 nvbo->tile_flags = tile_flags; 151 152 nouveau_bo_fixup_align(dev, tile_mode, tile_flags, &align, &size); 153 align >>= PAGE_SHIFT; 154 155 nvbo->placement.fpfn = 0; 156 nvbo->placement.lpfn = mappable ? dev_priv->fb_mappable_pages : 0; 157 nouveau_bo_placement_set(nvbo, flags, 0); 158 159 nvbo->channel = chan; 160 ret = ttm_bo_init(&dev_priv->ttm.bdev, &nvbo->bo, size, 161 ttm_bo_type_device, &nvbo->placement, align, 0, 162 false, NULL, size, nouveau_bo_del_ttm); 163 nvbo->channel = NULL; 164 if (ret) { 165 /* ttm will call nouveau_bo_del_ttm if it fails.. */ 166 return ret; 167 } 168 169 spin_lock(&dev_priv->ttm.bo_list_lock); 170 list_add_tail(&nvbo->head, &dev_priv->ttm.bo_list); 171 spin_unlock(&dev_priv->ttm.bo_list_lock); 172 *pnvbo = nvbo; 173 return 0; 174 } 175 176 static void 177 set_placement_list(uint32_t *pl, unsigned *n, uint32_t type, uint32_t flags) 178 { 179 *n = 0; 180 181 if (type & TTM_PL_FLAG_VRAM) 182 pl[(*n)++] = TTM_PL_FLAG_VRAM | flags; 183 if (type & TTM_PL_FLAG_TT) 184 pl[(*n)++] = TTM_PL_FLAG_TT | flags; 185 if (type & TTM_PL_FLAG_SYSTEM) 186 pl[(*n)++] = TTM_PL_FLAG_SYSTEM | flags; 187 } 188 189 void 190 nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy) 191 { 192 struct ttm_placement *pl = &nvbo->placement; 193 uint32_t flags = TTM_PL_MASK_CACHING | 194 (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0); 195 196 pl->placement = nvbo->placements; 197 set_placement_list(nvbo->placements, &pl->num_placement, 198 type, flags); 199 200 pl->busy_placement = nvbo->busy_placements; 201 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement, 202 type | busy, flags); 203 } 204 205 int 206 nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype) 207 { 208 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev); 209 struct ttm_buffer_object *bo = &nvbo->bo; 210 int ret; 211 212 if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) { 213 NV_ERROR(nouveau_bdev(bo->bdev)->dev, 214 "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo, 215 1 << bo->mem.mem_type, memtype); 216 return -EINVAL; 217 } 218 219 if (nvbo->pin_refcnt++) 220 return 0; 221 222 ret = ttm_bo_reserve(bo, false, false, false, 0); 223 if (ret) 224 goto out; 225 226 nouveau_bo_placement_set(nvbo, memtype, 0); 227 228 ret = ttm_bo_validate(bo, &nvbo->placement, false, false); 229 if (ret == 0) { 230 switch (bo->mem.mem_type) { 231 case TTM_PL_VRAM: 232 dev_priv->fb_aper_free -= bo->mem.size; 233 break; 234 case TTM_PL_TT: 235 dev_priv->gart_info.aper_free -= bo->mem.size; 236 break; 237 default: 238 break; 239 } 240 } 241 ttm_bo_unreserve(bo); 242 out: 243 if (unlikely(ret)) 244 nvbo->pin_refcnt--; 245 return ret; 246 } 247 248 int 249 nouveau_bo_unpin(struct nouveau_bo *nvbo) 250 { 251 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev); 252 struct ttm_buffer_object *bo = &nvbo->bo; 253 int ret; 254 255 if (--nvbo->pin_refcnt) 256 return 0; 257 258 ret = ttm_bo_reserve(bo, false, false, false, 0); 259 if (ret) 260 return ret; 261 262 nouveau_bo_placement_set(nvbo, bo->mem.placement, 0); 263 264 ret = ttm_bo_validate(bo, &nvbo->placement, false, false); 265 if (ret == 0) { 266 switch (bo->mem.mem_type) { 267 case TTM_PL_VRAM: 268 dev_priv->fb_aper_free += bo->mem.size; 269 break; 270 case TTM_PL_TT: 271 dev_priv->gart_info.aper_free += bo->mem.size; 272 break; 273 default: 274 break; 275 } 276 } 277 278 ttm_bo_unreserve(bo); 279 return ret; 280 } 281 282 int 283 nouveau_bo_map(struct nouveau_bo *nvbo) 284 { 285 int ret; 286 287 ret = ttm_bo_reserve(&nvbo->bo, false, false, false, 0); 288 if (ret) 289 return ret; 290 291 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap); 292 ttm_bo_unreserve(&nvbo->bo); 293 return ret; 294 } 295 296 void 297 nouveau_bo_unmap(struct nouveau_bo *nvbo) 298 { 299 ttm_bo_kunmap(&nvbo->kmap); 300 } 301 302 u16 303 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index) 304 { 305 bool is_iomem; 306 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); 307 mem = &mem[index]; 308 if (is_iomem) 309 return ioread16_native((void __force __iomem *)mem); 310 else 311 return *mem; 312 } 313 314 void 315 nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val) 316 { 317 bool is_iomem; 318 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); 319 mem = &mem[index]; 320 if (is_iomem) 321 iowrite16_native(val, (void __force __iomem *)mem); 322 else 323 *mem = val; 324 } 325 326 u32 327 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index) 328 { 329 bool is_iomem; 330 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); 331 mem = &mem[index]; 332 if (is_iomem) 333 return ioread32_native((void __force __iomem *)mem); 334 else 335 return *mem; 336 } 337 338 void 339 nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val) 340 { 341 bool is_iomem; 342 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); 343 mem = &mem[index]; 344 if (is_iomem) 345 iowrite32_native(val, (void __force __iomem *)mem); 346 else 347 *mem = val; 348 } 349 350 static struct ttm_backend * 351 nouveau_bo_create_ttm_backend_entry(struct ttm_bo_device *bdev) 352 { 353 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev); 354 struct drm_device *dev = dev_priv->dev; 355 356 switch (dev_priv->gart_info.type) { 357 #if __OS_HAS_AGP 358 case NOUVEAU_GART_AGP: 359 return ttm_agp_backend_init(bdev, dev->agp->bridge); 360 #endif 361 case NOUVEAU_GART_SGDMA: 362 return nouveau_sgdma_init_ttm(dev); 363 default: 364 NV_ERROR(dev, "Unknown GART type %d\n", 365 dev_priv->gart_info.type); 366 break; 367 } 368 369 return NULL; 370 } 371 372 static int 373 nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) 374 { 375 /* We'll do this from user space. */ 376 return 0; 377 } 378 379 static int 380 nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, 381 struct ttm_mem_type_manager *man) 382 { 383 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev); 384 struct drm_device *dev = dev_priv->dev; 385 386 switch (type) { 387 case TTM_PL_SYSTEM: 388 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; 389 man->available_caching = TTM_PL_MASK_CACHING; 390 man->default_caching = TTM_PL_FLAG_CACHED; 391 break; 392 case TTM_PL_VRAM: 393 man->flags = TTM_MEMTYPE_FLAG_FIXED | 394 TTM_MEMTYPE_FLAG_MAPPABLE | 395 TTM_MEMTYPE_FLAG_NEEDS_IOREMAP; 396 man->available_caching = TTM_PL_FLAG_UNCACHED | 397 TTM_PL_FLAG_WC; 398 man->default_caching = TTM_PL_FLAG_WC; 399 400 man->io_addr = NULL; 401 man->io_offset = drm_get_resource_start(dev, 1); 402 man->io_size = drm_get_resource_len(dev, 1); 403 if (man->io_size > dev_priv->vram_size) 404 man->io_size = dev_priv->vram_size; 405 406 man->gpu_offset = dev_priv->vm_vram_base; 407 break; 408 case TTM_PL_TT: 409 switch (dev_priv->gart_info.type) { 410 case NOUVEAU_GART_AGP: 411 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | 412 TTM_MEMTYPE_FLAG_NEEDS_IOREMAP; 413 man->available_caching = TTM_PL_FLAG_UNCACHED; 414 man->default_caching = TTM_PL_FLAG_UNCACHED; 415 break; 416 case NOUVEAU_GART_SGDMA: 417 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | 418 TTM_MEMTYPE_FLAG_CMA; 419 man->available_caching = TTM_PL_MASK_CACHING; 420 man->default_caching = TTM_PL_FLAG_CACHED; 421 break; 422 default: 423 NV_ERROR(dev, "Unknown GART type: %d\n", 424 dev_priv->gart_info.type); 425 return -EINVAL; 426 } 427 428 man->io_offset = dev_priv->gart_info.aper_base; 429 man->io_size = dev_priv->gart_info.aper_size; 430 man->io_addr = NULL; 431 man->gpu_offset = dev_priv->vm_gart_base; 432 break; 433 default: 434 NV_ERROR(dev, "Unsupported memory type %u\n", (unsigned)type); 435 return -EINVAL; 436 } 437 return 0; 438 } 439 440 static void 441 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl) 442 { 443 struct nouveau_bo *nvbo = nouveau_bo(bo); 444 445 switch (bo->mem.mem_type) { 446 case TTM_PL_VRAM: 447 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT, 448 TTM_PL_FLAG_SYSTEM); 449 break; 450 default: 451 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0); 452 break; 453 } 454 455 *pl = nvbo->placement; 456 } 457 458 459 /* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access 460 * TTM_PL_{VRAM,TT} directly. 461 */ 462 463 static int 464 nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan, 465 struct nouveau_bo *nvbo, bool evict, bool no_wait, 466 struct ttm_mem_reg *new_mem) 467 { 468 struct nouveau_fence *fence = NULL; 469 int ret; 470 471 ret = nouveau_fence_new(chan, &fence, true); 472 if (ret) 473 return ret; 474 475 ret = ttm_bo_move_accel_cleanup(&nvbo->bo, fence, NULL, 476 evict, no_wait, new_mem); 477 if (nvbo->channel && nvbo->channel != chan) 478 ret = nouveau_fence_wait(fence, NULL, false, false); 479 nouveau_fence_unref((void *)&fence); 480 return ret; 481 } 482 483 static inline uint32_t 484 nouveau_bo_mem_ctxdma(struct nouveau_bo *nvbo, struct nouveau_channel *chan, 485 struct ttm_mem_reg *mem) 486 { 487 if (chan == nouveau_bdev(nvbo->bo.bdev)->channel) { 488 if (mem->mem_type == TTM_PL_TT) 489 return NvDmaGART; 490 return NvDmaVRAM; 491 } 492 493 if (mem->mem_type == TTM_PL_TT) 494 return chan->gart_handle; 495 return chan->vram_handle; 496 } 497 498 static int 499 nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr, 500 int no_wait, struct ttm_mem_reg *new_mem) 501 { 502 struct nouveau_bo *nvbo = nouveau_bo(bo); 503 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); 504 struct ttm_mem_reg *old_mem = &bo->mem; 505 struct nouveau_channel *chan; 506 uint64_t src_offset, dst_offset; 507 uint32_t page_count; 508 int ret; 509 510 chan = nvbo->channel; 511 if (!chan || nvbo->tile_flags || nvbo->no_vm) 512 chan = dev_priv->channel; 513 514 src_offset = old_mem->mm_node->start << PAGE_SHIFT; 515 dst_offset = new_mem->mm_node->start << PAGE_SHIFT; 516 if (chan != dev_priv->channel) { 517 if (old_mem->mem_type == TTM_PL_TT) 518 src_offset += dev_priv->vm_gart_base; 519 else 520 src_offset += dev_priv->vm_vram_base; 521 522 if (new_mem->mem_type == TTM_PL_TT) 523 dst_offset += dev_priv->vm_gart_base; 524 else 525 dst_offset += dev_priv->vm_vram_base; 526 } 527 528 ret = RING_SPACE(chan, 3); 529 if (ret) 530 return ret; 531 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2); 532 OUT_RING(chan, nouveau_bo_mem_ctxdma(nvbo, chan, old_mem)); 533 OUT_RING(chan, nouveau_bo_mem_ctxdma(nvbo, chan, new_mem)); 534 535 if (dev_priv->card_type >= NV_50) { 536 ret = RING_SPACE(chan, 4); 537 if (ret) 538 return ret; 539 BEGIN_RING(chan, NvSubM2MF, 0x0200, 1); 540 OUT_RING(chan, 1); 541 BEGIN_RING(chan, NvSubM2MF, 0x021c, 1); 542 OUT_RING(chan, 1); 543 } 544 545 page_count = new_mem->num_pages; 546 while (page_count) { 547 int line_count = (page_count > 2047) ? 2047 : page_count; 548 549 if (dev_priv->card_type >= NV_50) { 550 ret = RING_SPACE(chan, 3); 551 if (ret) 552 return ret; 553 BEGIN_RING(chan, NvSubM2MF, 0x0238, 2); 554 OUT_RING(chan, upper_32_bits(src_offset)); 555 OUT_RING(chan, upper_32_bits(dst_offset)); 556 } 557 ret = RING_SPACE(chan, 11); 558 if (ret) 559 return ret; 560 BEGIN_RING(chan, NvSubM2MF, 561 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8); 562 OUT_RING(chan, lower_32_bits(src_offset)); 563 OUT_RING(chan, lower_32_bits(dst_offset)); 564 OUT_RING(chan, PAGE_SIZE); /* src_pitch */ 565 OUT_RING(chan, PAGE_SIZE); /* dst_pitch */ 566 OUT_RING(chan, PAGE_SIZE); /* line_length */ 567 OUT_RING(chan, line_count); 568 OUT_RING(chan, (1<<8)|(1<<0)); 569 OUT_RING(chan, 0); 570 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); 571 OUT_RING(chan, 0); 572 573 page_count -= line_count; 574 src_offset += (PAGE_SIZE * line_count); 575 dst_offset += (PAGE_SIZE * line_count); 576 } 577 578 return nouveau_bo_move_accel_cleanup(chan, nvbo, evict, no_wait, new_mem); 579 } 580 581 static int 582 nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr, 583 bool no_wait, struct ttm_mem_reg *new_mem) 584 { 585 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING; 586 struct ttm_placement placement; 587 struct ttm_mem_reg tmp_mem; 588 int ret; 589 590 placement.fpfn = placement.lpfn = 0; 591 placement.num_placement = placement.num_busy_placement = 1; 592 placement.placement = placement.busy_placement = &placement_memtype; 593 594 tmp_mem = *new_mem; 595 tmp_mem.mm_node = NULL; 596 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait); 597 if (ret) 598 return ret; 599 600 ret = ttm_tt_bind(bo->ttm, &tmp_mem); 601 if (ret) 602 goto out; 603 604 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait, &tmp_mem); 605 if (ret) 606 goto out; 607 608 ret = ttm_bo_move_ttm(bo, evict, no_wait, new_mem); 609 out: 610 if (tmp_mem.mm_node) { 611 spin_lock(&bo->bdev->glob->lru_lock); 612 drm_mm_put_block(tmp_mem.mm_node); 613 spin_unlock(&bo->bdev->glob->lru_lock); 614 } 615 616 return ret; 617 } 618 619 static int 620 nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr, 621 bool no_wait, struct ttm_mem_reg *new_mem) 622 { 623 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING; 624 struct ttm_placement placement; 625 struct ttm_mem_reg tmp_mem; 626 int ret; 627 628 placement.fpfn = placement.lpfn = 0; 629 placement.num_placement = placement.num_busy_placement = 1; 630 placement.placement = placement.busy_placement = &placement_memtype; 631 632 tmp_mem = *new_mem; 633 tmp_mem.mm_node = NULL; 634 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait); 635 if (ret) 636 return ret; 637 638 ret = ttm_bo_move_ttm(bo, evict, no_wait, &tmp_mem); 639 if (ret) 640 goto out; 641 642 ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait, new_mem); 643 if (ret) 644 goto out; 645 646 out: 647 if (tmp_mem.mm_node) { 648 spin_lock(&bo->bdev->glob->lru_lock); 649 drm_mm_put_block(tmp_mem.mm_node); 650 spin_unlock(&bo->bdev->glob->lru_lock); 651 } 652 653 return ret; 654 } 655 656 static int 657 nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem, 658 struct nouveau_tile_reg **new_tile) 659 { 660 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); 661 struct drm_device *dev = dev_priv->dev; 662 struct nouveau_bo *nvbo = nouveau_bo(bo); 663 uint64_t offset; 664 int ret; 665 666 if (nvbo->no_vm || new_mem->mem_type != TTM_PL_VRAM) { 667 /* Nothing to do. */ 668 *new_tile = NULL; 669 return 0; 670 } 671 672 offset = new_mem->mm_node->start << PAGE_SHIFT; 673 674 if (dev_priv->card_type == NV_50) { 675 ret = nv50_mem_vm_bind_linear(dev, 676 offset + dev_priv->vm_vram_base, 677 new_mem->size, nvbo->tile_flags, 678 offset); 679 if (ret) 680 return ret; 681 682 } else if (dev_priv->card_type >= NV_10) { 683 *new_tile = nv10_mem_set_tiling(dev, offset, new_mem->size, 684 nvbo->tile_mode); 685 } 686 687 return 0; 688 } 689 690 static void 691 nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo, 692 struct nouveau_tile_reg *new_tile, 693 struct nouveau_tile_reg **old_tile) 694 { 695 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); 696 struct drm_device *dev = dev_priv->dev; 697 698 if (dev_priv->card_type >= NV_10 && 699 dev_priv->card_type < NV_50) { 700 if (*old_tile) 701 nv10_mem_expire_tiling(dev, *old_tile, bo->sync_obj); 702 703 *old_tile = new_tile; 704 } 705 } 706 707 static int 708 nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr, 709 bool no_wait, struct ttm_mem_reg *new_mem) 710 { 711 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); 712 struct nouveau_bo *nvbo = nouveau_bo(bo); 713 struct ttm_mem_reg *old_mem = &bo->mem; 714 struct nouveau_tile_reg *new_tile = NULL; 715 int ret = 0; 716 717 ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile); 718 if (ret) 719 return ret; 720 721 /* Software copy if the card isn't up and running yet. */ 722 if (dev_priv->init_state != NOUVEAU_CARD_INIT_DONE || 723 !dev_priv->channel) { 724 ret = ttm_bo_move_memcpy(bo, evict, no_wait, new_mem); 725 goto out; 726 } 727 728 /* Fake bo copy. */ 729 if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) { 730 BUG_ON(bo->mem.mm_node != NULL); 731 bo->mem = *new_mem; 732 new_mem->mm_node = NULL; 733 goto out; 734 } 735 736 /* Hardware assisted copy. */ 737 if (new_mem->mem_type == TTM_PL_SYSTEM) 738 ret = nouveau_bo_move_flipd(bo, evict, intr, no_wait, new_mem); 739 else if (old_mem->mem_type == TTM_PL_SYSTEM) 740 ret = nouveau_bo_move_flips(bo, evict, intr, no_wait, new_mem); 741 else 742 ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait, new_mem); 743 744 if (!ret) 745 goto out; 746 747 /* Fallback to software copy. */ 748 ret = ttm_bo_move_memcpy(bo, evict, no_wait, new_mem); 749 750 out: 751 if (ret) 752 nouveau_bo_vm_cleanup(bo, NULL, &new_tile); 753 else 754 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile); 755 756 return ret; 757 } 758 759 static int 760 nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp) 761 { 762 return 0; 763 } 764 765 struct ttm_bo_driver nouveau_bo_driver = { 766 .create_ttm_backend_entry = nouveau_bo_create_ttm_backend_entry, 767 .invalidate_caches = nouveau_bo_invalidate_caches, 768 .init_mem_type = nouveau_bo_init_mem_type, 769 .evict_flags = nouveau_bo_evict_flags, 770 .move = nouveau_bo_move, 771 .verify_access = nouveau_bo_verify_access, 772 .sync_obj_signaled = nouveau_fence_signalled, 773 .sync_obj_wait = nouveau_fence_wait, 774 .sync_obj_flush = nouveau_fence_flush, 775 .sync_obj_unref = nouveau_fence_unref, 776 .sync_obj_ref = nouveau_fence_ref, 777 }; 778 779