1 /* 2 * Copyright 2007 Dave Airlied 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 /* 25 * Authors: Dave Airlied <airlied@linux.ie> 26 * Ben Skeggs <darktama@iinet.net.au> 27 * Jeremy Kolb <jkolb@brandeis.edu> 28 */ 29 30 #include <linux/dma-mapping.h> 31 32 #include "nouveau_drv.h" 33 #include "nouveau_chan.h" 34 #include "nouveau_fence.h" 35 36 #include "nouveau_bo.h" 37 #include "nouveau_ttm.h" 38 #include "nouveau_gem.h" 39 #include "nouveau_mem.h" 40 #include "nouveau_vmm.h" 41 42 #include <nvif/class.h> 43 #include <nvif/if500b.h> 44 #include <nvif/if900b.h> 45 46 static int nouveau_ttm_tt_bind(struct ttm_device *bdev, struct ttm_tt *ttm, 47 struct ttm_resource *reg); 48 static void nouveau_ttm_tt_unbind(struct ttm_device *bdev, struct ttm_tt *ttm); 49 50 /* 51 * NV10-NV40 tiling helpers 52 */ 53 54 static void 55 nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg, 56 u32 addr, u32 size, u32 pitch, u32 flags) 57 { 58 struct nouveau_drm *drm = nouveau_drm(dev); 59 int i = reg - drm->tile.reg; 60 struct nvkm_fb *fb = nvxx_fb(&drm->client.device); 61 struct nvkm_fb_tile *tile = &fb->tile.region[i]; 62 63 nouveau_fence_unref(®->fence); 64 65 if (tile->pitch) 66 nvkm_fb_tile_fini(fb, i, tile); 67 68 if (pitch) 69 nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile); 70 71 nvkm_fb_tile_prog(fb, i, tile); 72 } 73 74 static struct nouveau_drm_tile * 75 nv10_bo_get_tile_region(struct drm_device *dev, int i) 76 { 77 struct nouveau_drm *drm = nouveau_drm(dev); 78 struct nouveau_drm_tile *tile = &drm->tile.reg[i]; 79 80 spin_lock(&drm->tile.lock); 81 82 if (!tile->used && 83 (!tile->fence || nouveau_fence_done(tile->fence))) 84 tile->used = true; 85 else 86 tile = NULL; 87 88 spin_unlock(&drm->tile.lock); 89 return tile; 90 } 91 92 static void 93 nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile, 94 struct dma_fence *fence) 95 { 96 struct nouveau_drm *drm = nouveau_drm(dev); 97 98 if (tile) { 99 spin_lock(&drm->tile.lock); 100 tile->fence = (struct nouveau_fence *)dma_fence_get(fence); 101 tile->used = false; 102 spin_unlock(&drm->tile.lock); 103 } 104 } 105 106 static struct nouveau_drm_tile * 107 nv10_bo_set_tiling(struct drm_device *dev, u32 addr, 108 u32 size, u32 pitch, u32 zeta) 109 { 110 struct nouveau_drm *drm = nouveau_drm(dev); 111 struct nvkm_fb *fb = nvxx_fb(&drm->client.device); 112 struct nouveau_drm_tile *tile, *found = NULL; 113 int i; 114 115 for (i = 0; i < fb->tile.regions; i++) { 116 tile = nv10_bo_get_tile_region(dev, i); 117 118 if (pitch && !found) { 119 found = tile; 120 continue; 121 122 } else if (tile && fb->tile.region[i].pitch) { 123 /* Kill an unused tile region. */ 124 nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0); 125 } 126 127 nv10_bo_put_tile_region(dev, tile, NULL); 128 } 129 130 if (found) 131 nv10_bo_update_tile_region(dev, found, addr, size, pitch, zeta); 132 return found; 133 } 134 135 static void 136 nouveau_bo_del_ttm(struct ttm_buffer_object *bo) 137 { 138 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 139 struct drm_device *dev = drm->dev; 140 struct nouveau_bo *nvbo = nouveau_bo(bo); 141 142 WARN_ON(nvbo->bo.pin_count > 0); 143 nouveau_bo_del_io_reserve_lru(bo); 144 nv10_bo_put_tile_region(dev, nvbo->tile, NULL); 145 146 /* 147 * If nouveau_bo_new() allocated this buffer, the GEM object was never 148 * initialized, so don't attempt to release it. 149 */ 150 if (bo->base.dev) 151 drm_gem_object_release(&bo->base); 152 153 kfree(nvbo); 154 } 155 156 static inline u64 157 roundup_64(u64 x, u32 y) 158 { 159 x += y - 1; 160 do_div(x, y); 161 return x * y; 162 } 163 164 static void 165 nouveau_bo_fixup_align(struct nouveau_bo *nvbo, int *align, u64 *size) 166 { 167 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 168 struct nvif_device *device = &drm->client.device; 169 170 if (device->info.family < NV_DEVICE_INFO_V0_TESLA) { 171 if (nvbo->mode) { 172 if (device->info.chipset >= 0x40) { 173 *align = 65536; 174 *size = roundup_64(*size, 64 * nvbo->mode); 175 176 } else if (device->info.chipset >= 0x30) { 177 *align = 32768; 178 *size = roundup_64(*size, 64 * nvbo->mode); 179 180 } else if (device->info.chipset >= 0x20) { 181 *align = 16384; 182 *size = roundup_64(*size, 64 * nvbo->mode); 183 184 } else if (device->info.chipset >= 0x10) { 185 *align = 16384; 186 *size = roundup_64(*size, 32 * nvbo->mode); 187 } 188 } 189 } else { 190 *size = roundup_64(*size, (1 << nvbo->page)); 191 *align = max((1 << nvbo->page), *align); 192 } 193 194 *size = roundup_64(*size, PAGE_SIZE); 195 } 196 197 struct nouveau_bo * 198 nouveau_bo_alloc(struct nouveau_cli *cli, u64 *size, int *align, u32 domain, 199 u32 tile_mode, u32 tile_flags) 200 { 201 struct nouveau_drm *drm = cli->drm; 202 struct nouveau_bo *nvbo; 203 struct nvif_mmu *mmu = &cli->mmu; 204 struct nvif_vmm *vmm = cli->svm.cli ? &cli->svm.vmm : &cli->vmm.vmm; 205 int i, pi = -1; 206 207 if (!*size) { 208 NV_WARN(drm, "skipped size %016llx\n", *size); 209 return ERR_PTR(-EINVAL); 210 } 211 212 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL); 213 if (!nvbo) 214 return ERR_PTR(-ENOMEM); 215 INIT_LIST_HEAD(&nvbo->head); 216 INIT_LIST_HEAD(&nvbo->entry); 217 INIT_LIST_HEAD(&nvbo->vma_list); 218 nvbo->bo.bdev = &drm->ttm.bdev; 219 220 /* This is confusing, and doesn't actually mean we want an uncached 221 * mapping, but is what NOUVEAU_GEM_DOMAIN_COHERENT gets translated 222 * into in nouveau_gem_new(). 223 */ 224 if (domain & NOUVEAU_GEM_DOMAIN_COHERENT) { 225 /* Determine if we can get a cache-coherent map, forcing 226 * uncached mapping if we can't. 227 */ 228 if (!nouveau_drm_use_coherent_gpu_mapping(drm)) 229 nvbo->force_coherent = true; 230 } 231 232 if (cli->device.info.family >= NV_DEVICE_INFO_V0_FERMI) { 233 nvbo->kind = (tile_flags & 0x0000ff00) >> 8; 234 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) { 235 kfree(nvbo); 236 return ERR_PTR(-EINVAL); 237 } 238 239 nvbo->comp = mmu->kind[nvbo->kind] != nvbo->kind; 240 } else 241 if (cli->device.info.family >= NV_DEVICE_INFO_V0_TESLA) { 242 nvbo->kind = (tile_flags & 0x00007f00) >> 8; 243 nvbo->comp = (tile_flags & 0x00030000) >> 16; 244 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) { 245 kfree(nvbo); 246 return ERR_PTR(-EINVAL); 247 } 248 } else { 249 nvbo->zeta = (tile_flags & 0x00000007); 250 } 251 nvbo->mode = tile_mode; 252 nvbo->contig = !(tile_flags & NOUVEAU_GEM_TILE_NONCONTIG); 253 254 /* Determine the desirable target GPU page size for the buffer. */ 255 for (i = 0; i < vmm->page_nr; i++) { 256 /* Because we cannot currently allow VMM maps to fail 257 * during buffer migration, we need to determine page 258 * size for the buffer up-front, and pre-allocate its 259 * page tables. 260 * 261 * Skip page sizes that can't support needed domains. 262 */ 263 if (cli->device.info.family > NV_DEVICE_INFO_V0_CURIE && 264 (domain & NOUVEAU_GEM_DOMAIN_VRAM) && !vmm->page[i].vram) 265 continue; 266 if ((domain & NOUVEAU_GEM_DOMAIN_GART) && 267 (!vmm->page[i].host || vmm->page[i].shift > PAGE_SHIFT)) 268 continue; 269 270 /* Select this page size if it's the first that supports 271 * the potential memory domains, or when it's compatible 272 * with the requested compression settings. 273 */ 274 if (pi < 0 || !nvbo->comp || vmm->page[i].comp) 275 pi = i; 276 277 /* Stop once the buffer is larger than the current page size. */ 278 if (*size >= 1ULL << vmm->page[i].shift) 279 break; 280 } 281 282 if (WARN_ON(pi < 0)) 283 return ERR_PTR(-EINVAL); 284 285 /* Disable compression if suitable settings couldn't be found. */ 286 if (nvbo->comp && !vmm->page[pi].comp) { 287 if (mmu->object.oclass >= NVIF_CLASS_MMU_GF100) 288 nvbo->kind = mmu->kind[nvbo->kind]; 289 nvbo->comp = 0; 290 } 291 nvbo->page = vmm->page[pi].shift; 292 293 nouveau_bo_fixup_align(nvbo, align, size); 294 295 return nvbo; 296 } 297 298 int 299 nouveau_bo_init(struct nouveau_bo *nvbo, u64 size, int align, u32 domain, 300 struct sg_table *sg, struct dma_resv *robj) 301 { 302 int type = sg ? ttm_bo_type_sg : ttm_bo_type_device; 303 int ret; 304 305 nvbo->bo.mem.num_pages = size >> PAGE_SHIFT; 306 nouveau_bo_placement_set(nvbo, domain, 0); 307 INIT_LIST_HEAD(&nvbo->io_reserve_lru); 308 309 ret = ttm_bo_init(nvbo->bo.bdev, &nvbo->bo, size, type, 310 &nvbo->placement, align >> PAGE_SHIFT, false, sg, 311 robj, nouveau_bo_del_ttm); 312 if (ret) { 313 /* ttm will call nouveau_bo_del_ttm if it fails.. */ 314 return ret; 315 } 316 317 return 0; 318 } 319 320 int 321 nouveau_bo_new(struct nouveau_cli *cli, u64 size, int align, 322 uint32_t domain, uint32_t tile_mode, uint32_t tile_flags, 323 struct sg_table *sg, struct dma_resv *robj, 324 struct nouveau_bo **pnvbo) 325 { 326 struct nouveau_bo *nvbo; 327 int ret; 328 329 nvbo = nouveau_bo_alloc(cli, &size, &align, domain, tile_mode, 330 tile_flags); 331 if (IS_ERR(nvbo)) 332 return PTR_ERR(nvbo); 333 334 ret = nouveau_bo_init(nvbo, size, align, domain, sg, robj); 335 if (ret) 336 return ret; 337 338 *pnvbo = nvbo; 339 return 0; 340 } 341 342 static void 343 set_placement_list(struct ttm_place *pl, unsigned *n, uint32_t domain) 344 { 345 *n = 0; 346 347 if (domain & NOUVEAU_GEM_DOMAIN_VRAM) { 348 pl[*n].mem_type = TTM_PL_VRAM; 349 pl[*n].flags = 0; 350 (*n)++; 351 } 352 if (domain & NOUVEAU_GEM_DOMAIN_GART) { 353 pl[*n].mem_type = TTM_PL_TT; 354 pl[*n].flags = 0; 355 (*n)++; 356 } 357 if (domain & NOUVEAU_GEM_DOMAIN_CPU) { 358 pl[*n].mem_type = TTM_PL_SYSTEM; 359 pl[(*n)++].flags = 0; 360 } 361 } 362 363 static void 364 set_placement_range(struct nouveau_bo *nvbo, uint32_t domain) 365 { 366 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 367 u32 vram_pages = drm->client.device.info.ram_size >> PAGE_SHIFT; 368 unsigned i, fpfn, lpfn; 369 370 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS && 371 nvbo->mode && (domain & NOUVEAU_GEM_DOMAIN_VRAM) && 372 nvbo->bo.mem.num_pages < vram_pages / 4) { 373 /* 374 * Make sure that the color and depth buffers are handled 375 * by independent memory controller units. Up to a 9x 376 * speed up when alpha-blending and depth-test are enabled 377 * at the same time. 378 */ 379 if (nvbo->zeta) { 380 fpfn = vram_pages / 2; 381 lpfn = ~0; 382 } else { 383 fpfn = 0; 384 lpfn = vram_pages / 2; 385 } 386 for (i = 0; i < nvbo->placement.num_placement; ++i) { 387 nvbo->placements[i].fpfn = fpfn; 388 nvbo->placements[i].lpfn = lpfn; 389 } 390 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) { 391 nvbo->busy_placements[i].fpfn = fpfn; 392 nvbo->busy_placements[i].lpfn = lpfn; 393 } 394 } 395 } 396 397 void 398 nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t domain, 399 uint32_t busy) 400 { 401 struct ttm_placement *pl = &nvbo->placement; 402 403 pl->placement = nvbo->placements; 404 set_placement_list(nvbo->placements, &pl->num_placement, domain); 405 406 pl->busy_placement = nvbo->busy_placements; 407 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement, 408 domain | busy); 409 410 set_placement_range(nvbo, domain); 411 } 412 413 int 414 nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t domain, bool contig) 415 { 416 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 417 struct ttm_buffer_object *bo = &nvbo->bo; 418 bool force = false, evict = false; 419 int ret; 420 421 ret = ttm_bo_reserve(bo, false, false, NULL); 422 if (ret) 423 return ret; 424 425 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA && 426 domain == NOUVEAU_GEM_DOMAIN_VRAM && contig) { 427 if (!nvbo->contig) { 428 nvbo->contig = true; 429 force = true; 430 evict = true; 431 } 432 } 433 434 if (nvbo->bo.pin_count) { 435 bool error = evict; 436 437 switch (bo->mem.mem_type) { 438 case TTM_PL_VRAM: 439 error |= !(domain & NOUVEAU_GEM_DOMAIN_VRAM); 440 break; 441 case TTM_PL_TT: 442 error |= !(domain & NOUVEAU_GEM_DOMAIN_GART); 443 default: 444 break; 445 } 446 447 if (error) { 448 NV_ERROR(drm, "bo %p pinned elsewhere: " 449 "0x%08x vs 0x%08x\n", bo, 450 bo->mem.mem_type, domain); 451 ret = -EBUSY; 452 } 453 ttm_bo_pin(&nvbo->bo); 454 goto out; 455 } 456 457 if (evict) { 458 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART, 0); 459 ret = nouveau_bo_validate(nvbo, false, false); 460 if (ret) 461 goto out; 462 } 463 464 nouveau_bo_placement_set(nvbo, domain, 0); 465 ret = nouveau_bo_validate(nvbo, false, false); 466 if (ret) 467 goto out; 468 469 ttm_bo_pin(&nvbo->bo); 470 471 switch (bo->mem.mem_type) { 472 case TTM_PL_VRAM: 473 drm->gem.vram_available -= bo->base.size; 474 break; 475 case TTM_PL_TT: 476 drm->gem.gart_available -= bo->base.size; 477 break; 478 default: 479 break; 480 } 481 482 out: 483 if (force && ret) 484 nvbo->contig = false; 485 ttm_bo_unreserve(bo); 486 return ret; 487 } 488 489 int 490 nouveau_bo_unpin(struct nouveau_bo *nvbo) 491 { 492 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 493 struct ttm_buffer_object *bo = &nvbo->bo; 494 int ret; 495 496 ret = ttm_bo_reserve(bo, false, false, NULL); 497 if (ret) 498 return ret; 499 500 ttm_bo_unpin(&nvbo->bo); 501 if (!nvbo->bo.pin_count) { 502 switch (bo->mem.mem_type) { 503 case TTM_PL_VRAM: 504 drm->gem.vram_available += bo->base.size; 505 break; 506 case TTM_PL_TT: 507 drm->gem.gart_available += bo->base.size; 508 break; 509 default: 510 break; 511 } 512 } 513 514 ttm_bo_unreserve(bo); 515 return 0; 516 } 517 518 int 519 nouveau_bo_map(struct nouveau_bo *nvbo) 520 { 521 int ret; 522 523 ret = ttm_bo_reserve(&nvbo->bo, false, false, NULL); 524 if (ret) 525 return ret; 526 527 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap); 528 529 ttm_bo_unreserve(&nvbo->bo); 530 return ret; 531 } 532 533 void 534 nouveau_bo_unmap(struct nouveau_bo *nvbo) 535 { 536 if (!nvbo) 537 return; 538 539 ttm_bo_kunmap(&nvbo->kmap); 540 } 541 542 void 543 nouveau_bo_sync_for_device(struct nouveau_bo *nvbo) 544 { 545 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 546 struct ttm_tt *ttm_dma = (struct ttm_tt *)nvbo->bo.ttm; 547 int i, j; 548 549 if (!ttm_dma) 550 return; 551 552 /* Don't waste time looping if the object is coherent */ 553 if (nvbo->force_coherent) 554 return; 555 556 i = 0; 557 while (i < ttm_dma->num_pages) { 558 struct page *p = ttm_dma->pages[i]; 559 size_t num_pages = 1; 560 561 for (j = i + 1; j < ttm_dma->num_pages; ++j) { 562 if (++p != ttm_dma->pages[j]) 563 break; 564 565 ++num_pages; 566 } 567 dma_sync_single_for_device(drm->dev->dev, 568 ttm_dma->dma_address[i], 569 num_pages * PAGE_SIZE, DMA_TO_DEVICE); 570 i += num_pages; 571 } 572 } 573 574 void 575 nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo) 576 { 577 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 578 struct ttm_tt *ttm_dma = (struct ttm_tt *)nvbo->bo.ttm; 579 int i, j; 580 581 if (!ttm_dma) 582 return; 583 584 /* Don't waste time looping if the object is coherent */ 585 if (nvbo->force_coherent) 586 return; 587 588 i = 0; 589 while (i < ttm_dma->num_pages) { 590 struct page *p = ttm_dma->pages[i]; 591 size_t num_pages = 1; 592 593 for (j = i + 1; j < ttm_dma->num_pages; ++j) { 594 if (++p != ttm_dma->pages[j]) 595 break; 596 597 ++num_pages; 598 } 599 600 dma_sync_single_for_cpu(drm->dev->dev, ttm_dma->dma_address[i], 601 num_pages * PAGE_SIZE, DMA_FROM_DEVICE); 602 i += num_pages; 603 } 604 } 605 606 void nouveau_bo_add_io_reserve_lru(struct ttm_buffer_object *bo) 607 { 608 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 609 struct nouveau_bo *nvbo = nouveau_bo(bo); 610 611 mutex_lock(&drm->ttm.io_reserve_mutex); 612 list_move_tail(&nvbo->io_reserve_lru, &drm->ttm.io_reserve_lru); 613 mutex_unlock(&drm->ttm.io_reserve_mutex); 614 } 615 616 void nouveau_bo_del_io_reserve_lru(struct ttm_buffer_object *bo) 617 { 618 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 619 struct nouveau_bo *nvbo = nouveau_bo(bo); 620 621 mutex_lock(&drm->ttm.io_reserve_mutex); 622 list_del_init(&nvbo->io_reserve_lru); 623 mutex_unlock(&drm->ttm.io_reserve_mutex); 624 } 625 626 int 627 nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible, 628 bool no_wait_gpu) 629 { 630 struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu }; 631 int ret; 632 633 ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, &ctx); 634 if (ret) 635 return ret; 636 637 nouveau_bo_sync_for_device(nvbo); 638 639 return 0; 640 } 641 642 void 643 nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val) 644 { 645 bool is_iomem; 646 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); 647 648 mem += index; 649 650 if (is_iomem) 651 iowrite16_native(val, (void __force __iomem *)mem); 652 else 653 *mem = val; 654 } 655 656 u32 657 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index) 658 { 659 bool is_iomem; 660 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); 661 662 mem += index; 663 664 if (is_iomem) 665 return ioread32_native((void __force __iomem *)mem); 666 else 667 return *mem; 668 } 669 670 void 671 nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val) 672 { 673 bool is_iomem; 674 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); 675 676 mem += index; 677 678 if (is_iomem) 679 iowrite32_native(val, (void __force __iomem *)mem); 680 else 681 *mem = val; 682 } 683 684 static struct ttm_tt * 685 nouveau_ttm_tt_create(struct ttm_buffer_object *bo, uint32_t page_flags) 686 { 687 #if IS_ENABLED(CONFIG_AGP) 688 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 689 690 if (drm->agp.bridge) { 691 return ttm_agp_tt_create(bo, drm->agp.bridge, page_flags); 692 } 693 #endif 694 695 return nouveau_sgdma_create_ttm(bo, page_flags); 696 } 697 698 static int 699 nouveau_ttm_tt_bind(struct ttm_device *bdev, struct ttm_tt *ttm, 700 struct ttm_resource *reg) 701 { 702 #if IS_ENABLED(CONFIG_AGP) 703 struct nouveau_drm *drm = nouveau_bdev(bdev); 704 #endif 705 if (!reg) 706 return -EINVAL; 707 #if IS_ENABLED(CONFIG_AGP) 708 if (drm->agp.bridge) 709 return ttm_agp_bind(ttm, reg); 710 #endif 711 return nouveau_sgdma_bind(bdev, ttm, reg); 712 } 713 714 static void 715 nouveau_ttm_tt_unbind(struct ttm_device *bdev, struct ttm_tt *ttm) 716 { 717 #if IS_ENABLED(CONFIG_AGP) 718 struct nouveau_drm *drm = nouveau_bdev(bdev); 719 720 if (drm->agp.bridge) { 721 ttm_agp_unbind(ttm); 722 return; 723 } 724 #endif 725 nouveau_sgdma_unbind(bdev, ttm); 726 } 727 728 static void 729 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl) 730 { 731 struct nouveau_bo *nvbo = nouveau_bo(bo); 732 733 switch (bo->mem.mem_type) { 734 case TTM_PL_VRAM: 735 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART, 736 NOUVEAU_GEM_DOMAIN_CPU); 737 break; 738 default: 739 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_CPU, 0); 740 break; 741 } 742 743 *pl = nvbo->placement; 744 } 745 746 static int 747 nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo, 748 struct ttm_resource *reg) 749 { 750 struct nouveau_mem *old_mem = nouveau_mem(&bo->mem); 751 struct nouveau_mem *new_mem = nouveau_mem(reg); 752 struct nvif_vmm *vmm = &drm->client.vmm.vmm; 753 int ret; 754 755 ret = nvif_vmm_get(vmm, LAZY, false, old_mem->mem.page, 0, 756 old_mem->mem.size, &old_mem->vma[0]); 757 if (ret) 758 return ret; 759 760 ret = nvif_vmm_get(vmm, LAZY, false, new_mem->mem.page, 0, 761 new_mem->mem.size, &old_mem->vma[1]); 762 if (ret) 763 goto done; 764 765 ret = nouveau_mem_map(old_mem, vmm, &old_mem->vma[0]); 766 if (ret) 767 goto done; 768 769 ret = nouveau_mem_map(new_mem, vmm, &old_mem->vma[1]); 770 done: 771 if (ret) { 772 nvif_vmm_put(vmm, &old_mem->vma[1]); 773 nvif_vmm_put(vmm, &old_mem->vma[0]); 774 } 775 return 0; 776 } 777 778 static int 779 nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, 780 struct ttm_operation_ctx *ctx, 781 struct ttm_resource *new_reg) 782 { 783 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 784 struct nouveau_channel *chan = drm->ttm.chan; 785 struct nouveau_cli *cli = (void *)chan->user.client; 786 struct nouveau_fence *fence; 787 int ret; 788 789 /* create temporary vmas for the transfer and attach them to the 790 * old nvkm_mem node, these will get cleaned up after ttm has 791 * destroyed the ttm_resource 792 */ 793 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) { 794 ret = nouveau_bo_move_prep(drm, bo, new_reg); 795 if (ret) 796 return ret; 797 } 798 799 if (drm_drv_uses_atomic_modeset(drm->dev)) 800 mutex_lock(&cli->mutex); 801 else 802 mutex_lock_nested(&cli->mutex, SINGLE_DEPTH_NESTING); 803 ret = nouveau_fence_sync(nouveau_bo(bo), chan, true, ctx->interruptible); 804 if (ret == 0) { 805 ret = drm->ttm.move(chan, bo, &bo->mem, new_reg); 806 if (ret == 0) { 807 ret = nouveau_fence_new(chan, false, &fence); 808 if (ret == 0) { 809 ret = ttm_bo_move_accel_cleanup(bo, 810 &fence->base, 811 evict, false, 812 new_reg); 813 nouveau_fence_unref(&fence); 814 } 815 } 816 } 817 mutex_unlock(&cli->mutex); 818 return ret; 819 } 820 821 void 822 nouveau_bo_move_init(struct nouveau_drm *drm) 823 { 824 static const struct _method_table { 825 const char *name; 826 int engine; 827 s32 oclass; 828 int (*exec)(struct nouveau_channel *, 829 struct ttm_buffer_object *, 830 struct ttm_resource *, struct ttm_resource *); 831 int (*init)(struct nouveau_channel *, u32 handle); 832 } _methods[] = { 833 { "COPY", 4, 0xc5b5, nve0_bo_move_copy, nve0_bo_move_init }, 834 { "GRCE", 0, 0xc5b5, nve0_bo_move_copy, nvc0_bo_move_init }, 835 { "COPY", 4, 0xc3b5, nve0_bo_move_copy, nve0_bo_move_init }, 836 { "GRCE", 0, 0xc3b5, nve0_bo_move_copy, nvc0_bo_move_init }, 837 { "COPY", 4, 0xc1b5, nve0_bo_move_copy, nve0_bo_move_init }, 838 { "GRCE", 0, 0xc1b5, nve0_bo_move_copy, nvc0_bo_move_init }, 839 { "COPY", 4, 0xc0b5, nve0_bo_move_copy, nve0_bo_move_init }, 840 { "GRCE", 0, 0xc0b5, nve0_bo_move_copy, nvc0_bo_move_init }, 841 { "COPY", 4, 0xb0b5, nve0_bo_move_copy, nve0_bo_move_init }, 842 { "GRCE", 0, 0xb0b5, nve0_bo_move_copy, nvc0_bo_move_init }, 843 { "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init }, 844 { "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init }, 845 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init }, 846 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init }, 847 { "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init }, 848 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init }, 849 { "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init }, 850 { "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init }, 851 { "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init }, 852 {}, 853 }; 854 const struct _method_table *mthd = _methods; 855 const char *name = "CPU"; 856 int ret; 857 858 do { 859 struct nouveau_channel *chan; 860 861 if (mthd->engine) 862 chan = drm->cechan; 863 else 864 chan = drm->channel; 865 if (chan == NULL) 866 continue; 867 868 ret = nvif_object_ctor(&chan->user, "ttmBoMove", 869 mthd->oclass | (mthd->engine << 16), 870 mthd->oclass, NULL, 0, 871 &drm->ttm.copy); 872 if (ret == 0) { 873 ret = mthd->init(chan, drm->ttm.copy.handle); 874 if (ret) { 875 nvif_object_dtor(&drm->ttm.copy); 876 continue; 877 } 878 879 drm->ttm.move = mthd->exec; 880 drm->ttm.chan = chan; 881 name = mthd->name; 882 break; 883 } 884 } while ((++mthd)->exec); 885 886 NV_INFO(drm, "MM: using %s for buffer copies\n", name); 887 } 888 889 static void nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, 890 struct ttm_resource *new_reg) 891 { 892 struct nouveau_mem *mem = new_reg ? nouveau_mem(new_reg) : NULL; 893 struct nouveau_bo *nvbo = nouveau_bo(bo); 894 struct nouveau_vma *vma; 895 896 /* ttm can now (stupidly) pass the driver bos it didn't create... */ 897 if (bo->destroy != nouveau_bo_del_ttm) 898 return; 899 900 nouveau_bo_del_io_reserve_lru(bo); 901 902 if (mem && new_reg->mem_type != TTM_PL_SYSTEM && 903 mem->mem.page == nvbo->page) { 904 list_for_each_entry(vma, &nvbo->vma_list, head) { 905 nouveau_vma_map(vma, mem); 906 } 907 } else { 908 list_for_each_entry(vma, &nvbo->vma_list, head) { 909 WARN_ON(ttm_bo_wait(bo, false, false)); 910 nouveau_vma_unmap(vma); 911 } 912 } 913 914 if (new_reg) { 915 if (new_reg->mm_node) 916 nvbo->offset = (new_reg->start << PAGE_SHIFT); 917 else 918 nvbo->offset = 0; 919 } 920 921 } 922 923 static int 924 nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_resource *new_reg, 925 struct nouveau_drm_tile **new_tile) 926 { 927 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 928 struct drm_device *dev = drm->dev; 929 struct nouveau_bo *nvbo = nouveau_bo(bo); 930 u64 offset = new_reg->start << PAGE_SHIFT; 931 932 *new_tile = NULL; 933 if (new_reg->mem_type != TTM_PL_VRAM) 934 return 0; 935 936 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { 937 *new_tile = nv10_bo_set_tiling(dev, offset, bo->base.size, 938 nvbo->mode, nvbo->zeta); 939 } 940 941 return 0; 942 } 943 944 static void 945 nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo, 946 struct nouveau_drm_tile *new_tile, 947 struct nouveau_drm_tile **old_tile) 948 { 949 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 950 struct drm_device *dev = drm->dev; 951 struct dma_fence *fence = dma_resv_get_excl(bo->base.resv); 952 953 nv10_bo_put_tile_region(dev, *old_tile, fence); 954 *old_tile = new_tile; 955 } 956 957 static int 958 nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, 959 struct ttm_operation_ctx *ctx, 960 struct ttm_resource *new_reg, 961 struct ttm_place *hop) 962 { 963 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 964 struct nouveau_bo *nvbo = nouveau_bo(bo); 965 struct ttm_resource *old_reg = &bo->mem; 966 struct nouveau_drm_tile *new_tile = NULL; 967 int ret = 0; 968 969 970 if (new_reg->mem_type == TTM_PL_TT) { 971 ret = nouveau_ttm_tt_bind(bo->bdev, bo->ttm, new_reg); 972 if (ret) 973 return ret; 974 } 975 976 nouveau_bo_move_ntfy(bo, new_reg); 977 ret = ttm_bo_wait_ctx(bo, ctx); 978 if (ret) 979 goto out_ntfy; 980 981 if (nvbo->bo.pin_count) 982 NV_WARN(drm, "Moving pinned object %p!\n", nvbo); 983 984 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) { 985 ret = nouveau_bo_vm_bind(bo, new_reg, &new_tile); 986 if (ret) 987 goto out_ntfy; 988 } 989 990 /* Fake bo copy. */ 991 if (old_reg->mem_type == TTM_PL_SYSTEM && !bo->ttm) { 992 ttm_bo_move_null(bo, new_reg); 993 goto out; 994 } 995 996 if (old_reg->mem_type == TTM_PL_SYSTEM && 997 new_reg->mem_type == TTM_PL_TT) { 998 ttm_bo_move_null(bo, new_reg); 999 goto out; 1000 } 1001 1002 if (old_reg->mem_type == TTM_PL_TT && 1003 new_reg->mem_type == TTM_PL_SYSTEM) { 1004 nouveau_ttm_tt_unbind(bo->bdev, bo->ttm); 1005 ttm_resource_free(bo, &bo->mem); 1006 ttm_bo_assign_mem(bo, new_reg); 1007 goto out; 1008 } 1009 1010 /* Hardware assisted copy. */ 1011 if (drm->ttm.move) { 1012 if ((old_reg->mem_type == TTM_PL_SYSTEM && 1013 new_reg->mem_type == TTM_PL_VRAM) || 1014 (old_reg->mem_type == TTM_PL_VRAM && 1015 new_reg->mem_type == TTM_PL_SYSTEM)) { 1016 hop->fpfn = 0; 1017 hop->lpfn = 0; 1018 hop->mem_type = TTM_PL_TT; 1019 hop->flags = 0; 1020 return -EMULTIHOP; 1021 } 1022 ret = nouveau_bo_move_m2mf(bo, evict, ctx, 1023 new_reg); 1024 } else 1025 ret = -ENODEV; 1026 1027 if (ret) { 1028 /* Fallback to software copy. */ 1029 ret = ttm_bo_move_memcpy(bo, ctx, new_reg); 1030 } 1031 1032 out: 1033 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) { 1034 if (ret) 1035 nouveau_bo_vm_cleanup(bo, NULL, &new_tile); 1036 else 1037 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile); 1038 } 1039 out_ntfy: 1040 if (ret) { 1041 nouveau_bo_move_ntfy(bo, &bo->mem); 1042 } 1043 return ret; 1044 } 1045 1046 static int 1047 nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp) 1048 { 1049 struct nouveau_bo *nvbo = nouveau_bo(bo); 1050 1051 return drm_vma_node_verify_access(&nvbo->bo.base.vma_node, 1052 filp->private_data); 1053 } 1054 1055 static void 1056 nouveau_ttm_io_mem_free_locked(struct nouveau_drm *drm, 1057 struct ttm_resource *reg) 1058 { 1059 struct nouveau_mem *mem = nouveau_mem(reg); 1060 1061 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) { 1062 switch (reg->mem_type) { 1063 case TTM_PL_TT: 1064 if (mem->kind) 1065 nvif_object_unmap_handle(&mem->mem.object); 1066 break; 1067 case TTM_PL_VRAM: 1068 nvif_object_unmap_handle(&mem->mem.object); 1069 break; 1070 default: 1071 break; 1072 } 1073 } 1074 } 1075 1076 static int 1077 nouveau_ttm_io_mem_reserve(struct ttm_device *bdev, struct ttm_resource *reg) 1078 { 1079 struct nouveau_drm *drm = nouveau_bdev(bdev); 1080 struct nvkm_device *device = nvxx_device(&drm->client.device); 1081 struct nouveau_mem *mem = nouveau_mem(reg); 1082 struct nvif_mmu *mmu = &drm->client.mmu; 1083 int ret; 1084 1085 mutex_lock(&drm->ttm.io_reserve_mutex); 1086 retry: 1087 switch (reg->mem_type) { 1088 case TTM_PL_SYSTEM: 1089 /* System memory */ 1090 ret = 0; 1091 goto out; 1092 case TTM_PL_TT: 1093 #if IS_ENABLED(CONFIG_AGP) 1094 if (drm->agp.bridge) { 1095 reg->bus.offset = (reg->start << PAGE_SHIFT) + 1096 drm->agp.base; 1097 reg->bus.is_iomem = !drm->agp.cma; 1098 reg->bus.caching = ttm_write_combined; 1099 } 1100 #endif 1101 if (drm->client.mem->oclass < NVIF_CLASS_MEM_NV50 || 1102 !mem->kind) { 1103 /* untiled */ 1104 ret = 0; 1105 break; 1106 } 1107 fallthrough; /* tiled memory */ 1108 case TTM_PL_VRAM: 1109 reg->bus.offset = (reg->start << PAGE_SHIFT) + 1110 device->func->resource_addr(device, 1); 1111 reg->bus.is_iomem = true; 1112 1113 /* Some BARs do not support being ioremapped WC */ 1114 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA && 1115 mmu->type[drm->ttm.type_vram].type & NVIF_MEM_UNCACHED) 1116 reg->bus.caching = ttm_uncached; 1117 else 1118 reg->bus.caching = ttm_write_combined; 1119 1120 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) { 1121 union { 1122 struct nv50_mem_map_v0 nv50; 1123 struct gf100_mem_map_v0 gf100; 1124 } args; 1125 u64 handle, length; 1126 u32 argc = 0; 1127 1128 switch (mem->mem.object.oclass) { 1129 case NVIF_CLASS_MEM_NV50: 1130 args.nv50.version = 0; 1131 args.nv50.ro = 0; 1132 args.nv50.kind = mem->kind; 1133 args.nv50.comp = mem->comp; 1134 argc = sizeof(args.nv50); 1135 break; 1136 case NVIF_CLASS_MEM_GF100: 1137 args.gf100.version = 0; 1138 args.gf100.ro = 0; 1139 args.gf100.kind = mem->kind; 1140 argc = sizeof(args.gf100); 1141 break; 1142 default: 1143 WARN_ON(1); 1144 break; 1145 } 1146 1147 ret = nvif_object_map_handle(&mem->mem.object, 1148 &args, argc, 1149 &handle, &length); 1150 if (ret != 1) { 1151 if (WARN_ON(ret == 0)) 1152 ret = -EINVAL; 1153 goto out; 1154 } 1155 1156 reg->bus.offset = handle; 1157 } 1158 ret = 0; 1159 break; 1160 default: 1161 ret = -EINVAL; 1162 } 1163 1164 out: 1165 if (ret == -ENOSPC) { 1166 struct nouveau_bo *nvbo; 1167 1168 nvbo = list_first_entry_or_null(&drm->ttm.io_reserve_lru, 1169 typeof(*nvbo), 1170 io_reserve_lru); 1171 if (nvbo) { 1172 list_del_init(&nvbo->io_reserve_lru); 1173 drm_vma_node_unmap(&nvbo->bo.base.vma_node, 1174 bdev->dev_mapping); 1175 nouveau_ttm_io_mem_free_locked(drm, &nvbo->bo.mem); 1176 goto retry; 1177 } 1178 1179 } 1180 mutex_unlock(&drm->ttm.io_reserve_mutex); 1181 return ret; 1182 } 1183 1184 static void 1185 nouveau_ttm_io_mem_free(struct ttm_device *bdev, struct ttm_resource *reg) 1186 { 1187 struct nouveau_drm *drm = nouveau_bdev(bdev); 1188 1189 mutex_lock(&drm->ttm.io_reserve_mutex); 1190 nouveau_ttm_io_mem_free_locked(drm, reg); 1191 mutex_unlock(&drm->ttm.io_reserve_mutex); 1192 } 1193 1194 vm_fault_t nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo) 1195 { 1196 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 1197 struct nouveau_bo *nvbo = nouveau_bo(bo); 1198 struct nvkm_device *device = nvxx_device(&drm->client.device); 1199 u32 mappable = device->func->resource_size(device, 1) >> PAGE_SHIFT; 1200 int i, ret; 1201 1202 /* as long as the bo isn't in vram, and isn't tiled, we've got 1203 * nothing to do here. 1204 */ 1205 if (bo->mem.mem_type != TTM_PL_VRAM) { 1206 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA || 1207 !nvbo->kind) 1208 return 0; 1209 1210 if (bo->mem.mem_type != TTM_PL_SYSTEM) 1211 return 0; 1212 1213 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART, 0); 1214 1215 } else { 1216 /* make sure bo is in mappable vram */ 1217 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA || 1218 bo->mem.start + bo->mem.num_pages < mappable) 1219 return 0; 1220 1221 for (i = 0; i < nvbo->placement.num_placement; ++i) { 1222 nvbo->placements[i].fpfn = 0; 1223 nvbo->placements[i].lpfn = mappable; 1224 } 1225 1226 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) { 1227 nvbo->busy_placements[i].fpfn = 0; 1228 nvbo->busy_placements[i].lpfn = mappable; 1229 } 1230 1231 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_VRAM, 0); 1232 } 1233 1234 ret = nouveau_bo_validate(nvbo, false, false); 1235 if (unlikely(ret == -EBUSY || ret == -ERESTARTSYS)) 1236 return VM_FAULT_NOPAGE; 1237 else if (unlikely(ret)) 1238 return VM_FAULT_SIGBUS; 1239 1240 ttm_bo_move_to_lru_tail_unlocked(bo); 1241 return 0; 1242 } 1243 1244 static int 1245 nouveau_ttm_tt_populate(struct ttm_device *bdev, 1246 struct ttm_tt *ttm, struct ttm_operation_ctx *ctx) 1247 { 1248 struct ttm_tt *ttm_dma = (void *)ttm; 1249 struct nouveau_drm *drm; 1250 struct device *dev; 1251 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 1252 1253 if (ttm_tt_is_populated(ttm)) 1254 return 0; 1255 1256 if (slave && ttm->sg) { 1257 drm_prime_sg_to_dma_addr_array(ttm->sg, ttm_dma->dma_address, 1258 ttm->num_pages); 1259 return 0; 1260 } 1261 1262 drm = nouveau_bdev(bdev); 1263 dev = drm->dev->dev; 1264 1265 return ttm_pool_alloc(&drm->ttm.bdev.pool, ttm, ctx); 1266 } 1267 1268 static void 1269 nouveau_ttm_tt_unpopulate(struct ttm_device *bdev, 1270 struct ttm_tt *ttm) 1271 { 1272 struct nouveau_drm *drm; 1273 struct device *dev; 1274 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 1275 1276 if (slave) 1277 return; 1278 1279 drm = nouveau_bdev(bdev); 1280 dev = drm->dev->dev; 1281 1282 return ttm_pool_free(&drm->ttm.bdev.pool, ttm); 1283 } 1284 1285 static void 1286 nouveau_ttm_tt_destroy(struct ttm_device *bdev, 1287 struct ttm_tt *ttm) 1288 { 1289 #if IS_ENABLED(CONFIG_AGP) 1290 struct nouveau_drm *drm = nouveau_bdev(bdev); 1291 if (drm->agp.bridge) { 1292 ttm_agp_unbind(ttm); 1293 ttm_tt_destroy_common(bdev, ttm); 1294 ttm_agp_destroy(ttm); 1295 return; 1296 } 1297 #endif 1298 nouveau_sgdma_destroy(bdev, ttm); 1299 } 1300 1301 void 1302 nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence, bool exclusive) 1303 { 1304 struct dma_resv *resv = nvbo->bo.base.resv; 1305 1306 if (exclusive) 1307 dma_resv_add_excl_fence(resv, &fence->base); 1308 else if (fence) 1309 dma_resv_add_shared_fence(resv, &fence->base); 1310 } 1311 1312 static void 1313 nouveau_bo_delete_mem_notify(struct ttm_buffer_object *bo) 1314 { 1315 nouveau_bo_move_ntfy(bo, NULL); 1316 } 1317 1318 struct ttm_device_funcs nouveau_bo_driver = { 1319 .ttm_tt_create = &nouveau_ttm_tt_create, 1320 .ttm_tt_populate = &nouveau_ttm_tt_populate, 1321 .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate, 1322 .ttm_tt_destroy = &nouveau_ttm_tt_destroy, 1323 .eviction_valuable = ttm_bo_eviction_valuable, 1324 .evict_flags = nouveau_bo_evict_flags, 1325 .delete_mem_notify = nouveau_bo_delete_mem_notify, 1326 .move = nouveau_bo_move, 1327 .verify_access = nouveau_bo_verify_access, 1328 .io_mem_reserve = &nouveau_ttm_io_mem_reserve, 1329 .io_mem_free = &nouveau_ttm_io_mem_free, 1330 }; 1331