1 /* 2 * Copyright 2007-2008 Nouveau Project 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef __NOUVEAU_BIOS_H__ 25 #define __NOUVEAU_BIOS_H__ 26 27 #include "nvreg.h" 28 #include "nouveau_i2c.h" 29 30 #define DCB_MAX_NUM_ENTRIES 16 31 #define DCB_MAX_NUM_I2C_ENTRIES 16 32 #define DCB_MAX_NUM_GPIO_ENTRIES 32 33 #define DCB_MAX_NUM_CONNECTOR_ENTRIES 16 34 35 #define DCB_LOC_ON_CHIP 0 36 37 #define ROM16(x) le16_to_cpu(*(u16 *)&(x)) 38 #define ROM32(x) le32_to_cpu(*(u32 *)&(x)) 39 #define ROM48(x) ({ u8 *p = &(x); (u64)ROM16(p[4]) << 32 | ROM32(p[0]); }) 40 #define ROM64(x) le64_to_cpu(*(u64 *)&(x)) 41 #define ROMPTR(d,x) ({ \ 42 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 43 ROM16(x) ? &dev_priv->vbios.data[ROM16(x)] : NULL; \ 44 }) 45 46 struct bit_entry { 47 uint8_t id; 48 uint8_t version; 49 uint16_t length; 50 uint16_t offset; 51 uint8_t *data; 52 }; 53 54 int bit_table(struct drm_device *, u8 id, struct bit_entry *); 55 56 enum dcb_gpio_tag { 57 DCB_GPIO_TVDAC0 = 0xc, 58 DCB_GPIO_TVDAC1 = 0x2d, 59 DCB_GPIO_PWM_FAN = 0x9, 60 DCB_GPIO_FAN_SENSE = 0x3d, 61 DCB_GPIO_UNUSED = 0xff 62 }; 63 64 enum dcb_connector_type { 65 DCB_CONNECTOR_VGA = 0x00, 66 DCB_CONNECTOR_TV_0 = 0x10, 67 DCB_CONNECTOR_TV_1 = 0x11, 68 DCB_CONNECTOR_TV_3 = 0x13, 69 DCB_CONNECTOR_DVI_I = 0x30, 70 DCB_CONNECTOR_DVI_D = 0x31, 71 DCB_CONNECTOR_LVDS = 0x40, 72 DCB_CONNECTOR_LVDS_SPWG = 0x41, 73 DCB_CONNECTOR_DP = 0x46, 74 DCB_CONNECTOR_eDP = 0x47, 75 DCB_CONNECTOR_HDMI_0 = 0x60, 76 DCB_CONNECTOR_HDMI_1 = 0x61, 77 DCB_CONNECTOR_NONE = 0xff 78 }; 79 80 enum dcb_type { 81 OUTPUT_ANALOG = 0, 82 OUTPUT_TV = 1, 83 OUTPUT_TMDS = 2, 84 OUTPUT_LVDS = 3, 85 OUTPUT_DP = 6, 86 OUTPUT_EOL = 14, /* DCB 4.0+, appears to be end-of-list */ 87 OUTPUT_UNUSED = 15, 88 OUTPUT_ANY = -1 89 }; 90 91 struct dcb_entry { 92 int index; /* may not be raw dcb index if merging has happened */ 93 enum dcb_type type; 94 uint8_t i2c_index; 95 uint8_t heads; 96 uint8_t connector; 97 uint8_t bus; 98 uint8_t location; 99 uint8_t or; 100 bool duallink_possible; 101 union { 102 struct sor_conf { 103 int link; 104 } sorconf; 105 struct { 106 int maxfreq; 107 } crtconf; 108 struct { 109 struct sor_conf sor; 110 bool use_straps_for_mode; 111 bool use_acpi_for_edid; 112 bool use_power_scripts; 113 } lvdsconf; 114 struct { 115 bool has_component_output; 116 } tvconf; 117 struct { 118 struct sor_conf sor; 119 int link_nr; 120 int link_bw; 121 } dpconf; 122 struct { 123 struct sor_conf sor; 124 int slave_addr; 125 } tmdsconf; 126 }; 127 bool i2c_upper_default; 128 }; 129 130 struct dcb_table { 131 uint8_t version; 132 int entries; 133 struct dcb_entry entry[DCB_MAX_NUM_ENTRIES]; 134 }; 135 136 enum nouveau_or { 137 OUTPUT_A = (1 << 0), 138 OUTPUT_B = (1 << 1), 139 OUTPUT_C = (1 << 2) 140 }; 141 142 enum LVDS_script { 143 /* Order *does* matter here */ 144 LVDS_INIT = 1, 145 LVDS_RESET, 146 LVDS_BACKLIGHT_ON, 147 LVDS_BACKLIGHT_OFF, 148 LVDS_PANEL_ON, 149 LVDS_PANEL_OFF 150 }; 151 152 /* these match types in pll limits table version 0x40, 153 * nouveau uses them on all chipsets internally where a 154 * specific pll needs to be referenced, but the exact 155 * register isn't known. 156 */ 157 enum pll_types { 158 PLL_CORE = 0x01, 159 PLL_SHADER = 0x02, 160 PLL_UNK03 = 0x03, 161 PLL_MEMORY = 0x04, 162 PLL_VDEC = 0x05, 163 PLL_UNK40 = 0x40, 164 PLL_UNK41 = 0x41, 165 PLL_UNK42 = 0x42, 166 PLL_VPLL0 = 0x80, 167 PLL_VPLL1 = 0x81, 168 PLL_MAX = 0xff 169 }; 170 171 struct pll_lims { 172 u32 reg; 173 174 struct { 175 int minfreq; 176 int maxfreq; 177 int min_inputfreq; 178 int max_inputfreq; 179 180 uint8_t min_m; 181 uint8_t max_m; 182 uint8_t min_n; 183 uint8_t max_n; 184 } vco1, vco2; 185 186 uint8_t max_log2p; 187 /* 188 * for most pre nv50 cards setting a log2P of 7 (the common max_log2p 189 * value) is no different to 6 (at least for vplls) so allowing the MNP 190 * calc to use 7 causes the generated clock to be out by a factor of 2. 191 * however, max_log2p cannot be fixed-up during parsing as the 192 * unmodified max_log2p value is still needed for setting mplls, hence 193 * an additional max_usable_log2p member 194 */ 195 uint8_t max_usable_log2p; 196 uint8_t log2p_bias; 197 198 uint8_t min_p; 199 uint8_t max_p; 200 201 int refclk; 202 }; 203 204 struct nvbios { 205 struct drm_device *dev; 206 enum { 207 NVBIOS_BMP, 208 NVBIOS_BIT 209 } type; 210 uint16_t offset; 211 212 uint8_t chip_version; 213 214 uint32_t dactestval; 215 uint32_t tvdactestval; 216 uint8_t digital_min_front_porch; 217 bool fp_no_ddc; 218 219 spinlock_t lock; 220 221 uint8_t data[NV_PROM_SIZE]; 222 unsigned int length; 223 bool execute; 224 225 uint8_t major_version; 226 uint8_t feature_byte; 227 bool is_mobile; 228 229 uint32_t fmaxvco, fminvco; 230 231 bool old_style_init; 232 uint16_t init_script_tbls_ptr; 233 uint16_t extra_init_script_tbl_ptr; 234 uint16_t macro_index_tbl_ptr; 235 uint16_t macro_tbl_ptr; 236 uint16_t condition_tbl_ptr; 237 uint16_t io_condition_tbl_ptr; 238 uint16_t io_flag_condition_tbl_ptr; 239 uint16_t init_function_tbl_ptr; 240 241 uint16_t pll_limit_tbl_ptr; 242 uint16_t ram_restrict_tbl_ptr; 243 uint8_t ram_restrict_group_count; 244 245 uint16_t some_script_ptr; /* BIT I + 14 */ 246 uint16_t init96_tbl_ptr; /* BIT I + 16 */ 247 248 struct dcb_table dcb; 249 250 struct { 251 int crtchead; 252 } state; 253 254 struct { 255 struct dcb_entry *output; 256 int crtc; 257 uint16_t script_table_ptr; 258 } display; 259 260 struct { 261 uint16_t fptablepointer; /* also used by tmds */ 262 uint16_t fpxlatetableptr; 263 int xlatwidth; 264 uint16_t lvdsmanufacturerpointer; 265 uint16_t fpxlatemanufacturertableptr; 266 uint16_t mode_ptr; 267 uint16_t xlated_entry; 268 bool power_off_for_reset; 269 bool reset_after_pclk_change; 270 bool dual_link; 271 bool link_c_increment; 272 bool if_is_24bit; 273 int duallink_transition_clk; 274 uint8_t strapless_is_24bit; 275 uint8_t *edid; 276 277 /* will need resetting after suspend */ 278 int last_script_invoc; 279 bool lvds_init_run; 280 } fp; 281 282 struct { 283 uint16_t output0_script_ptr; 284 uint16_t output1_script_ptr; 285 } tmds; 286 287 struct { 288 uint16_t mem_init_tbl_ptr; 289 uint16_t sdr_seq_tbl_ptr; 290 uint16_t ddr_seq_tbl_ptr; 291 292 struct { 293 uint8_t crt, tv, panel; 294 } i2c_indices; 295 296 uint16_t lvds_single_a_script_ptr; 297 } legacy; 298 }; 299 300 void *dcb_table(struct drm_device *); 301 void *dcb_outp(struct drm_device *, u8 idx); 302 int dcb_outp_foreach(struct drm_device *, void *data, 303 int (*)(struct drm_device *, void *, int idx, u8 *outp)); 304 u8 *dcb_conntab(struct drm_device *); 305 u8 *dcb_conn(struct drm_device *, u8 idx); 306 307 #endif 308