xref: /linux/drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h (revision 2ba9268dd603d23e17643437b2246acb6844953b)
1 #ifndef __NVKM_CLK_H__
2 #define __NVKM_CLK_H__
3 #include <core/subdev.h>
4 #include <core/notify.h>
5 struct nvbios_pll;
6 struct nvkm_pll_vals;
7 
8 enum nv_clk_src {
9 	nv_clk_src_crystal,
10 	nv_clk_src_href,
11 
12 	nv_clk_src_hclk,
13 	nv_clk_src_hclkm3,
14 	nv_clk_src_hclkm3d2,
15 	nv_clk_src_hclkm2d3, /* NVAA */
16 	nv_clk_src_hclkm4, /* NVAA */
17 	nv_clk_src_cclk, /* NVAA */
18 
19 	nv_clk_src_host,
20 
21 	nv_clk_src_sppll0,
22 	nv_clk_src_sppll1,
23 
24 	nv_clk_src_mpllsrcref,
25 	nv_clk_src_mpllsrc,
26 	nv_clk_src_mpll,
27 	nv_clk_src_mdiv,
28 
29 	nv_clk_src_core,
30 	nv_clk_src_core_intm,
31 	nv_clk_src_shader,
32 
33 	nv_clk_src_mem,
34 
35 	nv_clk_src_gpc,
36 	nv_clk_src_rop,
37 	nv_clk_src_hubk01,
38 	nv_clk_src_hubk06,
39 	nv_clk_src_hubk07,
40 	nv_clk_src_copy,
41 	nv_clk_src_daemon,
42 	nv_clk_src_disp,
43 	nv_clk_src_vdec,
44 
45 	nv_clk_src_dom6,
46 
47 	nv_clk_src_max,
48 };
49 
50 struct nvkm_cstate {
51 	struct list_head head;
52 	u8  voltage;
53 	u32 domain[nv_clk_src_max];
54 };
55 
56 struct nvkm_pstate {
57 	struct list_head head;
58 	struct list_head list; /* c-states */
59 	struct nvkm_cstate base;
60 	u8 pstate;
61 	u8 fanspeed;
62 };
63 
64 struct nvkm_domain {
65 	enum nv_clk_src name;
66 	u8 bios; /* 0xff for none */
67 #define NVKM_CLK_DOM_FLAG_CORE 0x01
68 	u8 flags;
69 	const char *mname;
70 	int mdiv;
71 };
72 
73 struct nvkm_clk {
74 	struct nvkm_subdev base;
75 
76 	struct nvkm_domain *domains;
77 	struct nvkm_pstate bstate;
78 
79 	struct list_head states;
80 	int state_nr;
81 
82 	struct work_struct work;
83 	wait_queue_head_t wait;
84 	atomic_t waiting;
85 
86 	struct nvkm_notify pwrsrc_ntfy;
87 	int pwrsrc;
88 	int pstate; /* current */
89 	int ustate_ac; /* user-requested (-1 disabled, -2 perfmon) */
90 	int ustate_dc; /* user-requested (-1 disabled, -2 perfmon) */
91 	int astate; /* perfmon adjustment (base) */
92 	int tstate; /* thermal adjustment (max-) */
93 	int dstate; /* display adjustment (min+) */
94 
95 	bool allow_reclock;
96 
97 	int  (*read)(struct nvkm_clk *, enum nv_clk_src);
98 	int  (*calc)(struct nvkm_clk *, struct nvkm_cstate *);
99 	int  (*prog)(struct nvkm_clk *);
100 	void (*tidy)(struct nvkm_clk *);
101 
102 	/*XXX: die, these are here *only* to support the completely
103 	 *     bat-shit insane what-was-nvkm_hw.c code
104 	 */
105 	int (*pll_calc)(struct nvkm_clk *, struct nvbios_pll *, int clk,
106 			struct nvkm_pll_vals *pv);
107 	int (*pll_prog)(struct nvkm_clk *, u32 reg1, struct nvkm_pll_vals *pv);
108 };
109 
110 static inline struct nvkm_clk *
111 nvkm_clk(void *obj)
112 {
113 	return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_CLK);
114 }
115 
116 #define nvkm_clk_create(p,e,o,i,r,s,n,d)                                  \
117 	nvkm_clk_create_((p), (e), (o), (i), (r), (s), (n), sizeof(**d),  \
118 			      (void **)d)
119 #define nvkm_clk_destroy(p) ({                                            \
120 	struct nvkm_clk *clk = (p);                                       \
121 	_nvkm_clk_dtor(nv_object(clk));                                   \
122 })
123 #define nvkm_clk_init(p) ({                                               \
124 	struct nvkm_clk *clk = (p);                                       \
125 	_nvkm_clk_init(nv_object(clk));                                   \
126 })
127 #define nvkm_clk_fini(p,s) ({                                             \
128 	struct nvkm_clk *clk = (p);                                       \
129 	_nvkm_clk_fini(nv_object(clk), (s));                              \
130 })
131 
132 int  nvkm_clk_create_(struct nvkm_object *, struct nvkm_object *,
133 			   struct nvkm_oclass *,
134 			   struct nvkm_domain *, struct nvkm_pstate *,
135 			   int, bool, int, void **);
136 void _nvkm_clk_dtor(struct nvkm_object *);
137 int  _nvkm_clk_init(struct nvkm_object *);
138 int  _nvkm_clk_fini(struct nvkm_object *, bool);
139 
140 extern struct nvkm_oclass nv04_clk_oclass;
141 extern struct nvkm_oclass nv40_clk_oclass;
142 extern struct nvkm_oclass *nv50_clk_oclass;
143 extern struct nvkm_oclass *g84_clk_oclass;
144 extern struct nvkm_oclass *mcp77_clk_oclass;
145 extern struct nvkm_oclass gt215_clk_oclass;
146 extern struct nvkm_oclass gf100_clk_oclass;
147 extern struct nvkm_oclass gk104_clk_oclass;
148 extern struct nvkm_oclass gk20a_clk_oclass;
149 
150 int nv04_clk_pll_set(struct nvkm_clk *, u32 type, u32 freq);
151 int nv04_clk_pll_calc(struct nvkm_clk *, struct nvbios_pll *, int clk,
152 		      struct nvkm_pll_vals *);
153 int nv04_clk_pll_prog(struct nvkm_clk *, u32 reg1, struct nvkm_pll_vals *);
154 int gt215_clk_pll_calc(struct nvkm_clk *, struct nvbios_pll *,
155 		       int clk, struct nvkm_pll_vals *);
156 
157 int nvkm_clk_ustate(struct nvkm_clk *, int req, int pwr);
158 int nvkm_clk_astate(struct nvkm_clk *, int req, int rel, bool wait);
159 int nvkm_clk_dstate(struct nvkm_clk *, int req, int rel);
160 int nvkm_clk_tstate(struct nvkm_clk *, int req, int rel);
161 #endif
162