1*b7019ac5SIlia Mirkin /* SPDX-License-Identifier: MIT */ 2c39f472eSBen Skeggs #ifndef __NVBIOS_PMU_H__ 3c39f472eSBen Skeggs #define __NVBIOS_PMU_H__ 4c39f472eSBen Skeggs struct nvbios_pmuT { 5c39f472eSBen Skeggs }; 6c39f472eSBen Skeggs 7d390b480SBen Skeggs u32 nvbios_pmuTe(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len); 8c39f472eSBen Skeggs 9c39f472eSBen Skeggs struct nvbios_pmuE { 10c39f472eSBen Skeggs u8 type; 11c39f472eSBen Skeggs u32 data; 12c39f472eSBen Skeggs }; 13c39f472eSBen Skeggs 14d390b480SBen Skeggs u32 nvbios_pmuEe(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr); 15d390b480SBen Skeggs u32 nvbios_pmuEp(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr, 16c39f472eSBen Skeggs struct nvbios_pmuE *); 17c39f472eSBen Skeggs 18c39f472eSBen Skeggs struct nvbios_pmuR { 19c39f472eSBen Skeggs u32 boot_addr_pmu; 20c39f472eSBen Skeggs u32 boot_addr; 21c39f472eSBen Skeggs u32 boot_size; 22c39f472eSBen Skeggs u32 code_addr_pmu; 23c39f472eSBen Skeggs u32 code_addr; 24c39f472eSBen Skeggs u32 code_size; 25c39f472eSBen Skeggs u32 init_addr_pmu; 26c39f472eSBen Skeggs 27c39f472eSBen Skeggs u32 data_addr_pmu; 28c39f472eSBen Skeggs u32 data_addr; 29c39f472eSBen Skeggs u32 data_size; 30c39f472eSBen Skeggs u32 args_addr_pmu; 31c39f472eSBen Skeggs }; 32c39f472eSBen Skeggs 33d390b480SBen Skeggs bool nvbios_pmuRm(struct nvkm_bios *, u8 type, struct nvbios_pmuR *); 34c39f472eSBen Skeggs #endif 35