1*b7019ac5SIlia Mirkin /* SPDX-License-Identifier: MIT */ 2c39f472eSBen Skeggs #ifndef __NVBIOS_PLL_H__ 3c39f472eSBen Skeggs #define __NVBIOS_PLL_H__ 4c39f472eSBen Skeggs /*XXX: kill me */ 5d390b480SBen Skeggs struct nvkm_pll_vals { 6c39f472eSBen Skeggs union { 7c39f472eSBen Skeggs struct { 8c39f472eSBen Skeggs #ifdef __BIG_ENDIAN 9c39f472eSBen Skeggs uint8_t N1, M1, N2, M2; 10c39f472eSBen Skeggs #else 11c39f472eSBen Skeggs uint8_t M1, N1, M2, N2; 12c39f472eSBen Skeggs #endif 13c39f472eSBen Skeggs }; 14c39f472eSBen Skeggs struct { 15c39f472eSBen Skeggs uint16_t NM1, NM2; 16c39f472eSBen Skeggs } __attribute__((packed)); 17c39f472eSBen Skeggs }; 18c39f472eSBen Skeggs int log2P; 19c39f472eSBen Skeggs 20c39f472eSBen Skeggs int refclk; 21c39f472eSBen Skeggs }; 22c39f472eSBen Skeggs 23c39f472eSBen Skeggs /* these match types in pll limits table version 0x40, 24d390b480SBen Skeggs * nvkm uses them on all chipsets internally where a 25c39f472eSBen Skeggs * specific pll needs to be referenced, but the exact 26c39f472eSBen Skeggs * register isn't known. 27c39f472eSBen Skeggs */ 28c39f472eSBen Skeggs enum nvbios_pll_type { 29c39f472eSBen Skeggs PLL_CORE = 0x01, 30c39f472eSBen Skeggs PLL_SHADER = 0x02, 31c39f472eSBen Skeggs PLL_UNK03 = 0x03, 32c39f472eSBen Skeggs PLL_MEMORY = 0x04, 33c39f472eSBen Skeggs PLL_VDEC = 0x05, 34c39f472eSBen Skeggs PLL_UNK40 = 0x40, 35c39f472eSBen Skeggs PLL_UNK41 = 0x41, 36c39f472eSBen Skeggs PLL_UNK42 = 0x42, 37c39f472eSBen Skeggs PLL_VPLL0 = 0x80, 38c39f472eSBen Skeggs PLL_VPLL1 = 0x81, 39c39f472eSBen Skeggs PLL_VPLL2 = 0x82, 40c39f472eSBen Skeggs PLL_VPLL3 = 0x83, 41c39f472eSBen Skeggs PLL_MAX = 0xff 42c39f472eSBen Skeggs }; 43c39f472eSBen Skeggs 44c39f472eSBen Skeggs struct nvbios_pll { 45c39f472eSBen Skeggs enum nvbios_pll_type type; 46c39f472eSBen Skeggs u32 reg; 47c39f472eSBen Skeggs u32 refclk; 48c39f472eSBen Skeggs 49c39f472eSBen Skeggs u8 min_p; 50c39f472eSBen Skeggs u8 max_p; 51c39f472eSBen Skeggs u8 bias_p; 52c39f472eSBen Skeggs 53c39f472eSBen Skeggs /* 54c39f472eSBen Skeggs * for most pre nv50 cards setting a log2P of 7 (the common max_log2p 55c39f472eSBen Skeggs * value) is no different to 6 (at least for vplls) so allowing the MNP 56c39f472eSBen Skeggs * calc to use 7 causes the generated clock to be out by a factor of 2. 57c39f472eSBen Skeggs * however, max_log2p cannot be fixed-up during parsing as the 58c39f472eSBen Skeggs * unmodified max_log2p value is still needed for setting mplls, hence 59c39f472eSBen Skeggs * an additional max_usable_log2p member 60c39f472eSBen Skeggs */ 61c39f472eSBen Skeggs u8 max_p_usable; 62c39f472eSBen Skeggs 63c39f472eSBen Skeggs struct { 64c39f472eSBen Skeggs u32 min_freq; 65c39f472eSBen Skeggs u32 max_freq; 66c39f472eSBen Skeggs u32 min_inputfreq; 67c39f472eSBen Skeggs u32 max_inputfreq; 68c39f472eSBen Skeggs u8 min_m; 69c39f472eSBen Skeggs u8 max_m; 70c39f472eSBen Skeggs u8 min_n; 71c39f472eSBen Skeggs u8 max_n; 72c39f472eSBen Skeggs } vco1, vco2; 73c39f472eSBen Skeggs }; 74c39f472eSBen Skeggs 75d390b480SBen Skeggs int nvbios_pll_parse(struct nvkm_bios *, u32 type, struct nvbios_pll *); 76c39f472eSBen Skeggs #endif 77