1 /* SPDX-License-Identifier: MIT */ 2 #ifndef __NVIF_IF0012_H__ 3 #define __NVIF_IF0012_H__ 4 5 #include <drm/display/drm_dp.h> 6 7 union nvif_outp_args { 8 struct nvif_outp_v0 { 9 __u8 version; 10 __u8 id; /* DCB device index. */ 11 __u8 pad02[6]; 12 } v0; 13 }; 14 15 #define NVIF_OUTP_V0_DETECT 0x00 16 #define NVIF_OUTP_V0_EDID_GET 0x01 17 18 #define NVIF_OUTP_V0_INHERIT 0x10 19 #define NVIF_OUTP_V0_ACQUIRE 0x11 20 #define NVIF_OUTP_V0_RELEASE 0x12 21 22 #define NVIF_OUTP_V0_LOAD_DETECT 0x20 23 24 #define NVIF_OUTP_V0_BL_GET 0x30 25 #define NVIF_OUTP_V0_BL_SET 0x31 26 27 #define NVIF_OUTP_V0_LVDS 0x40 28 29 #define NVIF_OUTP_V0_HDMI 0x50 30 31 #define NVIF_OUTP_V0_INFOFRAME 0x60 32 #define NVIF_OUTP_V0_HDA_ELD 0x61 33 34 #define NVIF_OUTP_V0_DP_AUX_PWR 0x70 35 #define NVIF_OUTP_V0_DP_AUX_XFER 0x71 36 #define NVIF_OUTP_V0_DP_RATES 0x72 37 #define NVIF_OUTP_V0_DP_TRAIN 0x73 38 #define NVIF_OUTP_V0_DP_DRIVE 0x74 39 #define NVIF_OUTP_V0_DP_SST 0x75 40 #define NVIF_OUTP_V0_DP_MST_ID_GET 0x76 41 #define NVIF_OUTP_V0_DP_MST_ID_PUT 0x77 42 #define NVIF_OUTP_V0_DP_MST_VCPI 0x78 43 44 union nvif_outp_detect_args { 45 struct nvif_outp_detect_v0 { 46 __u8 version; 47 #define NVIF_OUTP_DETECT_V0_NOT_PRESENT 0x00 48 #define NVIF_OUTP_DETECT_V0_PRESENT 0x01 49 #define NVIF_OUTP_DETECT_V0_UNKNOWN 0x02 50 __u8 status; 51 } v0; 52 }; 53 54 union nvif_outp_edid_get_args { 55 struct nvif_outp_edid_get_v0 { 56 __u8 version; 57 __u8 pad01; 58 __u16 size; 59 __u8 data[2048]; 60 } v0; 61 }; 62 63 union nvif_outp_load_detect_args { 64 struct nvif_outp_load_detect_v0 { 65 __u8 version; 66 __u8 load; 67 __u8 pad02[2]; 68 __u32 data; /*TODO: move vbios loadval parsing into nvkm */ 69 } v0; 70 }; 71 72 union nvif_outp_acquire_args { 73 struct nvif_outp_acquire_v0 { 74 __u8 version; 75 #define NVIF_OUTP_ACQUIRE_V0_DAC 0x00 76 #define NVIF_OUTP_ACQUIRE_V0_SOR 0x01 77 #define NVIF_OUTP_ACQUIRE_V0_PIOR 0x02 78 __u8 type; 79 __u8 or; 80 __u8 link; 81 __u8 pad04[4]; 82 union { 83 struct { 84 __u8 hda; 85 } sor; 86 }; 87 } v0; 88 }; 89 90 union nvif_outp_inherit_args { 91 struct nvif_outp_inherit_v0 { 92 __u8 version; 93 #define NVIF_OUTP_INHERIT_V0_RGB_CRT 0x00 94 #define NVIF_OUTP_INHERIT_V0_TV 0x01 95 #define NVIF_OUTP_INHERIT_V0_TMDS 0x02 96 #define NVIF_OUTP_INHERIT_V0_LVDS 0x03 97 #define NVIF_OUTP_INHERIT_V0_DP 0x04 98 // In/out. Input is one of the above values, output is the actual hw protocol 99 __u8 proto; 100 __u8 or; 101 __u8 link; 102 __u8 head; 103 union { 104 struct { 105 // TODO: Figure out padding, and whether we even want this field 106 __u8 hda; 107 } tmds; 108 }; 109 } v0; 110 }; 111 112 union nvif_outp_release_args { 113 struct nvif_outp_release_vn { 114 } vn; 115 }; 116 117 union nvif_outp_bl_get_args { 118 struct nvif_outp_bl_get_v0 { 119 __u8 version; 120 __u8 level; 121 } v0; 122 }; 123 124 union nvif_outp_bl_set_args { 125 struct nvif_outp_bl_set_v0 { 126 __u8 version; 127 __u8 level; 128 } v0; 129 }; 130 131 union nvif_outp_lvds_args { 132 struct nvif_outp_lvds_v0 { 133 __u8 version; 134 __u8 dual; 135 __u8 bpc8; 136 } v0; 137 }; 138 139 union nvif_outp_hdmi_args { 140 struct nvif_outp_hdmi_v0 { 141 __u8 version; 142 __u8 head; 143 __u8 enable; 144 __u8 max_ac_packet; 145 __u8 rekey; 146 __u8 scdc; 147 __u8 scdc_scrambling; 148 __u8 scdc_low_rates; 149 __u32 khz; 150 } v0; 151 }; 152 153 union nvif_outp_infoframe_args { 154 struct nvif_outp_infoframe_v0 { 155 __u8 version; 156 #define NVIF_OUTP_INFOFRAME_V0_AVI 0 157 #define NVIF_OUTP_INFOFRAME_V0_VSI 1 158 __u8 type; 159 __u8 head; 160 __u8 pad03[5]; 161 __u8 data[]; 162 } v0; 163 }; 164 165 union nvif_outp_hda_eld_args { 166 struct nvif_outp_hda_eld_v0 { 167 __u8 version; 168 __u8 head; 169 __u8 pad02[6]; 170 __u8 data[]; 171 } v0; 172 }; 173 174 union nvif_outp_dp_aux_pwr_args { 175 struct nvif_outp_dp_aux_pwr_v0 { 176 __u8 version; 177 __u8 state; 178 __u8 pad02[6]; 179 } v0; 180 }; 181 182 union nvif_outp_dp_aux_xfer_args { 183 struct nvif_outp_dp_aux_xfer_v0 { 184 __u8 version; 185 __u8 pad01; 186 __u8 type; 187 __u8 size; 188 __u32 addr; 189 __u8 data[16]; 190 } v0; 191 }; 192 193 union nvif_outp_dp_rates_args { 194 struct nvif_outp_dp_rates_v0 { 195 __u8 version; 196 __u8 pad01[6]; 197 __u8 rates; 198 struct { 199 __s8 dpcd; 200 __u32 rate; 201 } rate[8]; 202 } v0; 203 }; 204 205 union nvif_outp_dp_train_args { 206 struct nvif_outp_dp_train_v0 { 207 __u8 version; 208 __u8 retrain; 209 __u8 mst; 210 __u8 lttprs; 211 __u8 post_lt_adj; 212 __u8 link_nr; 213 __u32 link_bw; 214 __u8 dpcd[DP_RECEIVER_CAP_SIZE]; 215 } v0; 216 }; 217 218 union nvif_outp_dp_drive_args { 219 struct nvif_outp_dp_drive_v0 { 220 __u8 version; 221 __u8 pad01[2]; 222 __u8 lanes; 223 __u8 pe[4]; 224 __u8 vs[4]; 225 } v0; 226 }; 227 228 union nvif_outp_dp_sst_args { 229 struct nvif_outp_dp_sst_v0 { 230 __u8 version; 231 __u8 head; 232 __u8 pad02[2]; 233 __u32 watermark; 234 __u32 hblanksym; 235 __u32 vblanksym; 236 } v0; 237 }; 238 239 union nvif_outp_dp_mst_id_put_args { 240 struct nvif_outp_dp_mst_id_put_v0 { 241 __u8 version; 242 __u8 pad01[3]; 243 __u32 id; 244 } v0; 245 }; 246 247 union nvif_outp_dp_mst_id_get_args { 248 struct nvif_outp_dp_mst_id_get_v0 { 249 __u8 version; 250 __u8 pad01[3]; 251 __u32 id; 252 } v0; 253 }; 254 255 union nvif_outp_dp_mst_vcpi_args { 256 struct nvif_outp_dp_mst_vcpi_v0 { 257 __u8 version; 258 __u8 head; 259 __u8 start_slot; 260 __u8 num_slots; 261 __u16 pbn; 262 __u16 aligned_pbn; 263 } v0; 264 }; 265 #endif 266