1 #ifndef __NVIF_CLASS_H__ 2 #define __NVIF_CLASS_H__ 3 4 /* these class numbers are made up by us, and not nvidia-assigned */ 5 #define NVIF_CLASS_CLIENT /* if0000.h */ -0x00000000 6 7 #define NVIF_CLASS_CONTROL /* if0001.h */ -0x00000001 8 9 #define NVIF_CLASS_PERFMON /* if0002.h */ -0x00000002 10 #define NVIF_CLASS_PERFDOM /* if0003.h */ -0x00000003 11 12 #define NVIF_CLASS_SW_NV04 /* if0004.h */ -0x00000004 13 #define NVIF_CLASS_SW_NV10 /* if0005.h */ -0x00000005 14 #define NVIF_CLASS_SW_NV50 /* if0005.h */ -0x00000006 15 #define NVIF_CLASS_SW_GF100 /* if0005.h */ -0x00000007 16 17 /* the below match nvidia-assigned (either in hw, or sw) class numbers */ 18 #define NV_NULL_CLASS 0x00000030 19 20 #define NV_DEVICE /* cl0080.h */ 0x00000080 21 22 #define NV_DMA_FROM_MEMORY /* cl0002.h */ 0x00000002 23 #define NV_DMA_TO_MEMORY /* cl0002.h */ 0x00000003 24 #define NV_DMA_IN_MEMORY /* cl0002.h */ 0x0000003d 25 26 #define NV50_TWOD 0x0000502d 27 #define FERMI_TWOD_A 0x0000902d 28 29 #define NV50_MEMORY_TO_MEMORY_FORMAT 0x00005039 30 #define FERMI_MEMORY_TO_MEMORY_FORMAT_A 0x00009039 31 32 #define KEPLER_INLINE_TO_MEMORY_A 0x0000a040 33 #define KEPLER_INLINE_TO_MEMORY_B 0x0000a140 34 35 #define NV04_DISP /* cl0046.h */ 0x00000046 36 37 #define NV03_CHANNEL_DMA /* cl506b.h */ 0x0000006b 38 #define NV10_CHANNEL_DMA /* cl506b.h */ 0x0000006e 39 #define NV17_CHANNEL_DMA /* cl506b.h */ 0x0000176e 40 #define NV40_CHANNEL_DMA /* cl506b.h */ 0x0000406e 41 #define NV50_CHANNEL_DMA /* cl506e.h */ 0x0000506e 42 #define G82_CHANNEL_DMA /* cl826e.h */ 0x0000826e 43 44 #define NV50_CHANNEL_GPFIFO /* cl506f.h */ 0x0000506f 45 #define G82_CHANNEL_GPFIFO /* cl826f.h */ 0x0000826f 46 #define FERMI_CHANNEL_GPFIFO /* cl906f.h */ 0x0000906f 47 #define KEPLER_CHANNEL_GPFIFO_A /* cla06f.h */ 0x0000a06f 48 #define KEPLER_CHANNEL_GPFIFO_B /* cla06f.h */ 0x0000a16f 49 #define MAXWELL_CHANNEL_GPFIFO_A /* cla06f.h */ 0x0000b06f 50 #define PASCAL_CHANNEL_GPFIFO_A /* cla06f.h */ 0x0000c06f 51 52 #define NV50_DISP /* cl5070.h */ 0x00005070 53 #define G82_DISP /* cl5070.h */ 0x00008270 54 #define GT200_DISP /* cl5070.h */ 0x00008370 55 #define GT214_DISP /* cl5070.h */ 0x00008570 56 #define GT206_DISP /* cl5070.h */ 0x00008870 57 #define GF110_DISP /* cl5070.h */ 0x00009070 58 #define GK104_DISP /* cl5070.h */ 0x00009170 59 #define GK110_DISP /* cl5070.h */ 0x00009270 60 #define GM107_DISP /* cl5070.h */ 0x00009470 61 #define GM200_DISP /* cl5070.h */ 0x00009570 62 #define GP100_DISP /* cl5070.h */ 0x00009770 63 #define GP102_DISP /* cl5070.h */ 0x00009870 64 65 #define NV31_MPEG 0x00003174 66 #define G82_MPEG 0x00008274 67 68 #define NV74_VP2 0x00007476 69 70 #define NV50_DISP_CURSOR /* cl507a.h */ 0x0000507a 71 #define G82_DISP_CURSOR /* cl507a.h */ 0x0000827a 72 #define GT214_DISP_CURSOR /* cl507a.h */ 0x0000857a 73 #define GF110_DISP_CURSOR /* cl507a.h */ 0x0000907a 74 #define GK104_DISP_CURSOR /* cl507a.h */ 0x0000917a 75 76 #define NV50_DISP_OVERLAY /* cl507b.h */ 0x0000507b 77 #define G82_DISP_OVERLAY /* cl507b.h */ 0x0000827b 78 #define GT214_DISP_OVERLAY /* cl507b.h */ 0x0000857b 79 #define GF110_DISP_OVERLAY /* cl507b.h */ 0x0000907b 80 #define GK104_DISP_OVERLAY /* cl507b.h */ 0x0000917b 81 82 #define NV50_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000507c 83 #define G82_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000827c 84 #define GT200_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000837c 85 #define GT214_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000857c 86 #define GF110_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000907c 87 #define GK104_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000917c 88 #define GK110_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000927c 89 90 #define NV50_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000507d 91 #define G82_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000827d 92 #define GT200_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000837d 93 #define GT214_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000857d 94 #define GT206_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000887d 95 #define GF110_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000907d 96 #define GK104_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000917d 97 #define GK110_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000927d 98 #define GM107_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000947d 99 #define GM200_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000957d 100 #define GP100_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000977d 101 #define GP102_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000987d 102 103 #define NV50_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000507e 104 #define G82_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000827e 105 #define GT200_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000837e 106 #define GT214_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000857e 107 #define GF110_DISP_OVERLAY_CONTROL_DMA /* cl507e.h */ 0x0000907e 108 #define GK104_DISP_OVERLAY_CONTROL_DMA /* cl507e.h */ 0x0000917e 109 110 #define NV50_TESLA 0x00005097 111 #define G82_TESLA 0x00008297 112 #define GT200_TESLA 0x00008397 113 #define GT214_TESLA 0x00008597 114 #define GT21A_TESLA 0x00008697 115 116 #define FERMI_A /* cl9097.h */ 0x00009097 117 #define FERMI_B /* cl9097.h */ 0x00009197 118 #define FERMI_C /* cl9097.h */ 0x00009297 119 120 #define KEPLER_A /* cl9097.h */ 0x0000a097 121 #define KEPLER_B /* cl9097.h */ 0x0000a197 122 #define KEPLER_C /* cl9097.h */ 0x0000a297 123 124 #define MAXWELL_A /* cl9097.h */ 0x0000b097 125 #define MAXWELL_B /* cl9097.h */ 0x0000b197 126 127 #define PASCAL_A /* cl9097.h */ 0x0000c097 128 #define PASCAL_B /* cl9097.h */ 0x0000c197 129 130 #define NV74_BSP 0x000074b0 131 132 #define GT212_MSVLD 0x000085b1 133 #define IGT21A_MSVLD 0x000086b1 134 #define G98_MSVLD 0x000088b1 135 #define GF100_MSVLD 0x000090b1 136 #define GK104_MSVLD 0x000095b1 137 138 #define GT212_MSPDEC 0x000085b2 139 #define G98_MSPDEC 0x000088b2 140 #define GF100_MSPDEC 0x000090b2 141 #define GK104_MSPDEC 0x000095b2 142 143 #define GT212_MSPPP 0x000085b3 144 #define G98_MSPPP 0x000088b3 145 #define GF100_MSPPP 0x000090b3 146 147 #define G98_SEC 0x000088b4 148 149 #define GT212_DMA 0x000085b5 150 #define FERMI_DMA 0x000090b5 151 #define KEPLER_DMA_COPY_A 0x0000a0b5 152 #define MAXWELL_DMA_COPY_A 0x0000b0b5 153 #define PASCAL_DMA_COPY_A 0x0000c0b5 154 #define PASCAL_DMA_COPY_B 0x0000c1b5 155 156 #define FERMI_DECOMPRESS 0x000090b8 157 158 #define NV50_COMPUTE 0x000050c0 159 #define GT214_COMPUTE 0x000085c0 160 #define FERMI_COMPUTE_A 0x000090c0 161 #define FERMI_COMPUTE_B 0x000091c0 162 #define KEPLER_COMPUTE_A 0x0000a0c0 163 #define KEPLER_COMPUTE_B 0x0000a1c0 164 #define MAXWELL_COMPUTE_A 0x0000b0c0 165 #define MAXWELL_COMPUTE_B 0x0000b1c0 166 #define PASCAL_COMPUTE_A 0x0000c0c0 167 #define PASCAL_COMPUTE_B 0x0000c1c0 168 169 #define NV74_CIPHER 0x000074c1 170 #endif 171