1 /* SPDX-License-Identifier: MIT */ 2 #ifndef __NVIF_CLASS_H__ 3 #define __NVIF_CLASS_H__ 4 5 /* these class numbers are made up by us, and not nvidia-assigned */ 6 #define NVIF_CLASS_CLIENT /* if0000.h */ -0x00000000 7 8 #define NVIF_CLASS_CONTROL /* if0001.h */ -0x00000001 9 10 #define NVIF_CLASS_SW_NV04 /* if0004.h */ -0x00000004 11 #define NVIF_CLASS_SW_NV10 /* if0005.h */ -0x00000005 12 #define NVIF_CLASS_SW_NV50 /* if0005.h */ -0x00000006 13 #define NVIF_CLASS_SW_GF100 /* if0005.h */ -0x00000007 14 15 #define NVIF_CLASS_MMU /* if0008.h */ 0x80000008 16 #define NVIF_CLASS_MMU_NV04 /* if0008.h */ 0x80000009 17 #define NVIF_CLASS_MMU_NV50 /* if0008.h */ 0x80005009 18 #define NVIF_CLASS_MMU_GF100 /* if0008.h */ 0x80009009 19 20 #define NVIF_CLASS_MEM /* if000a.h */ 0x8000000a 21 #define NVIF_CLASS_MEM_NV04 /* if000b.h */ 0x8000000b 22 #define NVIF_CLASS_MEM_NV50 /* if500b.h */ 0x8000500b 23 #define NVIF_CLASS_MEM_GF100 /* if900b.h */ 0x8000900b 24 25 #define NVIF_CLASS_VMM /* if000c.h */ 0x8000000c 26 #define NVIF_CLASS_VMM_NV04 /* if000d.h */ 0x8000000d 27 #define NVIF_CLASS_VMM_NV50 /* if500d.h */ 0x8000500d 28 #define NVIF_CLASS_VMM_GF100 /* if900d.h */ 0x8000900d 29 #define NVIF_CLASS_VMM_GM200 /* ifb00d.h */ 0x8000b00d 30 #define NVIF_CLASS_VMM_GP100 /* ifc00d.h */ 0x8000c00d 31 32 #define NVIF_CLASS_EVENT /* if000e.h */ 0x8000000e 33 34 #define NVIF_CLASS_DISP /* if0010.h */ 0x80000010 35 #define NVIF_CLASS_CONN /* if0011.h */ 0x80000011 36 #define NVIF_CLASS_OUTP /* if0012.h */ 0x80000012 37 #define NVIF_CLASS_HEAD /* if0013.h */ 0x80000013 38 #define NVIF_CLASS_DISP_CHAN /* if0014.h */ 0x80000014 39 40 #define NVIF_CLASS_CHAN /* if0020.h */ 0x80000020 41 #define NVIF_CLASS_CGRP /* if0021.h */ 0x80000021 42 43 /* the below match nvidia-assigned (either in hw, or sw) class numbers */ 44 #define NV_NULL_CLASS 0x00000030 45 46 #define NV_DEVICE /* cl0080.h */ 0x00000080 47 48 #define NV_DMA_FROM_MEMORY /* cl0002.h */ 0x00000002 49 #define NV_DMA_TO_MEMORY /* cl0002.h */ 0x00000003 50 #define NV_DMA_IN_MEMORY /* cl0002.h */ 0x0000003d 51 52 #define NV50_TWOD 0x0000502d 53 #define FERMI_TWOD_A 0x0000902d 54 55 #define NV50_MEMORY_TO_MEMORY_FORMAT 0x00005039 56 #define FERMI_MEMORY_TO_MEMORY_FORMAT_A 0x00009039 57 58 #define KEPLER_INLINE_TO_MEMORY_A 0x0000a040 59 #define KEPLER_INLINE_TO_MEMORY_B 0x0000a140 60 #define BLACKWELL_INLINE_TO_MEMORY_A 0x0000cd40 61 62 #define NV04_DISP /* cl0046.h */ 0x00000046 63 64 #define VOLTA_USERMODE_A 0x0000c361 65 #define TURING_USERMODE_A 0x0000c461 66 #define AMPERE_USERMODE_A 0x0000c561 67 #define HOPPER_USERMODE_A 0x0000c661 68 #define BLACKWELL_USERMODE_A 0x0000c761 69 70 #define MAXWELL_FAULT_BUFFER_A /* clb069.h */ 0x0000b069 71 #define VOLTA_FAULT_BUFFER_A /* clb069.h */ 0x0000c369 72 73 #define NV03_CHANNEL_DMA /* if0020.h */ 0x0000006b 74 #define NV10_CHANNEL_DMA /* if0020.h */ 0x0000006e 75 #define NV17_CHANNEL_DMA /* if0020.h */ 0x0000176e 76 #define NV40_CHANNEL_DMA /* if0020.h */ 0x0000406e 77 78 #define KEPLER_CHANNEL_GROUP_A /* if0021.h */ 0x0000a06c 79 80 #define NV50_CHANNEL_GPFIFO /* if0020.h */ 0x0000506f 81 #define G82_CHANNEL_GPFIFO /* if0020.h */ 0x0000826f 82 #define FERMI_CHANNEL_GPFIFO /* if0020.h */ 0x0000906f 83 #define KEPLER_CHANNEL_GPFIFO_A /* if0020.h */ 0x0000a06f 84 #define KEPLER_CHANNEL_GPFIFO_B /* if0020.h */ 0x0000a16f 85 #define MAXWELL_CHANNEL_GPFIFO_A /* if0020.h */ 0x0000b06f 86 #define PASCAL_CHANNEL_GPFIFO_A /* if0020.h */ 0x0000c06f 87 #define VOLTA_CHANNEL_GPFIFO_A /* if0020.h */ 0x0000c36f 88 #define TURING_CHANNEL_GPFIFO_A /* if0020.h */ 0x0000c46f 89 #define AMPERE_CHANNEL_GPFIFO_A /* if0020.h */ 0x0000c56f 90 #define AMPERE_CHANNEL_GPFIFO_B /* if0020.h */ 0x0000c76f 91 #define HOPPER_CHANNEL_GPFIFO_A 0x0000c86f 92 #define BLACKWELL_CHANNEL_GPFIFO_A 0x0000c96f 93 #define BLACKWELL_CHANNEL_GPFIFO_B 0x0000ca6f 94 95 #define NV50_DISP /* if0010.h */ 0x00005070 96 #define G82_DISP /* if0010.h */ 0x00008270 97 #define GT200_DISP /* if0010.h */ 0x00008370 98 #define GT214_DISP /* if0010.h */ 0x00008570 99 #define GT206_DISP /* if0010.h */ 0x00008870 100 #define GF110_DISP /* if0010.h */ 0x00009070 101 #define GK104_DISP /* if0010.h */ 0x00009170 102 #define GK110_DISP /* if0010.h */ 0x00009270 103 #define GM107_DISP /* if0010.h */ 0x00009470 104 #define GM200_DISP /* if0010.h */ 0x00009570 105 #define GP100_DISP /* if0010.h */ 0x00009770 106 #define GP102_DISP /* if0010.h */ 0x00009870 107 #define GV100_DISP /* if0010.h */ 0x0000c370 108 #define TU102_DISP /* if0010.h */ 0x0000c570 109 #define GA102_DISP /* if0010.h */ 0x0000c670 110 #define AD102_DISP /* if0010.h */ 0x0000c770 111 #define GB202_DISP 0x0000ca70 112 113 #define GV100_DISP_CAPS 0x0000c373 114 #define GB202_DISP_CAPS 0x0000ca73 115 116 #define NV31_MPEG 0x00003174 117 #define G82_MPEG 0x00008274 118 119 #define NV74_VP2 0x00007476 120 121 #define NV50_DISP_CURSOR /* if0014.h */ 0x0000507a 122 #define G82_DISP_CURSOR /* if0014.h */ 0x0000827a 123 #define GT214_DISP_CURSOR /* if0014.h */ 0x0000857a 124 #define GF110_DISP_CURSOR /* if0014.h */ 0x0000907a 125 #define GK104_DISP_CURSOR /* if0014.h */ 0x0000917a 126 #define GV100_DISP_CURSOR /* if0014.h */ 0x0000c37a 127 #define TU102_DISP_CURSOR /* if0014.h */ 0x0000c57a 128 #define GA102_DISP_CURSOR /* if0014.h */ 0x0000c67a 129 #define GB202_DISP_CURSOR 0x0000ca7a 130 131 #define NV50_DISP_OVERLAY /* if0014.h */ 0x0000507b 132 #define G82_DISP_OVERLAY /* if0014.h */ 0x0000827b 133 #define GT214_DISP_OVERLAY /* if0014.h */ 0x0000857b 134 #define GF110_DISP_OVERLAY /* if0014.h */ 0x0000907b 135 #define GK104_DISP_OVERLAY /* if0014.h */ 0x0000917b 136 137 #define GV100_DISP_WINDOW_IMM_CHANNEL_DMA /* if0014.h */ 0x0000c37b 138 #define TU102_DISP_WINDOW_IMM_CHANNEL_DMA /* if0014.h */ 0x0000c57b 139 #define GA102_DISP_WINDOW_IMM_CHANNEL_DMA /* if0014.h */ 0x0000c67b 140 #define GB202_DISP_WINDOW_IMM_CHANNEL_DMA 0x0000ca7b 141 142 #define NV50_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000507c 143 #define G82_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000827c 144 #define GT200_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000837c 145 #define GT214_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000857c 146 #define GF110_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000907c 147 #define GK104_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000917c 148 #define GK110_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000927c 149 150 #define NV50_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000507d 151 #define G82_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000827d 152 #define GT200_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000837d 153 #define GT214_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000857d 154 #define GT206_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000887d 155 #define GF110_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000907d 156 #define GK104_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000917d 157 #define GK110_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000927d 158 #define GM107_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000947d 159 #define GM200_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000957d 160 #define GP100_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000977d 161 #define GP102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000987d 162 #define GV100_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c37d 163 #define TU102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c57d 164 #define GA102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c67d 165 #define AD102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c77d 166 #define GB202_DISP_CORE_CHANNEL_DMA 0x0000ca7d 167 168 #define NV50_DISP_OVERLAY_CHANNEL_DMA /* if0014.h */ 0x0000507e 169 #define G82_DISP_OVERLAY_CHANNEL_DMA /* if0014.h */ 0x0000827e 170 #define GT200_DISP_OVERLAY_CHANNEL_DMA /* if0014.h */ 0x0000837e 171 #define GT214_DISP_OVERLAY_CHANNEL_DMA /* if0014.h */ 0x0000857e 172 #define GF110_DISP_OVERLAY_CONTROL_DMA /* if0014.h */ 0x0000907e 173 #define GK104_DISP_OVERLAY_CONTROL_DMA /* if0014.h */ 0x0000917e 174 175 #define GV100_DISP_WINDOW_CHANNEL_DMA /* if0014.h */ 0x0000c37e 176 #define TU102_DISP_WINDOW_CHANNEL_DMA /* if0014.h */ 0x0000c57e 177 #define GA102_DISP_WINDOW_CHANNEL_DMA /* if0014.h */ 0x0000c67e 178 #define GB202_DISP_WINDOW_CHANNEL_DMA 0x0000ca7e 179 180 #define NV50_TESLA 0x00005097 181 #define G82_TESLA 0x00008297 182 #define GT200_TESLA 0x00008397 183 #define GT214_TESLA 0x00008597 184 #define GT21A_TESLA 0x00008697 185 186 #define FERMI_A /* cl9097.h */ 0x00009097 187 #define FERMI_B /* cl9097.h */ 0x00009197 188 #define FERMI_C /* cl9097.h */ 0x00009297 189 190 #define KEPLER_A /* cl9097.h */ 0x0000a097 191 #define KEPLER_B /* cl9097.h */ 0x0000a197 192 #define KEPLER_C /* cl9097.h */ 0x0000a297 193 194 #define MAXWELL_A /* cl9097.h */ 0x0000b097 195 #define MAXWELL_B /* cl9097.h */ 0x0000b197 196 197 #define PASCAL_A /* cl9097.h */ 0x0000c097 198 #define PASCAL_B /* cl9097.h */ 0x0000c197 199 200 #define VOLTA_A /* cl9097.h */ 0x0000c397 201 202 #define TURING_A /* cl9097.h */ 0x0000c597 203 204 #define AMPERE_A 0x0000c697 205 #define AMPERE_B /* cl9097.h */ 0x0000c797 206 207 #define ADA_A /* cl9097.h */ 0x0000c997 208 209 #define HOPPER_A 0x0000cb97 210 211 #define BLACKWELL_A 0x0000cd97 212 #define BLACKWELL_B 0x0000ce97 213 214 #define NV74_BSP 0x000074b0 215 216 #define NVB8B0_VIDEO_DECODER 0x0000b8b0 217 #define NVC4B0_VIDEO_DECODER 0x0000c4b0 218 #define NVC6B0_VIDEO_DECODER 0x0000c6b0 219 #define NVC7B0_VIDEO_DECODER 0x0000c7b0 220 #define NVC9B0_VIDEO_DECODER 0x0000c9b0 221 #define NVCDB0_VIDEO_DECODER 0x0000cdb0 222 #define NVCFB0_VIDEO_DECODER 0x0000cfb0 223 224 #define GT212_MSVLD 0x000085b1 225 #define IGT21A_MSVLD 0x000086b1 226 #define G98_MSVLD 0x000088b1 227 #define GF100_MSVLD 0x000090b1 228 #define GK104_MSVLD 0x000095b1 229 230 #define GT212_MSPDEC 0x000085b2 231 #define G98_MSPDEC 0x000088b2 232 #define GF100_MSPDEC 0x000090b2 233 #define GK104_MSPDEC 0x000095b2 234 235 #define GT212_MSPPP 0x000085b3 236 #define G98_MSPPP 0x000088b3 237 #define GF100_MSPPP 0x000090b3 238 239 #define G98_SEC 0x000088b4 240 241 #define GT212_DMA 0x000085b5 242 #define FERMI_DMA 0x000090b5 243 #define KEPLER_DMA_COPY_A 0x0000a0b5 244 #define MAXWELL_DMA_COPY_A 0x0000b0b5 245 #define PASCAL_DMA_COPY_A 0x0000c0b5 246 #define PASCAL_DMA_COPY_B 0x0000c1b5 247 #define VOLTA_DMA_COPY_A 0x0000c3b5 248 #define TURING_DMA_COPY_A 0x0000c5b5 249 #define AMPERE_DMA_COPY_A 0x0000c6b5 250 #define AMPERE_DMA_COPY_B 0x0000c7b5 251 #define HOPPER_DMA_COPY_A 0x0000c8b5 252 #define BLACKWELL_DMA_COPY_A 0x0000c9b5 253 #define BLACKWELL_DMA_COPY_B 0x0000cab5 254 255 #define NVC4B7_VIDEO_ENCODER 0x0000c4b7 256 #define NVC7B7_VIDEO_ENCODER 0x0000c7b7 257 #define NVC9B7_VIDEO_ENCODER 0x0000c9b7 258 #define NVCFB7_VIDEO_ENCODER 0x0000cfb7 259 260 #define FERMI_DECOMPRESS 0x000090b8 261 262 #define NV50_COMPUTE 0x000050c0 263 #define GT214_COMPUTE 0x000085c0 264 #define FERMI_COMPUTE_A 0x000090c0 265 #define FERMI_COMPUTE_B 0x000091c0 266 #define KEPLER_COMPUTE_A 0x0000a0c0 267 #define KEPLER_COMPUTE_B 0x0000a1c0 268 #define MAXWELL_COMPUTE_A 0x0000b0c0 269 #define MAXWELL_COMPUTE_B 0x0000b1c0 270 #define PASCAL_COMPUTE_A 0x0000c0c0 271 #define PASCAL_COMPUTE_B 0x0000c1c0 272 #define VOLTA_COMPUTE_A 0x0000c3c0 273 #define TURING_COMPUTE_A 0x0000c5c0 274 #define AMPERE_COMPUTE_A 0x0000c6c0 275 #define AMPERE_COMPUTE_B 0x0000c7c0 276 #define ADA_COMPUTE_A 0x0000c9c0 277 #define HOPPER_COMPUTE_A 0x0000cbc0 278 #define BLACKWELL_COMPUTE_A 0x0000cdc0 279 #define BLACKWELL_COMPUTE_B 0x0000cec0 280 281 #define NV74_CIPHER 0x000074c1 282 283 #define NVB8D1_VIDEO_NVJPG 0x0000b8d1 284 #define NVC4D1_VIDEO_NVJPG 0x0000c4d1 285 #define NVC9D1_VIDEO_NVJPG 0x0000c9d1 286 #define NVCDD1_VIDEO_NVJPG 0x0000cdd1 287 #define NVCFD1_VIDEO_NVJPG 0x0000cfd1 288 289 #define NVB8FA_VIDEO_OFA 0x0000b8fa 290 #define NVC6FA_VIDEO_OFA 0x0000c6fa 291 #define NVC7FA_VIDEO_OFA 0x0000c7fa 292 #define NVC9FA_VIDEO_OFA 0x0000c9fa 293 #define NVCDFA_VIDEO_OFA 0x0000cdfa 294 #define NVCFFA_VIDEO_OFA 0x0000cffa 295 #endif 296