1 #ifndef __NVIF_CLASS_H__ 2 #define __NVIF_CLASS_H__ 3 4 /* these class numbers are made up by us, and not nvidia-assigned */ 5 #define NVIF_CLASS_CONTROL /* if0001.h */ -1 6 #define NVIF_CLASS_PERFMON /* if0002.h */ -2 7 #define NVIF_CLASS_PERFDOM /* if0003.h */ -3 8 #define NVIF_CLASS_SW_NV04 /* if0004.h */ -4 9 #define NVIF_CLASS_SW_NV10 /* if0005.h */ -5 10 #define NVIF_CLASS_SW_NV50 /* if0005.h */ -6 11 #define NVIF_CLASS_SW_GF100 /* if0005.h */ -7 12 13 /* the below match nvidia-assigned (either in hw, or sw) class numbers */ 14 #define NV_DEVICE /* cl0080.h */ 0x00000080 15 16 #define NV_DMA_FROM_MEMORY /* cl0002.h */ 0x00000002 17 #define NV_DMA_TO_MEMORY /* cl0002.h */ 0x00000003 18 #define NV_DMA_IN_MEMORY /* cl0002.h */ 0x0000003d 19 20 #define FERMI_TWOD_A 0x0000902d 21 22 #define FERMI_MEMORY_TO_MEMORY_FORMAT_A 0x00009039 23 24 #define KEPLER_INLINE_TO_MEMORY_A 0x0000a040 25 #define KEPLER_INLINE_TO_MEMORY_B 0x0000a140 26 27 #define NV04_DISP /* cl0046.h */ 0x00000046 28 29 #define NV03_CHANNEL_DMA /* cl506b.h */ 0x0000006b 30 #define NV10_CHANNEL_DMA /* cl506b.h */ 0x0000006e 31 #define NV17_CHANNEL_DMA /* cl506b.h */ 0x0000176e 32 #define NV40_CHANNEL_DMA /* cl506b.h */ 0x0000406e 33 #define NV50_CHANNEL_DMA /* cl506e.h */ 0x0000506e 34 #define G82_CHANNEL_DMA /* cl826e.h */ 0x0000826e 35 36 #define NV50_CHANNEL_GPFIFO /* cl506f.h */ 0x0000506f 37 #define G82_CHANNEL_GPFIFO /* cl826f.h */ 0x0000826f 38 #define FERMI_CHANNEL_GPFIFO /* cl906f.h */ 0x0000906f 39 #define KEPLER_CHANNEL_GPFIFO_A /* cla06f.h */ 0x0000a06f 40 #define KEPLER_CHANNEL_GPFIFO_B /* cla06f.h */ 0x0000a16f 41 #define MAXWELL_CHANNEL_GPFIFO_A /* cla06f.h */ 0x0000b06f 42 43 #define NV50_DISP /* cl5070.h */ 0x00005070 44 #define G82_DISP /* cl5070.h */ 0x00008270 45 #define GT200_DISP /* cl5070.h */ 0x00008370 46 #define GT214_DISP /* cl5070.h */ 0x00008570 47 #define GT206_DISP /* cl5070.h */ 0x00008870 48 #define GF110_DISP /* cl5070.h */ 0x00009070 49 #define GK104_DISP /* cl5070.h */ 0x00009170 50 #define GK110_DISP /* cl5070.h */ 0x00009270 51 #define GM107_DISP /* cl5070.h */ 0x00009470 52 #define GM200_DISP /* cl5070.h */ 0x00009570 53 54 #define NV31_MPEG 0x00003174 55 #define G82_MPEG 0x00008274 56 57 #define NV74_VP2 0x00007476 58 59 #define NV50_DISP_CURSOR /* cl507a.h */ 0x0000507a 60 #define G82_DISP_CURSOR /* cl507a.h */ 0x0000827a 61 #define GT214_DISP_CURSOR /* cl507a.h */ 0x0000857a 62 #define GF110_DISP_CURSOR /* cl507a.h */ 0x0000907a 63 #define GK104_DISP_CURSOR /* cl507a.h */ 0x0000917a 64 65 #define NV50_DISP_OVERLAY /* cl507b.h */ 0x0000507b 66 #define G82_DISP_OVERLAY /* cl507b.h */ 0x0000827b 67 #define GT214_DISP_OVERLAY /* cl507b.h */ 0x0000857b 68 #define GF110_DISP_OVERLAY /* cl507b.h */ 0x0000907b 69 #define GK104_DISP_OVERLAY /* cl507b.h */ 0x0000917b 70 71 #define NV50_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000507c 72 #define G82_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000827c 73 #define GT200_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000837c 74 #define GT214_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000857c 75 #define GF110_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000907c 76 #define GK104_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000917c 77 #define GK110_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000927c 78 79 #define NV50_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000507d 80 #define G82_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000827d 81 #define GT200_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000837d 82 #define GT214_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000857d 83 #define GT206_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000887d 84 #define GF110_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000907d 85 #define GK104_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000917d 86 #define GK110_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000927d 87 #define GM107_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000947d 88 #define GM200_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000957d 89 90 #define NV50_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000507e 91 #define G82_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000827e 92 #define GT200_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000837e 93 #define GT214_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000857e 94 #define GF110_DISP_OVERLAY_CONTROL_DMA /* cl507e.h */ 0x0000907e 95 #define GK104_DISP_OVERLAY_CONTROL_DMA /* cl507e.h */ 0x0000917e 96 97 #define FERMI_A /* cl9097.h */ 0x00009097 98 #define FERMI_B /* cl9097.h */ 0x00009197 99 #define FERMI_C /* cl9097.h */ 0x00009297 100 101 #define KEPLER_A /* cl9097.h */ 0x0000a097 102 #define KEPLER_B /* cl9097.h */ 0x0000a197 103 #define KEPLER_C /* cl9097.h */ 0x0000a297 104 105 #define MAXWELL_A /* cl9097.h */ 0x0000b097 106 #define MAXWELL_B /* cl9097.h */ 0x0000b197 107 108 #define NV74_BSP 0x000074b0 109 110 #define GT212_MSVLD 0x000085b1 111 #define IGT21A_MSVLD 0x000086b1 112 #define G98_MSVLD 0x000088b1 113 #define GF100_MSVLD 0x000090b1 114 #define GK104_MSVLD 0x000095b1 115 116 #define GT212_MSPDEC 0x000085b2 117 #define G98_MSPDEC 0x000088b2 118 #define GF100_MSPDEC 0x000090b2 119 #define GK104_MSPDEC 0x000095b2 120 121 #define GT212_MSPPP 0x000085b3 122 #define G98_MSPPP 0x000088b3 123 #define GF100_MSPPP 0x000090b3 124 125 #define G98_SEC 0x000088b4 126 127 #define GT212_DMA 0x000085b5 128 #define FERMI_DMA 0x000090b5 129 #define KEPLER_DMA_COPY_A 0x0000a0b5 130 #define MAXWELL_DMA_COPY_A 0x0000b0b5 131 132 #define FERMI_DECOMPRESS 0x000090b8 133 134 #define FERMI_COMPUTE_A 0x000090c0 135 #define FERMI_COMPUTE_B 0x000091c0 136 #define KEPLER_COMPUTE_A 0x0000a0c0 137 #define KEPLER_COMPUTE_B 0x0000a1c0 138 #define MAXWELL_COMPUTE_A 0x0000b0c0 139 #define MAXWELL_COMPUTE_B 0x0000b1c0 140 141 #define NV74_CIPHER 0x000074c1 142 #endif 143