1 /* SPDX-License-Identifier: MIT */ 2 #ifndef __NVIF_CL0080_H__ 3 #define __NVIF_CL0080_H__ 4 5 #define NV_DEVICE_V0_INFO 0x00 6 #define NV_DEVICE_V0_TIME 0x01 7 8 struct nv_device_info_v0 { 9 __u8 version; 10 #define NV_DEVICE_INFO_V0_IGP 0x00 11 #define NV_DEVICE_INFO_V0_PCI 0x01 12 #define NV_DEVICE_INFO_V0_AGP 0x02 13 #define NV_DEVICE_INFO_V0_PCIE 0x03 14 #define NV_DEVICE_INFO_V0_SOC 0x04 15 __u8 platform; 16 __u16 chipset; /* from NV_PMC_BOOT_0 */ 17 __u8 revision; /* from NV_PMC_BOOT_0 */ 18 #define NV_DEVICE_INFO_V0_TNT 0x01 19 #define NV_DEVICE_INFO_V0_CELSIUS 0x02 20 #define NV_DEVICE_INFO_V0_KELVIN 0x03 21 #define NV_DEVICE_INFO_V0_RANKINE 0x04 22 #define NV_DEVICE_INFO_V0_CURIE 0x05 23 #define NV_DEVICE_INFO_V0_TESLA 0x06 24 #define NV_DEVICE_INFO_V0_FERMI 0x07 25 #define NV_DEVICE_INFO_V0_KEPLER 0x08 26 #define NV_DEVICE_INFO_V0_MAXWELL 0x09 27 #define NV_DEVICE_INFO_V0_PASCAL 0x0a 28 #define NV_DEVICE_INFO_V0_VOLTA 0x0b 29 #define NV_DEVICE_INFO_V0_TURING 0x0c 30 #define NV_DEVICE_INFO_V0_AMPERE 0x0d 31 #define NV_DEVICE_INFO_V0_ADA 0x0e 32 __u8 family; 33 __u8 pad06[2]; 34 __u64 ram_size; 35 __u64 ram_user; 36 char chip[16]; 37 char name[64]; 38 }; 39 40 struct nv_device_info_v1 { 41 __u8 version; 42 __u8 count; 43 __u8 pad02[6]; 44 struct nv_device_info_v1_data { 45 __u64 mthd; /* NV_DEVICE_INFO_* (see below). */ 46 __u64 data; 47 } data[]; 48 }; 49 50 struct nv_device_time_v0 { 51 __u8 version; 52 __u8 pad01[7]; 53 __u64 time; 54 }; 55 56 #define NV_DEVICE_INFO_UNIT (0xffffffffULL << 32) 57 #define NV_DEVICE_INFO(n) ((n) | (0x00000000ULL << 32)) 58 #define NV_DEVICE_HOST(n) ((n) | (0x00000001ULL << 32)) 59 60 /* This will be returned in the mthd field for unsupported queries. */ 61 #define NV_DEVICE_INFO_INVALID ~0ULL 62 63 /* Returns the number of available runlists. */ 64 #define NV_DEVICE_HOST_RUNLISTS NV_DEVICE_HOST(0x00000000) 65 /* Returns the number of available channels (0 if per-runlist). */ 66 #define NV_DEVICE_HOST_CHANNELS NV_DEVICE_HOST(0x00000001) 67 68 /* Returns a mask of available engine types on runlist(data). */ 69 #define NV_DEVICE_HOST_RUNLIST_ENGINES NV_DEVICE_HOST(0x00000100) 70 #define NV_DEVICE_HOST_RUNLIST_ENGINES_SW 0x00000001 71 #define NV_DEVICE_HOST_RUNLIST_ENGINES_GR 0x00000002 72 #define NV_DEVICE_HOST_RUNLIST_ENGINES_MPEG 0x00000004 73 #define NV_DEVICE_HOST_RUNLIST_ENGINES_ME 0x00000008 74 #define NV_DEVICE_HOST_RUNLIST_ENGINES_CIPHER 0x00000010 75 #define NV_DEVICE_HOST_RUNLIST_ENGINES_BSP 0x00000020 76 #define NV_DEVICE_HOST_RUNLIST_ENGINES_VP 0x00000040 77 #define NV_DEVICE_HOST_RUNLIST_ENGINES_CE 0x00000080 78 #define NV_DEVICE_HOST_RUNLIST_ENGINES_SEC 0x00000100 79 #define NV_DEVICE_HOST_RUNLIST_ENGINES_MSVLD 0x00000200 80 #define NV_DEVICE_HOST_RUNLIST_ENGINES_MSPDEC 0x00000400 81 #define NV_DEVICE_HOST_RUNLIST_ENGINES_MSPPP 0x00000800 82 #define NV_DEVICE_HOST_RUNLIST_ENGINES_MSENC 0x00001000 83 #define NV_DEVICE_HOST_RUNLIST_ENGINES_VIC 0x00002000 84 #define NV_DEVICE_HOST_RUNLIST_ENGINES_SEC2 0x00004000 85 #define NV_DEVICE_HOST_RUNLIST_ENGINES_NVDEC 0x00008000 86 #define NV_DEVICE_HOST_RUNLIST_ENGINES_NVENC 0x00010000 87 #define NV_DEVICE_HOST_RUNLIST_ENGINES_NVJPG 0x00020000 88 #define NV_DEVICE_HOST_RUNLIST_ENGINES_OFA 0x00040000 89 /* Returns the number of available channels on runlist(data). */ 90 #define NV_DEVICE_HOST_RUNLIST_CHANNELS NV_DEVICE_HOST(0x00000101) 91 #endif 92