1*b1ca3847SBen Skeggs /* SPDX-License-Identifier: MIT 2*b1ca3847SBen Skeggs * 3*b1ca3847SBen Skeggs * Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. 4*b1ca3847SBen Skeggs */ 5*b1ca3847SBen Skeggs #include "nouveau_drv.h" 6*b1ca3847SBen Skeggs #include "nouveau_dma.h" 7*b1ca3847SBen Skeggs #include "nouveau_fence.h" 8*b1ca3847SBen Skeggs 9*b1ca3847SBen Skeggs #include "nv50_display.h" 10*b1ca3847SBen Skeggs 11*b1ca3847SBen Skeggs #include <nvif/push906f.h> 12*b1ca3847SBen Skeggs 13*b1ca3847SBen Skeggs #include <nvhw/class/clc36f.h> 14*b1ca3847SBen Skeggs 15*b1ca3847SBen Skeggs static int 16*b1ca3847SBen Skeggs gv100_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence) 17*b1ca3847SBen Skeggs { 18*b1ca3847SBen Skeggs struct nvif_push *push = &chan->chan.push; 19*b1ca3847SBen Skeggs int ret; 20*b1ca3847SBen Skeggs 21*b1ca3847SBen Skeggs ret = PUSH_WAIT(push, 8); 22*b1ca3847SBen Skeggs if (ret) 23*b1ca3847SBen Skeggs return ret; 24*b1ca3847SBen Skeggs 25*b1ca3847SBen Skeggs PUSH_MTHD(push, NVC36F, SEM_ADDR_LO, lower_32_bits(virtual), 26*b1ca3847SBen Skeggs SEM_ADDR_HI, upper_32_bits(virtual), 27*b1ca3847SBen Skeggs SEM_PAYLOAD_LO, sequence); 28*b1ca3847SBen Skeggs 29*b1ca3847SBen Skeggs PUSH_MTHD(push, NVC36F, SEM_EXECUTE, 30*b1ca3847SBen Skeggs NVDEF(NVC36F, SEM_EXECUTE, OPERATION, RELEASE) | 31*b1ca3847SBen Skeggs NVDEF(NVC36F, SEM_EXECUTE, RELEASE_WFI, EN) | 32*b1ca3847SBen Skeggs NVDEF(NVC36F, SEM_EXECUTE, PAYLOAD_SIZE, 32BIT) | 33*b1ca3847SBen Skeggs NVDEF(NVC36F, SEM_EXECUTE, RELEASE_TIMESTAMP, DIS)); 34*b1ca3847SBen Skeggs 35*b1ca3847SBen Skeggs PUSH_MTHD(push, NVC36F, NON_STALL_INTERRUPT, 0); 36*b1ca3847SBen Skeggs 37*b1ca3847SBen Skeggs PUSH_KICK(push); 38*b1ca3847SBen Skeggs return 0; 39*b1ca3847SBen Skeggs } 40*b1ca3847SBen Skeggs 41*b1ca3847SBen Skeggs static int 42*b1ca3847SBen Skeggs gv100_fence_sync32(struct nouveau_channel *chan, u64 virtual, u32 sequence) 43*b1ca3847SBen Skeggs { 44*b1ca3847SBen Skeggs struct nvif_push *push = &chan->chan.push; 45*b1ca3847SBen Skeggs int ret; 46*b1ca3847SBen Skeggs 47*b1ca3847SBen Skeggs ret = PUSH_WAIT(push, 6); 48*b1ca3847SBen Skeggs if (ret) 49*b1ca3847SBen Skeggs return ret; 50*b1ca3847SBen Skeggs 51*b1ca3847SBen Skeggs PUSH_MTHD(push, NVC36F, SEM_ADDR_LO, lower_32_bits(virtual), 52*b1ca3847SBen Skeggs SEM_ADDR_HI, upper_32_bits(virtual), 53*b1ca3847SBen Skeggs SEM_PAYLOAD_LO, sequence); 54*b1ca3847SBen Skeggs 55*b1ca3847SBen Skeggs PUSH_MTHD(push, NVC36F, SEM_EXECUTE, 56*b1ca3847SBen Skeggs NVDEF(NVC36F, SEM_EXECUTE, OPERATION, ACQ_CIRC_GEQ) | 57*b1ca3847SBen Skeggs NVDEF(NVC36F, SEM_EXECUTE, ACQUIRE_SWITCH_TSG, EN) | 58*b1ca3847SBen Skeggs NVDEF(NVC36F, SEM_EXECUTE, PAYLOAD_SIZE, 32BIT)); 59*b1ca3847SBen Skeggs 60*b1ca3847SBen Skeggs PUSH_KICK(push); 61*b1ca3847SBen Skeggs return 0; 62*b1ca3847SBen Skeggs } 63*b1ca3847SBen Skeggs 64*b1ca3847SBen Skeggs static int 65*b1ca3847SBen Skeggs gv100_fence_context_new(struct nouveau_channel *chan) 66*b1ca3847SBen Skeggs { 67*b1ca3847SBen Skeggs struct nv84_fence_chan *fctx; 68*b1ca3847SBen Skeggs int ret; 69*b1ca3847SBen Skeggs 70*b1ca3847SBen Skeggs ret = nv84_fence_context_new(chan); 71*b1ca3847SBen Skeggs if (ret) 72*b1ca3847SBen Skeggs return ret; 73*b1ca3847SBen Skeggs 74*b1ca3847SBen Skeggs fctx = chan->fence; 75*b1ca3847SBen Skeggs fctx->base.emit32 = gv100_fence_emit32; 76*b1ca3847SBen Skeggs fctx->base.sync32 = gv100_fence_sync32; 77*b1ca3847SBen Skeggs return 0; 78*b1ca3847SBen Skeggs } 79*b1ca3847SBen Skeggs 80*b1ca3847SBen Skeggs int 81*b1ca3847SBen Skeggs gv100_fence_create(struct nouveau_drm *drm) 82*b1ca3847SBen Skeggs { 83*b1ca3847SBen Skeggs struct nv84_fence_priv *priv; 84*b1ca3847SBen Skeggs int ret; 85*b1ca3847SBen Skeggs 86*b1ca3847SBen Skeggs ret = nv84_fence_create(drm); 87*b1ca3847SBen Skeggs if (ret) 88*b1ca3847SBen Skeggs return ret; 89*b1ca3847SBen Skeggs 90*b1ca3847SBen Skeggs priv = drm->fence; 91*b1ca3847SBen Skeggs priv->base.context_new = gv100_fence_context_new; 92*b1ca3847SBen Skeggs return 0; 93*b1ca3847SBen Skeggs } 94