1 /* 2 * Copyright 2018 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #include "wndw.h" 23 #include "wimm.h" 24 #include "handles.h" 25 26 #include <nvif/class.h> 27 #include <nvif/cl0002.h> 28 29 #include <nvhw/class/cl507c.h> 30 #include <nvhw/class/cl507e.h> 31 #include <nvhw/class/clc37e.h> 32 33 #include <linux/iosys-map.h> 34 35 #include <drm/drm_atomic.h> 36 #include <drm/drm_atomic_helper.h> 37 #include <drm/drm_blend.h> 38 #include <drm/drm_fourcc.h> 39 #include <drm/drm_framebuffer.h> 40 #include <drm/drm_gem_atomic_helper.h> 41 #include <drm/drm_panic.h> 42 #include <drm/ttm/ttm_bo.h> 43 44 #include "nouveau_bo.h" 45 #include "nouveau_gem.h" 46 #include "tile.h" 47 48 static void 49 nv50_wndw_ctxdma_del(struct nv50_wndw_ctxdma *ctxdma) 50 { 51 nvif_object_dtor(&ctxdma->object); 52 list_del(&ctxdma->head); 53 kfree(ctxdma); 54 } 55 56 static struct nv50_wndw_ctxdma * 57 nv50_wndw_ctxdma_new(struct nv50_wndw *wndw, struct drm_framebuffer *fb) 58 { 59 struct nouveau_drm *drm = nouveau_drm(fb->dev); 60 struct nv50_wndw_ctxdma *ctxdma; 61 u32 handle; 62 u32 unused; 63 u8 kind; 64 struct { 65 struct nv_dma_v0 base; 66 union { 67 struct nv50_dma_v0 nv50; 68 struct gf100_dma_v0 gf100; 69 struct gf119_dma_v0 gf119; 70 }; 71 } args = {}; 72 u32 argc = sizeof(args.base); 73 int ret; 74 75 nouveau_framebuffer_get_layout(fb, &unused, &kind); 76 handle = NV50_DISP_HANDLE_WNDW_CTX(kind); 77 78 list_for_each_entry(ctxdma, &wndw->ctxdma.list, head) { 79 if (ctxdma->object.handle == handle) 80 return ctxdma; 81 } 82 83 if (!(ctxdma = kzalloc(sizeof(*ctxdma), GFP_KERNEL))) 84 return ERR_PTR(-ENOMEM); 85 list_add(&ctxdma->head, &wndw->ctxdma.list); 86 87 args.base.target = NV_DMA_V0_TARGET_VRAM; 88 args.base.access = NV_DMA_V0_ACCESS_RDWR; 89 args.base.start = 0; 90 args.base.limit = drm->client.device.info.ram_user - 1; 91 92 if (drm->client.device.info.chipset < 0x80) { 93 args.nv50.part = NV50_DMA_V0_PART_256; 94 argc += sizeof(args.nv50); 95 } else 96 if (drm->client.device.info.chipset < 0xc0) { 97 args.nv50.part = NV50_DMA_V0_PART_256; 98 args.nv50.kind = kind; 99 argc += sizeof(args.nv50); 100 } else 101 if (drm->client.device.info.chipset < 0xd0) { 102 args.gf100.kind = kind; 103 argc += sizeof(args.gf100); 104 } else { 105 args.gf119.page = GF119_DMA_V0_PAGE_LP; 106 args.gf119.kind = kind; 107 argc += sizeof(args.gf119); 108 } 109 110 ret = nvif_object_ctor(wndw->ctxdma.parent, "kmsFbCtxDma", handle, 111 NV_DMA_IN_MEMORY, &args, argc, &ctxdma->object); 112 if (ret) { 113 nv50_wndw_ctxdma_del(ctxdma); 114 return ERR_PTR(ret); 115 } 116 117 return ctxdma; 118 } 119 120 int 121 nv50_wndw_wait_armed(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) 122 { 123 struct nv50_disp *disp = nv50_disp(wndw->plane.dev); 124 if (asyw->set.ntfy) { 125 return wndw->func->ntfy_wait_begun(disp->sync, 126 asyw->ntfy.offset, 127 wndw->wndw.base.device); 128 } 129 return 0; 130 } 131 132 void 133 nv50_wndw_flush_clr(struct nv50_wndw *wndw, u32 *interlock, bool flush, 134 struct nv50_wndw_atom *asyw) 135 { 136 union nv50_wndw_atom_mask clr = { 137 .mask = asyw->clr.mask & ~(flush ? 0 : asyw->set.mask), 138 }; 139 if (clr.sema ) wndw->func-> sema_clr(wndw); 140 if (clr.ntfy ) wndw->func-> ntfy_clr(wndw); 141 if (clr.xlut ) wndw->func-> xlut_clr(wndw); 142 if (clr.csc ) wndw->func-> csc_clr(wndw); 143 if (clr.image) wndw->func->image_clr(wndw); 144 145 interlock[wndw->interlock.type] |= wndw->interlock.data; 146 } 147 148 void 149 nv50_wndw_flush_set(struct nv50_wndw *wndw, u32 *interlock, 150 struct nv50_wndw_atom *asyw) 151 { 152 if (interlock[NV50_DISP_INTERLOCK_CORE]) { 153 asyw->image.mode = NV507C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING; 154 asyw->image.interval = 1; 155 } 156 157 if (asyw->set.sema ) wndw->func->sema_set (wndw, asyw); 158 if (asyw->set.ntfy ) wndw->func->ntfy_set (wndw, asyw); 159 if (asyw->set.image) wndw->func->image_set(wndw, asyw); 160 161 if (asyw->set.xlut ) { 162 if (asyw->ilut) { 163 asyw->xlut.i.offset = 164 nv50_lut_load(&wndw->ilut, asyw->xlut.i.buffer, 165 asyw->ilut, asyw->xlut.i.load); 166 } 167 wndw->func->xlut_set(wndw, asyw); 168 } 169 170 if (asyw->set.csc ) wndw->func->csc_set (wndw, asyw); 171 if (asyw->set.scale) wndw->func->scale_set(wndw, asyw); 172 if (asyw->set.blend) wndw->func->blend_set(wndw, asyw); 173 if (asyw->set.point) { 174 if (asyw->set.point = false, asyw->set.mask) 175 interlock[wndw->interlock.type] |= wndw->interlock.data; 176 interlock[NV50_DISP_INTERLOCK_WIMM] |= wndw->interlock.wimm; 177 178 wndw->immd->point(wndw, asyw); 179 wndw->immd->update(wndw, interlock); 180 } else { 181 interlock[wndw->interlock.type] |= wndw->interlock.data; 182 } 183 } 184 185 void 186 nv50_wndw_ntfy_enable(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) 187 { 188 struct nv50_disp *disp = nv50_disp(wndw->plane.dev); 189 190 asyw->ntfy.handle = wndw->wndw.sync.handle; 191 asyw->ntfy.offset = wndw->ntfy; 192 asyw->ntfy.awaken = false; 193 asyw->set.ntfy = true; 194 195 wndw->func->ntfy_reset(disp->sync, wndw->ntfy); 196 wndw->ntfy ^= 0x10; 197 } 198 199 static void 200 nv50_wndw_atomic_check_release(struct nv50_wndw *wndw, 201 struct nv50_wndw_atom *asyw, 202 struct nv50_head_atom *asyh) 203 { 204 struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev); 205 NV_ATOMIC(drm, "%s release\n", wndw->plane.name); 206 wndw->func->release(wndw, asyw, asyh); 207 asyw->ntfy.handle = 0; 208 asyw->sema.handle = 0; 209 asyw->xlut.handle = 0; 210 memset(asyw->image.handle, 0x00, sizeof(asyw->image.handle)); 211 } 212 213 static int 214 nv50_wndw_atomic_check_acquire_yuv(struct nv50_wndw_atom *asyw) 215 { 216 switch (asyw->state.fb->format->format) { 217 case DRM_FORMAT_YUYV: 218 asyw->image.format = NV507E_SURFACE_SET_PARAMS_FORMAT_VE8YO8UE8YE8; 219 break; 220 case DRM_FORMAT_UYVY: 221 asyw->image.format = NV507E_SURFACE_SET_PARAMS_FORMAT_YO8VE8YE8UE8; 222 break; 223 default: 224 WARN_ON(1); 225 return -EINVAL; 226 } 227 228 asyw->image.colorspace = NV507E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_601; 229 return 0; 230 } 231 232 static int 233 nv50_wndw_atomic_check_acquire_rgb(struct nv50_wndw_atom *asyw) 234 { 235 switch (asyw->state.fb->format->format) { 236 case DRM_FORMAT_C8: 237 asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_I8; 238 break; 239 case DRM_FORMAT_XRGB8888: 240 case DRM_FORMAT_ARGB8888: 241 asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8; 242 break; 243 case DRM_FORMAT_RGB565: 244 asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_R5G6B5; 245 break; 246 case DRM_FORMAT_XRGB1555: 247 case DRM_FORMAT_ARGB1555: 248 asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5; 249 break; 250 case DRM_FORMAT_XBGR2101010: 251 case DRM_FORMAT_ABGR2101010: 252 asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10; 253 break; 254 case DRM_FORMAT_XBGR8888: 255 case DRM_FORMAT_ABGR8888: 256 asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_A8B8G8R8; 257 break; 258 case DRM_FORMAT_XRGB2101010: 259 case DRM_FORMAT_ARGB2101010: 260 asyw->image.format = NVC37E_SET_PARAMS_FORMAT_A2R10G10B10; 261 break; 262 case DRM_FORMAT_XBGR16161616F: 263 case DRM_FORMAT_ABGR16161616F: 264 asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16; 265 break; 266 default: 267 return -EINVAL; 268 } 269 270 asyw->image.colorspace = NV507E_SURFACE_SET_PARAMS_COLOR_SPACE_RGB; 271 return 0; 272 } 273 274 static int 275 nv50_wndw_atomic_check_acquire(struct nv50_wndw *wndw, bool modeset, 276 struct nv50_wndw_atom *armw, 277 struct nv50_wndw_atom *asyw, 278 struct nv50_head_atom *asyh) 279 { 280 struct drm_framebuffer *fb = asyw->state.fb; 281 struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev); 282 uint8_t kind; 283 uint32_t tile_mode; 284 int ret; 285 286 NV_ATOMIC(drm, "%s acquire\n", wndw->plane.name); 287 288 if (fb != armw->state.fb || !armw->visible || modeset) { 289 nouveau_framebuffer_get_layout(fb, &tile_mode, &kind); 290 291 asyw->image.w = fb->width; 292 asyw->image.h = fb->height; 293 asyw->image.kind = kind; 294 295 ret = nv50_wndw_atomic_check_acquire_rgb(asyw); 296 if (ret) { 297 ret = nv50_wndw_atomic_check_acquire_yuv(asyw); 298 if (ret) 299 return ret; 300 } 301 302 if (asyw->image.kind) { 303 asyw->image.layout = NV507C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR; 304 if (drm->client.device.info.chipset >= 0xc0) 305 asyw->image.blockh = tile_mode >> 4; 306 else 307 asyw->image.blockh = tile_mode; 308 asyw->image.blocks[0] = fb->pitches[0] / 64; 309 asyw->image.pitch[0] = 0; 310 } else { 311 asyw->image.layout = NV507C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH; 312 asyw->image.blockh = NV507C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB; 313 asyw->image.blocks[0] = 0; 314 asyw->image.pitch[0] = fb->pitches[0]; 315 } 316 317 if (!asyh->state.async_flip) 318 asyw->image.interval = 1; 319 else 320 asyw->image.interval = 0; 321 322 if (asyw->image.interval) 323 asyw->image.mode = NV507C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING; 324 else 325 asyw->image.mode = NV507C_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE; 326 327 asyw->set.image = wndw->func->image_set != NULL; 328 } 329 330 if (wndw->func->scale_set) { 331 asyw->scale.sx = asyw->state.src_x >> 16; 332 asyw->scale.sy = asyw->state.src_y >> 16; 333 asyw->scale.sw = asyw->state.src_w >> 16; 334 asyw->scale.sh = asyw->state.src_h >> 16; 335 asyw->scale.dw = asyw->state.crtc_w; 336 asyw->scale.dh = asyw->state.crtc_h; 337 if (memcmp(&armw->scale, &asyw->scale, sizeof(asyw->scale))) 338 asyw->set.scale = true; 339 } 340 341 if (wndw->func->blend_set) { 342 asyw->blend.depth = 255 - asyw->state.normalized_zpos; 343 asyw->blend.k1 = asyw->state.alpha >> 8; 344 switch (asyw->state.pixel_blend_mode) { 345 case DRM_MODE_BLEND_PREMULTI: 346 asyw->blend.src_color = NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1; 347 asyw->blend.dst_color = NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC; 348 break; 349 case DRM_MODE_BLEND_COVERAGE: 350 asyw->blend.src_color = NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_SRC; 351 asyw->blend.dst_color = NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC; 352 break; 353 case DRM_MODE_BLEND_PIXEL_NONE: 354 default: 355 asyw->blend.src_color = NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1; 356 asyw->blend.dst_color = NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1; 357 break; 358 } 359 if (memcmp(&armw->blend, &asyw->blend, sizeof(asyw->blend))) 360 asyw->set.blend = true; 361 } 362 363 if (wndw->immd) { 364 asyw->point.x = asyw->state.crtc_x; 365 asyw->point.y = asyw->state.crtc_y; 366 if (memcmp(&armw->point, &asyw->point, sizeof(asyw->point))) 367 asyw->set.point = true; 368 } 369 370 return wndw->func->acquire(wndw, asyw, asyh); 371 } 372 373 static int 374 nv50_wndw_atomic_check_lut(struct nv50_wndw *wndw, 375 struct nv50_wndw_atom *armw, 376 struct nv50_wndw_atom *asyw, 377 struct nv50_head_atom *asyh) 378 { 379 struct drm_property_blob *ilut = asyh->state.degamma_lut; 380 381 /* I8 format without an input LUT makes no sense, and the 382 * HW error-checks for this. 383 * 384 * In order to handle legacy gamma, when there's no input 385 * LUT we need to steal the output LUT and use it instead. 386 */ 387 if (!ilut && asyw->state.fb->format->format == DRM_FORMAT_C8) { 388 /* This should be an error, but there's legacy clients 389 * that do a modeset before providing a gamma table. 390 * 391 * We keep the window disabled to avoid angering HW. 392 */ 393 if (!(ilut = asyh->state.gamma_lut)) { 394 asyw->visible = false; 395 return 0; 396 } 397 398 if (wndw->func->ilut) 399 asyh->wndw.olut |= BIT(wndw->id); 400 } else { 401 asyh->wndw.olut &= ~BIT(wndw->id); 402 } 403 404 if (!ilut && wndw->func->ilut_identity && 405 asyw->state.fb->format->format != DRM_FORMAT_XBGR16161616F && 406 asyw->state.fb->format->format != DRM_FORMAT_ABGR16161616F) { 407 static struct drm_property_blob dummy = {}; 408 ilut = &dummy; 409 } 410 411 /* Recalculate LUT state. */ 412 memset(&asyw->xlut, 0x00, sizeof(asyw->xlut)); 413 if ((asyw->ilut = wndw->func->ilut ? ilut : NULL)) { 414 wndw->func->ilut(wndw, asyw, drm_color_lut_size(ilut)); 415 asyw->xlut.handle = wndw->wndw.vram.handle; 416 asyw->xlut.i.buffer = !asyw->xlut.i.buffer; 417 asyw->set.xlut = true; 418 } else { 419 asyw->clr.xlut = armw->xlut.handle != 0; 420 } 421 422 /* Handle setting base SET_OUTPUT_LUT_LO_ENABLE_USE_CORE_LUT. */ 423 if (wndw->func->olut_core && 424 (!armw->visible || (armw->xlut.handle && !asyw->xlut.handle))) 425 asyw->set.xlut = true; 426 427 if (wndw->func->csc && asyh->state.ctm) { 428 const struct drm_color_ctm *ctm = asyh->state.ctm->data; 429 wndw->func->csc(wndw, asyw, ctm); 430 asyw->csc.valid = true; 431 asyw->set.csc = true; 432 } else { 433 asyw->csc.valid = false; 434 asyw->clr.csc = armw->csc.valid; 435 } 436 437 /* Can't do an immediate flip while changing the LUT. */ 438 asyh->state.async_flip = false; 439 return 0; 440 } 441 442 static int 443 nv50_wndw_atomic_check(struct drm_plane *plane, 444 struct drm_atomic_state *state) 445 { 446 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 447 plane); 448 struct nouveau_drm *drm = nouveau_drm(plane->dev); 449 struct nv50_wndw *wndw = nv50_wndw(plane); 450 struct nv50_wndw_atom *armw = nv50_wndw_atom(wndw->plane.state); 451 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 452 struct nv50_head_atom *harm = NULL, *asyh = NULL; 453 bool modeset = false; 454 int ret; 455 456 NV_ATOMIC(drm, "%s atomic_check\n", plane->name); 457 458 /* Fetch the assembly state for the head the window will belong to, 459 * and determine whether the window will be visible. 460 */ 461 if (asyw->state.crtc) { 462 asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc); 463 if (IS_ERR(asyh)) 464 return PTR_ERR(asyh); 465 modeset = drm_atomic_crtc_needs_modeset(&asyh->state); 466 asyw->visible = asyh->state.active; 467 } else { 468 asyw->visible = false; 469 } 470 471 /* Fetch assembly state for the head the window used to belong to. */ 472 if (armw->state.crtc) { 473 harm = nv50_head_atom_get(asyw->state.state, armw->state.crtc); 474 if (IS_ERR(harm)) 475 return PTR_ERR(harm); 476 } 477 478 /* LUT configuration can potentially cause the window to be disabled. */ 479 if (asyw->visible && wndw->func->xlut_set && 480 (!armw->visible || 481 asyh->state.color_mgmt_changed || 482 asyw->state.fb->format->format != 483 armw->state.fb->format->format)) { 484 ret = nv50_wndw_atomic_check_lut(wndw, armw, asyw, asyh); 485 if (ret) 486 return ret; 487 } 488 489 /* Calculate new window state. */ 490 if (asyw->visible) { 491 ret = nv50_wndw_atomic_check_acquire(wndw, modeset, 492 armw, asyw, asyh); 493 if (ret) 494 return ret; 495 496 asyh->wndw.mask |= BIT(wndw->id); 497 } else 498 if (armw->visible) { 499 nv50_wndw_atomic_check_release(wndw, asyw, harm); 500 harm->wndw.mask &= ~BIT(wndw->id); 501 } else { 502 return 0; 503 } 504 505 /* Aside from the obvious case where the window is actively being 506 * disabled, we might also need to temporarily disable the window 507 * when performing certain modeset operations. 508 */ 509 if (!asyw->visible || modeset) { 510 asyw->clr.ntfy = armw->ntfy.handle != 0; 511 asyw->clr.sema = armw->sema.handle != 0; 512 asyw->clr.xlut = armw->xlut.handle != 0; 513 if (asyw->clr.xlut && asyw->visible) 514 asyw->set.xlut = asyw->xlut.handle != 0; 515 asyw->clr.csc = armw->csc.valid; 516 if (wndw->func->image_clr) 517 asyw->clr.image = armw->image.handle[0] != 0; 518 } 519 520 return 0; 521 } 522 523 static void 524 nv50_wndw_cleanup_fb(struct drm_plane *plane, struct drm_plane_state *old_state) 525 { 526 struct nouveau_drm *drm = nouveau_drm(plane->dev); 527 struct nouveau_bo *nvbo; 528 529 NV_ATOMIC(drm, "%s cleanup: %p\n", plane->name, old_state->fb); 530 if (!old_state->fb) 531 return; 532 533 nvbo = nouveau_gem_object(old_state->fb->obj[0]); 534 nouveau_bo_unpin(nvbo); 535 } 536 537 static int 538 nv50_wndw_prepare_fb(struct drm_plane *plane, struct drm_plane_state *state) 539 { 540 struct drm_framebuffer *fb = state->fb; 541 struct nouveau_drm *drm = nouveau_drm(plane->dev); 542 struct nv50_wndw *wndw = nv50_wndw(plane); 543 struct nv50_wndw_atom *asyw = nv50_wndw_atom(state); 544 struct nouveau_bo *nvbo; 545 struct nv50_head_atom *asyh; 546 struct nv50_wndw_ctxdma *ctxdma; 547 int ret; 548 549 NV_ATOMIC(drm, "%s prepare: %p\n", plane->name, fb); 550 if (!asyw->state.fb) 551 return 0; 552 553 nvbo = nouveau_gem_object(fb->obj[0]); 554 ret = nouveau_bo_pin(nvbo, NOUVEAU_GEM_DOMAIN_VRAM, true); 555 if (ret) 556 return ret; 557 558 if (wndw->ctxdma.parent) { 559 ctxdma = nv50_wndw_ctxdma_new(wndw, fb); 560 if (IS_ERR(ctxdma)) { 561 nouveau_bo_unpin(nvbo); 562 return PTR_ERR(ctxdma); 563 } 564 565 if (asyw->visible) 566 asyw->image.handle[0] = ctxdma->object.handle; 567 } 568 569 ret = drm_gem_plane_helper_prepare_fb(plane, state); 570 if (ret) 571 return ret; 572 573 asyw->image.offset[0] = nvbo->offset; 574 575 if (wndw->func->prepare) { 576 asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc); 577 if (IS_ERR(asyh)) 578 return PTR_ERR(asyh); 579 580 wndw->func->prepare(wndw, asyh, asyw); 581 } 582 583 return 0; 584 } 585 586 /* Only used by drm_panic get_scanout_buffer() and set_pixel(), so it is 587 * protected by the drm panic spinlock 588 */ 589 static u32 nv50_panic_blk_h; 590 591 /* Return the framebuffer offset of the start of the block where pixel(x,y) is */ 592 static u32 593 nv50_get_block_off(unsigned int x, unsigned int y, unsigned int pitch) 594 { 595 u32 blk_x, blk_y, blk_columns; 596 597 blk_columns = nouveau_get_width_in_blocks(pitch); 598 blk_x = (x * 4) / NV_TILE_GOB_WIDTH_BYTES; 599 blk_y = y / nv50_panic_blk_h; 600 601 return ((blk_y * blk_columns) + blk_x) * NV_TILE_GOB_WIDTH_BYTES * nv50_panic_blk_h; 602 } 603 604 /* Turing and later have 2 level of tiles inside the block */ 605 static void 606 nv50_set_pixel_swizzle(struct drm_scanout_buffer *sb, unsigned int x, 607 unsigned int y, u32 color) 608 { 609 u32 blk_off, off, swizzle; 610 611 blk_off = nv50_get_block_off(x, y, sb->pitch[0]); 612 613 y = y % nv50_panic_blk_h; 614 615 /* Inside the block, use the fast address swizzle to compute the offset 616 * For nvidia blocklinear, bit order is yn..y3 x3 y2 x2 y1 y0 x1 x0 617 */ 618 swizzle = (x & 3) | (y & 3) << 2 | (x & 4) << 2 | (y & 4) << 3; 619 swizzle |= (x & 8) << 3 | (y >> 3) << 7; 620 off = blk_off + swizzle * 4; 621 622 iosys_map_wr(&sb->map[0], off, u32, color); 623 } 624 625 static void 626 nv50_set_pixel(struct drm_scanout_buffer *sb, unsigned int x, unsigned int y, 627 u32 color) 628 { 629 u32 blk_off, off; 630 631 blk_off = nv50_get_block_off(x, y, sb->width); 632 633 x = x % (NV_TILE_GOB_WIDTH_BYTES / 4); 634 y = y % nv50_panic_blk_h; 635 off = blk_off + x * 4 + y * NV_TILE_GOB_WIDTH_BYTES; 636 637 iosys_map_wr(&sb->map[0], off, u32, color); 638 } 639 640 static int 641 nv50_wndw_get_scanout_buffer(struct drm_plane *plane, struct drm_scanout_buffer *sb) 642 { 643 struct drm_framebuffer *fb; 644 struct nouveau_bo *nvbo; 645 struct nouveau_drm *drm = nouveau_drm(plane->dev); 646 u16 chipset = drm->client.device.info.chipset; 647 u8 family = drm->client.device.info.family; 648 u32 tile_mode; 649 u8 kind; 650 651 if (!plane->state || !plane->state->fb) 652 return -EINVAL; 653 654 fb = plane->state->fb; 655 nvbo = nouveau_gem_object(fb->obj[0]); 656 657 /* Don't support compressed format, or multiplane yet. */ 658 if (nvbo->comp || fb->format->num_planes != 1) 659 return -EOPNOTSUPP; 660 661 if (nouveau_bo_map(nvbo)) { 662 drm_warn(plane->dev, "nouveau bo map failed, panic won't be displayed\n"); 663 return -ENOMEM; 664 } 665 666 if (nvbo->kmap.bo_kmap_type & TTM_BO_MAP_IOMEM_MASK) 667 iosys_map_set_vaddr_iomem(&sb->map[0], (void __iomem *)nvbo->kmap.virtual); 668 else 669 iosys_map_set_vaddr(&sb->map[0], nvbo->kmap.virtual); 670 671 sb->height = fb->height; 672 sb->width = fb->width; 673 sb->pitch[0] = fb->pitches[0]; 674 sb->format = fb->format; 675 676 nouveau_framebuffer_get_layout(fb, &tile_mode, &kind); 677 if (kind) { 678 /* If tiling is enabled, use set_pixel() to display correctly. 679 * Only handle 32bits format for now. 680 */ 681 if (fb->format->cpp[0] != 4) 682 return -EOPNOTSUPP; 683 nv50_panic_blk_h = nouveau_get_gob_height(family) * 684 nouveau_get_gobs_in_block(tile_mode, chipset); 685 686 if (chipset >= 0x160) 687 sb->set_pixel = nv50_set_pixel_swizzle; 688 else 689 sb->set_pixel = nv50_set_pixel; 690 } 691 return 0; 692 } 693 694 static const struct drm_plane_helper_funcs 695 nv50_wndw_helper = { 696 .prepare_fb = nv50_wndw_prepare_fb, 697 .cleanup_fb = nv50_wndw_cleanup_fb, 698 .atomic_check = nv50_wndw_atomic_check, 699 }; 700 701 static const struct drm_plane_helper_funcs 702 nv50_wndw_primary_helper = { 703 .prepare_fb = nv50_wndw_prepare_fb, 704 .cleanup_fb = nv50_wndw_cleanup_fb, 705 .atomic_check = nv50_wndw_atomic_check, 706 .get_scanout_buffer = nv50_wndw_get_scanout_buffer, 707 }; 708 709 static void 710 nv50_wndw_atomic_destroy_state(struct drm_plane *plane, 711 struct drm_plane_state *state) 712 { 713 struct nv50_wndw_atom *asyw = nv50_wndw_atom(state); 714 __drm_atomic_helper_plane_destroy_state(&asyw->state); 715 kfree(asyw); 716 } 717 718 static struct drm_plane_state * 719 nv50_wndw_atomic_duplicate_state(struct drm_plane *plane) 720 { 721 struct nv50_wndw_atom *armw = nv50_wndw_atom(plane->state); 722 struct nv50_wndw_atom *asyw; 723 if (!(asyw = kmalloc(sizeof(*asyw), GFP_KERNEL))) 724 return NULL; 725 __drm_atomic_helper_plane_duplicate_state(plane, &asyw->state); 726 asyw->sema = armw->sema; 727 asyw->ntfy = armw->ntfy; 728 asyw->ilut = NULL; 729 asyw->xlut = armw->xlut; 730 asyw->csc = armw->csc; 731 asyw->image = armw->image; 732 asyw->point = armw->point; 733 asyw->clr.mask = 0; 734 asyw->set.mask = 0; 735 return &asyw->state; 736 } 737 738 static int 739 nv50_wndw_zpos_default(struct drm_plane *plane) 740 { 741 return (plane->type == DRM_PLANE_TYPE_PRIMARY) ? 0 : 742 (plane->type == DRM_PLANE_TYPE_OVERLAY) ? 1 : 255; 743 } 744 745 static void 746 nv50_wndw_reset(struct drm_plane *plane) 747 { 748 struct nv50_wndw_atom *asyw; 749 750 if (WARN_ON(!(asyw = kzalloc(sizeof(*asyw), GFP_KERNEL)))) 751 return; 752 753 if (plane->state) 754 plane->funcs->atomic_destroy_state(plane, plane->state); 755 756 __drm_atomic_helper_plane_reset(plane, &asyw->state); 757 } 758 759 static void 760 nv50_wndw_destroy(struct drm_plane *plane) 761 { 762 struct nv50_wndw *wndw = nv50_wndw(plane); 763 struct nv50_wndw_ctxdma *ctxdma, *ctxtmp; 764 765 list_for_each_entry_safe(ctxdma, ctxtmp, &wndw->ctxdma.list, head) { 766 nv50_wndw_ctxdma_del(ctxdma); 767 } 768 769 nv50_dmac_destroy(&wndw->wimm); 770 nv50_dmac_destroy(&wndw->wndw); 771 772 nv50_lut_fini(&wndw->ilut); 773 774 drm_plane_cleanup(&wndw->plane); 775 kfree(wndw); 776 } 777 778 /* This function assumes the format has already been validated against the plane 779 * and the modifier was validated against the device-wides modifier list at FB 780 * creation time. 781 */ 782 static bool nv50_plane_format_mod_supported(struct drm_plane *plane, 783 u32 format, u64 modifier) 784 { 785 struct nouveau_drm *drm = nouveau_drm(plane->dev); 786 uint8_t i; 787 788 if (drm->client.device.info.chipset < 0xc0) { 789 const struct drm_format_info *info = drm_format_info(format); 790 const uint8_t kind = (modifier >> 12) & 0xff; 791 792 if (!format) return false; 793 794 for (i = 0; i < info->num_planes; i++) 795 if ((info->cpp[i] != 4) && kind != 0x70) return false; 796 } 797 798 return true; 799 } 800 801 const struct drm_plane_funcs 802 nv50_wndw = { 803 .update_plane = drm_atomic_helper_update_plane, 804 .disable_plane = drm_atomic_helper_disable_plane, 805 .destroy = nv50_wndw_destroy, 806 .reset = nv50_wndw_reset, 807 .atomic_duplicate_state = nv50_wndw_atomic_duplicate_state, 808 .atomic_destroy_state = nv50_wndw_atomic_destroy_state, 809 .format_mod_supported = nv50_plane_format_mod_supported, 810 }; 811 812 static const u64 nv50_cursor_format_modifiers[] = { 813 DRM_FORMAT_MOD_LINEAR, 814 DRM_FORMAT_MOD_INVALID, 815 }; 816 817 int 818 nv50_wndw_new_(const struct nv50_wndw_func *func, struct drm_device *dev, 819 enum drm_plane_type type, const char *name, int index, 820 const u32 *format, u32 heads, 821 enum nv50_disp_interlock_type interlock_type, u32 interlock_data, 822 struct nv50_wndw **pwndw) 823 { 824 struct nouveau_drm *drm = nouveau_drm(dev); 825 struct nvif_mmu *mmu = &drm->client.mmu; 826 struct nv50_disp *disp = nv50_disp(dev); 827 struct nv50_wndw *wndw; 828 const u64 *format_modifiers; 829 int nformat; 830 int ret; 831 832 if (!(wndw = *pwndw = kzalloc(sizeof(*wndw), GFP_KERNEL))) 833 return -ENOMEM; 834 wndw->func = func; 835 wndw->id = index; 836 wndw->interlock.type = interlock_type; 837 wndw->interlock.data = interlock_data; 838 839 wndw->ctxdma.parent = &wndw->wndw.base.user; 840 INIT_LIST_HEAD(&wndw->ctxdma.list); 841 842 for (nformat = 0; format[nformat]; nformat++); 843 844 if (type == DRM_PLANE_TYPE_CURSOR) 845 format_modifiers = nv50_cursor_format_modifiers; 846 else 847 format_modifiers = nouveau_display(dev)->format_modifiers; 848 849 ret = drm_universal_plane_init(dev, &wndw->plane, heads, &nv50_wndw, format, nformat, 850 format_modifiers, type, "%s-%d", name, index); 851 if (ret) { 852 kfree(*pwndw); 853 *pwndw = NULL; 854 return ret; 855 } 856 857 if (type == DRM_PLANE_TYPE_PRIMARY) 858 drm_plane_helper_add(&wndw->plane, &nv50_wndw_primary_helper); 859 else 860 drm_plane_helper_add(&wndw->plane, &nv50_wndw_helper); 861 862 if (wndw->func->ilut) { 863 ret = nv50_lut_init(disp, mmu, &wndw->ilut); 864 if (ret) 865 return ret; 866 } 867 868 if (wndw->func->blend_set) { 869 ret = drm_plane_create_zpos_property(&wndw->plane, 870 nv50_wndw_zpos_default(&wndw->plane), 0, 254); 871 if (ret) 872 return ret; 873 874 ret = drm_plane_create_alpha_property(&wndw->plane); 875 if (ret) 876 return ret; 877 878 ret = drm_plane_create_blend_mode_property(&wndw->plane, 879 BIT(DRM_MODE_BLEND_PIXEL_NONE) | 880 BIT(DRM_MODE_BLEND_PREMULTI) | 881 BIT(DRM_MODE_BLEND_COVERAGE)); 882 if (ret) 883 return ret; 884 } else { 885 ret = drm_plane_create_zpos_immutable_property(&wndw->plane, 886 nv50_wndw_zpos_default(&wndw->plane)); 887 if (ret) 888 return ret; 889 } 890 891 return 0; 892 } 893 894 int 895 nv50_wndw_new(struct nouveau_drm *drm, enum drm_plane_type type, int index, 896 struct nv50_wndw **pwndw) 897 { 898 struct { 899 s32 oclass; 900 int version; 901 int (*new)(struct nouveau_drm *, enum drm_plane_type, 902 int, s32, struct nv50_wndw **); 903 } wndws[] = { 904 { GA102_DISP_WINDOW_CHANNEL_DMA, 0, wndwc67e_new }, 905 { TU102_DISP_WINDOW_CHANNEL_DMA, 0, wndwc57e_new }, 906 { GV100_DISP_WINDOW_CHANNEL_DMA, 0, wndwc37e_new }, 907 {} 908 }; 909 struct nv50_disp *disp = nv50_disp(drm->dev); 910 int cid, ret; 911 912 cid = nvif_mclass(&disp->disp->object, wndws); 913 if (cid < 0) { 914 NV_ERROR(drm, "No supported window class\n"); 915 return cid; 916 } 917 918 ret = wndws[cid].new(drm, type, index, wndws[cid].oclass, pwndw); 919 if (ret) 920 return ret; 921 922 return nv50_wimm_init(drm, *pwndw); 923 } 924