1 /* 2 * Copyright 2018 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #include "wndw.h" 23 #include "wimm.h" 24 #include "handles.h" 25 26 #include <nvif/class.h> 27 #include <nvif/cl0002.h> 28 29 #include <nvhw/class/cl507c.h> 30 #include <nvhw/class/cl507e.h> 31 #include <nvhw/class/clc37e.h> 32 33 #include <drm/drm_atomic_helper.h> 34 #include <drm/drm_fourcc.h> 35 36 #include "nouveau_bo.h" 37 #include "nouveau_gem.h" 38 39 static void 40 nv50_wndw_ctxdma_del(struct nv50_wndw_ctxdma *ctxdma) 41 { 42 nvif_object_dtor(&ctxdma->object); 43 list_del(&ctxdma->head); 44 kfree(ctxdma); 45 } 46 47 static struct nv50_wndw_ctxdma * 48 nv50_wndw_ctxdma_new(struct nv50_wndw *wndw, struct drm_framebuffer *fb) 49 { 50 struct nouveau_drm *drm = nouveau_drm(fb->dev); 51 struct nv50_wndw_ctxdma *ctxdma; 52 u32 handle; 53 u32 unused; 54 u8 kind; 55 struct { 56 struct nv_dma_v0 base; 57 union { 58 struct nv50_dma_v0 nv50; 59 struct gf100_dma_v0 gf100; 60 struct gf119_dma_v0 gf119; 61 }; 62 } args = {}; 63 u32 argc = sizeof(args.base); 64 int ret; 65 66 nouveau_framebuffer_get_layout(fb, &unused, &kind); 67 handle = NV50_DISP_HANDLE_WNDW_CTX(kind); 68 69 list_for_each_entry(ctxdma, &wndw->ctxdma.list, head) { 70 if (ctxdma->object.handle == handle) 71 return ctxdma; 72 } 73 74 if (!(ctxdma = kzalloc(sizeof(*ctxdma), GFP_KERNEL))) 75 return ERR_PTR(-ENOMEM); 76 list_add(&ctxdma->head, &wndw->ctxdma.list); 77 78 args.base.target = NV_DMA_V0_TARGET_VRAM; 79 args.base.access = NV_DMA_V0_ACCESS_RDWR; 80 args.base.start = 0; 81 args.base.limit = drm->client.device.info.ram_user - 1; 82 83 if (drm->client.device.info.chipset < 0x80) { 84 args.nv50.part = NV50_DMA_V0_PART_256; 85 argc += sizeof(args.nv50); 86 } else 87 if (drm->client.device.info.chipset < 0xc0) { 88 args.nv50.part = NV50_DMA_V0_PART_256; 89 args.nv50.kind = kind; 90 argc += sizeof(args.nv50); 91 } else 92 if (drm->client.device.info.chipset < 0xd0) { 93 args.gf100.kind = kind; 94 argc += sizeof(args.gf100); 95 } else { 96 args.gf119.page = GF119_DMA_V0_PAGE_LP; 97 args.gf119.kind = kind; 98 argc += sizeof(args.gf119); 99 } 100 101 ret = nvif_object_ctor(wndw->ctxdma.parent, "kmsFbCtxDma", handle, 102 NV_DMA_IN_MEMORY, &args, argc, &ctxdma->object); 103 if (ret) { 104 nv50_wndw_ctxdma_del(ctxdma); 105 return ERR_PTR(ret); 106 } 107 108 return ctxdma; 109 } 110 111 int 112 nv50_wndw_wait_armed(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) 113 { 114 struct nv50_disp *disp = nv50_disp(wndw->plane.dev); 115 if (asyw->set.ntfy) { 116 return wndw->func->ntfy_wait_begun(disp->sync, 117 asyw->ntfy.offset, 118 wndw->wndw.base.device); 119 } 120 return 0; 121 } 122 123 void 124 nv50_wndw_flush_clr(struct nv50_wndw *wndw, u32 *interlock, bool flush, 125 struct nv50_wndw_atom *asyw) 126 { 127 union nv50_wndw_atom_mask clr = { 128 .mask = asyw->clr.mask & ~(flush ? 0 : asyw->set.mask), 129 }; 130 if (clr.sema ) wndw->func-> sema_clr(wndw); 131 if (clr.ntfy ) wndw->func-> ntfy_clr(wndw); 132 if (clr.xlut ) wndw->func-> xlut_clr(wndw); 133 if (clr.csc ) wndw->func-> csc_clr(wndw); 134 if (clr.image) wndw->func->image_clr(wndw); 135 136 interlock[wndw->interlock.type] |= wndw->interlock.data; 137 } 138 139 void 140 nv50_wndw_flush_set(struct nv50_wndw *wndw, u32 *interlock, 141 struct nv50_wndw_atom *asyw) 142 { 143 if (interlock[NV50_DISP_INTERLOCK_CORE]) { 144 asyw->image.mode = NV507C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING; 145 asyw->image.interval = 1; 146 } 147 148 if (asyw->set.sema ) wndw->func->sema_set (wndw, asyw); 149 if (asyw->set.ntfy ) wndw->func->ntfy_set (wndw, asyw); 150 if (asyw->set.image) wndw->func->image_set(wndw, asyw); 151 152 if (asyw->set.xlut ) { 153 if (asyw->ilut) { 154 asyw->xlut.i.offset = 155 nv50_lut_load(&wndw->ilut, asyw->xlut.i.buffer, 156 asyw->ilut, asyw->xlut.i.load); 157 } 158 wndw->func->xlut_set(wndw, asyw); 159 } 160 161 if (asyw->set.csc ) wndw->func->csc_set (wndw, asyw); 162 if (asyw->set.scale) wndw->func->scale_set(wndw, asyw); 163 if (asyw->set.blend) wndw->func->blend_set(wndw, asyw); 164 if (asyw->set.point) { 165 if (asyw->set.point = false, asyw->set.mask) 166 interlock[wndw->interlock.type] |= wndw->interlock.data; 167 interlock[NV50_DISP_INTERLOCK_WIMM] |= wndw->interlock.wimm; 168 169 wndw->immd->point(wndw, asyw); 170 wndw->immd->update(wndw, interlock); 171 } else { 172 interlock[wndw->interlock.type] |= wndw->interlock.data; 173 } 174 } 175 176 void 177 nv50_wndw_ntfy_enable(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) 178 { 179 struct nv50_disp *disp = nv50_disp(wndw->plane.dev); 180 181 asyw->ntfy.handle = wndw->wndw.sync.handle; 182 asyw->ntfy.offset = wndw->ntfy; 183 asyw->ntfy.awaken = false; 184 asyw->set.ntfy = true; 185 186 wndw->func->ntfy_reset(disp->sync, wndw->ntfy); 187 wndw->ntfy ^= 0x10; 188 } 189 190 static void 191 nv50_wndw_atomic_check_release(struct nv50_wndw *wndw, 192 struct nv50_wndw_atom *asyw, 193 struct nv50_head_atom *asyh) 194 { 195 struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev); 196 NV_ATOMIC(drm, "%s release\n", wndw->plane.name); 197 wndw->func->release(wndw, asyw, asyh); 198 asyw->ntfy.handle = 0; 199 asyw->sema.handle = 0; 200 asyw->xlut.handle = 0; 201 memset(asyw->image.handle, 0x00, sizeof(asyw->image.handle)); 202 } 203 204 static int 205 nv50_wndw_atomic_check_acquire_yuv(struct nv50_wndw_atom *asyw) 206 { 207 switch (asyw->state.fb->format->format) { 208 case DRM_FORMAT_YUYV: 209 asyw->image.format = NV507E_SURFACE_SET_PARAMS_FORMAT_VE8YO8UE8YE8; 210 break; 211 case DRM_FORMAT_UYVY: 212 asyw->image.format = NV507E_SURFACE_SET_PARAMS_FORMAT_YO8VE8YE8UE8; 213 break; 214 default: 215 WARN_ON(1); 216 return -EINVAL; 217 } 218 219 asyw->image.colorspace = NV507E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_601; 220 return 0; 221 } 222 223 static int 224 nv50_wndw_atomic_check_acquire_rgb(struct nv50_wndw_atom *asyw) 225 { 226 switch (asyw->state.fb->format->format) { 227 case DRM_FORMAT_C8: 228 asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_I8; 229 break; 230 case DRM_FORMAT_XRGB8888: 231 case DRM_FORMAT_ARGB8888: 232 asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8; 233 break; 234 case DRM_FORMAT_RGB565: 235 asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_R5G6B5; 236 break; 237 case DRM_FORMAT_XRGB1555: 238 case DRM_FORMAT_ARGB1555: 239 asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5; 240 break; 241 case DRM_FORMAT_XBGR2101010: 242 case DRM_FORMAT_ABGR2101010: 243 asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10; 244 break; 245 case DRM_FORMAT_XBGR8888: 246 case DRM_FORMAT_ABGR8888: 247 asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_A8B8G8R8; 248 break; 249 case DRM_FORMAT_XRGB2101010: 250 case DRM_FORMAT_ARGB2101010: 251 asyw->image.format = NVC37E_SET_PARAMS_FORMAT_A2R10G10B10; 252 break; 253 case DRM_FORMAT_XBGR16161616F: 254 case DRM_FORMAT_ABGR16161616F: 255 asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16; 256 break; 257 default: 258 return -EINVAL; 259 } 260 261 asyw->image.colorspace = NV507E_SURFACE_SET_PARAMS_COLOR_SPACE_RGB; 262 return 0; 263 } 264 265 static int 266 nv50_wndw_atomic_check_acquire(struct nv50_wndw *wndw, bool modeset, 267 struct nv50_wndw_atom *armw, 268 struct nv50_wndw_atom *asyw, 269 struct nv50_head_atom *asyh) 270 { 271 struct drm_framebuffer *fb = asyw->state.fb; 272 struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev); 273 uint8_t kind; 274 uint32_t tile_mode; 275 int ret; 276 277 NV_ATOMIC(drm, "%s acquire\n", wndw->plane.name); 278 279 if (fb != armw->state.fb || !armw->visible || modeset) { 280 nouveau_framebuffer_get_layout(fb, &tile_mode, &kind); 281 282 asyw->image.w = fb->width; 283 asyw->image.h = fb->height; 284 asyw->image.kind = kind; 285 286 ret = nv50_wndw_atomic_check_acquire_rgb(asyw); 287 if (ret) { 288 ret = nv50_wndw_atomic_check_acquire_yuv(asyw); 289 if (ret) 290 return ret; 291 } 292 293 if (asyw->image.kind) { 294 asyw->image.layout = NV507C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR; 295 if (drm->client.device.info.chipset >= 0xc0) 296 asyw->image.blockh = tile_mode >> 4; 297 else 298 asyw->image.blockh = tile_mode; 299 asyw->image.blocks[0] = fb->pitches[0] / 64; 300 asyw->image.pitch[0] = 0; 301 } else { 302 asyw->image.layout = NV507C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH; 303 asyw->image.blockh = NV507C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB; 304 asyw->image.blocks[0] = 0; 305 asyw->image.pitch[0] = fb->pitches[0]; 306 } 307 308 if (!asyh->state.async_flip) 309 asyw->image.interval = 1; 310 else 311 asyw->image.interval = 0; 312 313 if (asyw->image.interval) 314 asyw->image.mode = NV507C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING; 315 else 316 asyw->image.mode = NV507C_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE; 317 318 asyw->set.image = wndw->func->image_set != NULL; 319 } 320 321 if (wndw->func->scale_set) { 322 asyw->scale.sx = asyw->state.src_x >> 16; 323 asyw->scale.sy = asyw->state.src_y >> 16; 324 asyw->scale.sw = asyw->state.src_w >> 16; 325 asyw->scale.sh = asyw->state.src_h >> 16; 326 asyw->scale.dw = asyw->state.crtc_w; 327 asyw->scale.dh = asyw->state.crtc_h; 328 if (memcmp(&armw->scale, &asyw->scale, sizeof(asyw->scale))) 329 asyw->set.scale = true; 330 } 331 332 if (wndw->func->blend_set) { 333 asyw->blend.depth = 255 - asyw->state.normalized_zpos; 334 asyw->blend.k1 = asyw->state.alpha >> 8; 335 switch (asyw->state.pixel_blend_mode) { 336 case DRM_MODE_BLEND_PREMULTI: 337 asyw->blend.src_color = NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1; 338 asyw->blend.dst_color = NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC; 339 break; 340 case DRM_MODE_BLEND_COVERAGE: 341 asyw->blend.src_color = NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_SRC; 342 asyw->blend.dst_color = NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC; 343 break; 344 case DRM_MODE_BLEND_PIXEL_NONE: 345 default: 346 asyw->blend.src_color = NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1; 347 asyw->blend.dst_color = NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1; 348 break; 349 } 350 if (memcmp(&armw->blend, &asyw->blend, sizeof(asyw->blend))) 351 asyw->set.blend = true; 352 } 353 354 if (wndw->immd) { 355 asyw->point.x = asyw->state.crtc_x; 356 asyw->point.y = asyw->state.crtc_y; 357 if (memcmp(&armw->point, &asyw->point, sizeof(asyw->point))) 358 asyw->set.point = true; 359 } 360 361 return wndw->func->acquire(wndw, asyw, asyh); 362 } 363 364 static int 365 nv50_wndw_atomic_check_lut(struct nv50_wndw *wndw, 366 struct nv50_wndw_atom *armw, 367 struct nv50_wndw_atom *asyw, 368 struct nv50_head_atom *asyh) 369 { 370 struct drm_property_blob *ilut = asyh->state.degamma_lut; 371 372 /* I8 format without an input LUT makes no sense, and the 373 * HW error-checks for this. 374 * 375 * In order to handle legacy gamma, when there's no input 376 * LUT we need to steal the output LUT and use it instead. 377 */ 378 if (!ilut && asyw->state.fb->format->format == DRM_FORMAT_C8) { 379 /* This should be an error, but there's legacy clients 380 * that do a modeset before providing a gamma table. 381 * 382 * We keep the window disabled to avoid angering HW. 383 */ 384 if (!(ilut = asyh->state.gamma_lut)) { 385 asyw->visible = false; 386 return 0; 387 } 388 389 if (wndw->func->ilut) 390 asyh->wndw.olut |= BIT(wndw->id); 391 } else { 392 asyh->wndw.olut &= ~BIT(wndw->id); 393 } 394 395 if (!ilut && wndw->func->ilut_identity && 396 asyw->state.fb->format->format != DRM_FORMAT_XBGR16161616F && 397 asyw->state.fb->format->format != DRM_FORMAT_ABGR16161616F) { 398 static struct drm_property_blob dummy = {}; 399 ilut = &dummy; 400 } 401 402 /* Recalculate LUT state. */ 403 memset(&asyw->xlut, 0x00, sizeof(asyw->xlut)); 404 if ((asyw->ilut = wndw->func->ilut ? ilut : NULL)) { 405 if (!wndw->func->ilut(wndw, asyw, drm_color_lut_size(ilut))) { 406 DRM_DEBUG_KMS("Invalid ilut\n"); 407 return -EINVAL; 408 } 409 asyw->xlut.handle = wndw->wndw.vram.handle; 410 asyw->xlut.i.buffer = !asyw->xlut.i.buffer; 411 asyw->set.xlut = true; 412 } else { 413 asyw->clr.xlut = armw->xlut.handle != 0; 414 } 415 416 /* Handle setting base SET_OUTPUT_LUT_LO_ENABLE_USE_CORE_LUT. */ 417 if (wndw->func->olut_core && 418 (!armw->visible || (armw->xlut.handle && !asyw->xlut.handle))) 419 asyw->set.xlut = true; 420 421 if (wndw->func->csc && asyh->state.ctm) { 422 const struct drm_color_ctm *ctm = asyh->state.ctm->data; 423 wndw->func->csc(wndw, asyw, ctm); 424 asyw->csc.valid = true; 425 asyw->set.csc = true; 426 } else { 427 asyw->csc.valid = false; 428 asyw->clr.csc = armw->csc.valid; 429 } 430 431 /* Can't do an immediate flip while changing the LUT. */ 432 asyh->state.async_flip = false; 433 return 0; 434 } 435 436 static int 437 nv50_wndw_atomic_check(struct drm_plane *plane, struct drm_plane_state *state) 438 { 439 struct nouveau_drm *drm = nouveau_drm(plane->dev); 440 struct nv50_wndw *wndw = nv50_wndw(plane); 441 struct nv50_wndw_atom *armw = nv50_wndw_atom(wndw->plane.state); 442 struct nv50_wndw_atom *asyw = nv50_wndw_atom(state); 443 struct nv50_head_atom *harm = NULL, *asyh = NULL; 444 bool modeset = false; 445 int ret; 446 447 NV_ATOMIC(drm, "%s atomic_check\n", plane->name); 448 449 /* Fetch the assembly state for the head the window will belong to, 450 * and determine whether the window will be visible. 451 */ 452 if (asyw->state.crtc) { 453 asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc); 454 if (IS_ERR(asyh)) 455 return PTR_ERR(asyh); 456 modeset = drm_atomic_crtc_needs_modeset(&asyh->state); 457 asyw->visible = asyh->state.active; 458 } else { 459 asyw->visible = false; 460 } 461 462 /* Fetch assembly state for the head the window used to belong to. */ 463 if (armw->state.crtc) { 464 harm = nv50_head_atom_get(asyw->state.state, armw->state.crtc); 465 if (IS_ERR(harm)) 466 return PTR_ERR(harm); 467 } 468 469 /* LUT configuration can potentially cause the window to be disabled. */ 470 if (asyw->visible && wndw->func->xlut_set && 471 (!armw->visible || 472 asyh->state.color_mgmt_changed || 473 asyw->state.fb->format->format != 474 armw->state.fb->format->format)) { 475 ret = nv50_wndw_atomic_check_lut(wndw, armw, asyw, asyh); 476 if (ret) 477 return ret; 478 } 479 480 /* Calculate new window state. */ 481 if (asyw->visible) { 482 ret = nv50_wndw_atomic_check_acquire(wndw, modeset, 483 armw, asyw, asyh); 484 if (ret) 485 return ret; 486 487 asyh->wndw.mask |= BIT(wndw->id); 488 } else 489 if (armw->visible) { 490 nv50_wndw_atomic_check_release(wndw, asyw, harm); 491 harm->wndw.mask &= ~BIT(wndw->id); 492 } else { 493 return 0; 494 } 495 496 /* Aside from the obvious case where the window is actively being 497 * disabled, we might also need to temporarily disable the window 498 * when performing certain modeset operations. 499 */ 500 if (!asyw->visible || modeset) { 501 asyw->clr.ntfy = armw->ntfy.handle != 0; 502 asyw->clr.sema = armw->sema.handle != 0; 503 asyw->clr.xlut = armw->xlut.handle != 0; 504 if (asyw->clr.xlut && asyw->visible) 505 asyw->set.xlut = asyw->xlut.handle != 0; 506 asyw->clr.csc = armw->csc.valid; 507 if (wndw->func->image_clr) 508 asyw->clr.image = armw->image.handle[0] != 0; 509 } 510 511 return 0; 512 } 513 514 static void 515 nv50_wndw_cleanup_fb(struct drm_plane *plane, struct drm_plane_state *old_state) 516 { 517 struct nouveau_drm *drm = nouveau_drm(plane->dev); 518 struct nouveau_bo *nvbo; 519 520 NV_ATOMIC(drm, "%s cleanup: %p\n", plane->name, old_state->fb); 521 if (!old_state->fb) 522 return; 523 524 nvbo = nouveau_gem_object(old_state->fb->obj[0]); 525 nouveau_bo_unpin(nvbo); 526 } 527 528 static int 529 nv50_wndw_prepare_fb(struct drm_plane *plane, struct drm_plane_state *state) 530 { 531 struct drm_framebuffer *fb = state->fb; 532 struct nouveau_drm *drm = nouveau_drm(plane->dev); 533 struct nv50_wndw *wndw = nv50_wndw(plane); 534 struct nv50_wndw_atom *asyw = nv50_wndw_atom(state); 535 struct nouveau_bo *nvbo; 536 struct nv50_head_atom *asyh; 537 struct nv50_wndw_ctxdma *ctxdma; 538 int ret; 539 540 NV_ATOMIC(drm, "%s prepare: %p\n", plane->name, fb); 541 if (!asyw->state.fb) 542 return 0; 543 544 nvbo = nouveau_gem_object(fb->obj[0]); 545 ret = nouveau_bo_pin(nvbo, NOUVEAU_GEM_DOMAIN_VRAM, true); 546 if (ret) 547 return ret; 548 549 if (wndw->ctxdma.parent) { 550 ctxdma = nv50_wndw_ctxdma_new(wndw, fb); 551 if (IS_ERR(ctxdma)) { 552 nouveau_bo_unpin(nvbo); 553 return PTR_ERR(ctxdma); 554 } 555 556 if (asyw->visible) 557 asyw->image.handle[0] = ctxdma->object.handle; 558 } 559 560 asyw->state.fence = dma_resv_get_excl_rcu(nvbo->bo.base.resv); 561 asyw->image.offset[0] = nvbo->offset; 562 563 if (wndw->func->prepare) { 564 asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc); 565 if (IS_ERR(asyh)) 566 return PTR_ERR(asyh); 567 568 wndw->func->prepare(wndw, asyh, asyw); 569 } 570 571 return 0; 572 } 573 574 static const struct drm_plane_helper_funcs 575 nv50_wndw_helper = { 576 .prepare_fb = nv50_wndw_prepare_fb, 577 .cleanup_fb = nv50_wndw_cleanup_fb, 578 .atomic_check = nv50_wndw_atomic_check, 579 }; 580 581 static void 582 nv50_wndw_atomic_destroy_state(struct drm_plane *plane, 583 struct drm_plane_state *state) 584 { 585 struct nv50_wndw_atom *asyw = nv50_wndw_atom(state); 586 __drm_atomic_helper_plane_destroy_state(&asyw->state); 587 kfree(asyw); 588 } 589 590 static struct drm_plane_state * 591 nv50_wndw_atomic_duplicate_state(struct drm_plane *plane) 592 { 593 struct nv50_wndw_atom *armw = nv50_wndw_atom(plane->state); 594 struct nv50_wndw_atom *asyw; 595 if (!(asyw = kmalloc(sizeof(*asyw), GFP_KERNEL))) 596 return NULL; 597 __drm_atomic_helper_plane_duplicate_state(plane, &asyw->state); 598 asyw->sema = armw->sema; 599 asyw->ntfy = armw->ntfy; 600 asyw->ilut = NULL; 601 asyw->xlut = armw->xlut; 602 asyw->csc = armw->csc; 603 asyw->image = armw->image; 604 asyw->point = armw->point; 605 asyw->clr.mask = 0; 606 asyw->set.mask = 0; 607 return &asyw->state; 608 } 609 610 static int 611 nv50_wndw_zpos_default(struct drm_plane *plane) 612 { 613 return (plane->type == DRM_PLANE_TYPE_PRIMARY) ? 0 : 614 (plane->type == DRM_PLANE_TYPE_OVERLAY) ? 1 : 255; 615 } 616 617 static void 618 nv50_wndw_reset(struct drm_plane *plane) 619 { 620 struct nv50_wndw_atom *asyw; 621 622 if (WARN_ON(!(asyw = kzalloc(sizeof(*asyw), GFP_KERNEL)))) 623 return; 624 625 if (plane->state) 626 plane->funcs->atomic_destroy_state(plane, plane->state); 627 628 __drm_atomic_helper_plane_reset(plane, &asyw->state); 629 plane->state->zpos = nv50_wndw_zpos_default(plane); 630 plane->state->normalized_zpos = nv50_wndw_zpos_default(plane); 631 } 632 633 static void 634 nv50_wndw_destroy(struct drm_plane *plane) 635 { 636 struct nv50_wndw *wndw = nv50_wndw(plane); 637 struct nv50_wndw_ctxdma *ctxdma, *ctxtmp; 638 639 list_for_each_entry_safe(ctxdma, ctxtmp, &wndw->ctxdma.list, head) { 640 nv50_wndw_ctxdma_del(ctxdma); 641 } 642 643 nvif_notify_dtor(&wndw->notify); 644 nv50_dmac_destroy(&wndw->wimm); 645 nv50_dmac_destroy(&wndw->wndw); 646 647 nv50_lut_fini(&wndw->ilut); 648 649 drm_plane_cleanup(&wndw->plane); 650 kfree(wndw); 651 } 652 653 /* This function assumes the format has already been validated against the plane 654 * and the modifier was validated against the device-wides modifier list at FB 655 * creation time. 656 */ 657 static bool nv50_plane_format_mod_supported(struct drm_plane *plane, 658 u32 format, u64 modifier) 659 { 660 struct nouveau_drm *drm = nouveau_drm(plane->dev); 661 uint8_t i; 662 663 if (drm->client.device.info.chipset < 0xc0) { 664 const struct drm_format_info *info = drm_format_info(format); 665 const uint8_t kind = (modifier >> 12) & 0xff; 666 667 if (!format) return false; 668 669 for (i = 0; i < info->num_planes; i++) 670 if ((info->cpp[i] != 4) && kind != 0x70) return false; 671 } 672 673 return true; 674 } 675 676 const struct drm_plane_funcs 677 nv50_wndw = { 678 .update_plane = drm_atomic_helper_update_plane, 679 .disable_plane = drm_atomic_helper_disable_plane, 680 .destroy = nv50_wndw_destroy, 681 .reset = nv50_wndw_reset, 682 .atomic_duplicate_state = nv50_wndw_atomic_duplicate_state, 683 .atomic_destroy_state = nv50_wndw_atomic_destroy_state, 684 .format_mod_supported = nv50_plane_format_mod_supported, 685 }; 686 687 static int 688 nv50_wndw_notify(struct nvif_notify *notify) 689 { 690 return NVIF_NOTIFY_KEEP; 691 } 692 693 void 694 nv50_wndw_fini(struct nv50_wndw *wndw) 695 { 696 nvif_notify_put(&wndw->notify); 697 } 698 699 void 700 nv50_wndw_init(struct nv50_wndw *wndw) 701 { 702 nvif_notify_get(&wndw->notify); 703 } 704 705 int 706 nv50_wndw_new_(const struct nv50_wndw_func *func, struct drm_device *dev, 707 enum drm_plane_type type, const char *name, int index, 708 const u32 *format, u32 heads, 709 enum nv50_disp_interlock_type interlock_type, u32 interlock_data, 710 struct nv50_wndw **pwndw) 711 { 712 struct nouveau_drm *drm = nouveau_drm(dev); 713 struct nvif_mmu *mmu = &drm->client.mmu; 714 struct nv50_disp *disp = nv50_disp(dev); 715 struct nv50_wndw *wndw; 716 int nformat; 717 int ret; 718 719 if (!(wndw = *pwndw = kzalloc(sizeof(*wndw), GFP_KERNEL))) 720 return -ENOMEM; 721 wndw->func = func; 722 wndw->id = index; 723 wndw->interlock.type = interlock_type; 724 wndw->interlock.data = interlock_data; 725 726 wndw->ctxdma.parent = &wndw->wndw.base.user; 727 INIT_LIST_HEAD(&wndw->ctxdma.list); 728 729 for (nformat = 0; format[nformat]; nformat++); 730 731 ret = drm_universal_plane_init(dev, &wndw->plane, heads, &nv50_wndw, 732 format, nformat, 733 nouveau_display(dev)->format_modifiers, 734 type, "%s-%d", name, index); 735 if (ret) { 736 kfree(*pwndw); 737 *pwndw = NULL; 738 return ret; 739 } 740 741 drm_plane_helper_add(&wndw->plane, &nv50_wndw_helper); 742 743 if (wndw->func->ilut) { 744 ret = nv50_lut_init(disp, mmu, &wndw->ilut); 745 if (ret) 746 return ret; 747 } 748 749 wndw->notify.func = nv50_wndw_notify; 750 751 if (wndw->func->blend_set) { 752 ret = drm_plane_create_zpos_property(&wndw->plane, 753 nv50_wndw_zpos_default(&wndw->plane), 0, 254); 754 if (ret) 755 return ret; 756 757 ret = drm_plane_create_alpha_property(&wndw->plane); 758 if (ret) 759 return ret; 760 761 ret = drm_plane_create_blend_mode_property(&wndw->plane, 762 BIT(DRM_MODE_BLEND_PIXEL_NONE) | 763 BIT(DRM_MODE_BLEND_PREMULTI) | 764 BIT(DRM_MODE_BLEND_COVERAGE)); 765 if (ret) 766 return ret; 767 } else { 768 ret = drm_plane_create_zpos_immutable_property(&wndw->plane, 769 nv50_wndw_zpos_default(&wndw->plane)); 770 if (ret) 771 return ret; 772 } 773 774 return 0; 775 } 776 777 int 778 nv50_wndw_new(struct nouveau_drm *drm, enum drm_plane_type type, int index, 779 struct nv50_wndw **pwndw) 780 { 781 struct { 782 s32 oclass; 783 int version; 784 int (*new)(struct nouveau_drm *, enum drm_plane_type, 785 int, s32, struct nv50_wndw **); 786 } wndws[] = { 787 { GA102_DISP_WINDOW_CHANNEL_DMA, 0, wndwc67e_new }, 788 { TU102_DISP_WINDOW_CHANNEL_DMA, 0, wndwc57e_new }, 789 { GV100_DISP_WINDOW_CHANNEL_DMA, 0, wndwc37e_new }, 790 {} 791 }; 792 struct nv50_disp *disp = nv50_disp(drm->dev); 793 int cid, ret; 794 795 cid = nvif_mclass(&disp->disp->object, wndws); 796 if (cid < 0) { 797 NV_ERROR(drm, "No supported window class\n"); 798 return cid; 799 } 800 801 ret = wndws[cid].new(drm, type, index, wndws[cid].oclass, pwndw); 802 if (ret) 803 return ret; 804 805 return nv50_wimm_init(drm, *pwndw); 806 } 807