1 /* SPDX-License-Identifier: MIT 2 * 3 * Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. 4 */ 5 #include "head.h" 6 #include "atom.h" 7 #include "core.h" 8 9 #include <nvif/pushc97b.h> 10 11 #include <nvhw/class/clca7d.h> 12 13 static int 14 headca7d_display_id(struct nv50_head *head, u32 display_id) 15 { 16 struct nvif_push *push = &head->disp->core->chan.push; 17 const int i = head->base.index; 18 int ret; 19 20 ret = PUSH_WAIT(push, 2); 21 if (ret) 22 return ret; 23 24 PUSH_MTHD(push, NVCA7D, HEAD_SET_DISPLAY_ID(i, 0), display_id); 25 26 return 0; 27 } 28 29 static int 30 headca7d_or(struct nv50_head *head, struct nv50_head_atom *asyh) 31 { 32 struct nvif_push *push = &head->disp->core->chan.push; 33 const int i = head->base.index; 34 u8 depth; 35 int ret; 36 37 switch (asyh->or.depth) { 38 case 6: 39 depth = NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444; 40 break; 41 case 5: 42 depth = NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444; 43 break; 44 case 2: 45 depth = NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444; 46 break; 47 case 0: 48 depth = NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444; 49 break; 50 default: 51 WARN_ON(1); 52 return -EINVAL; 53 } 54 55 ret = PUSH_WAIT(push, 2); 56 if (ret) 57 return ret; 58 59 PUSH_MTHD(push, NVCA7D, HEAD_SET_CONTROL_OUTPUT_RESOURCE(i), 60 NVVAL(NVCA7D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, CRC_MODE, asyh->or.crc_raster) | 61 NVVAL(NVCA7D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, HSYNC_POLARITY, asyh->or.nhsync) | 62 NVVAL(NVCA7D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, VSYNC_POLARITY, asyh->or.nvsync) | 63 NVVAL(NVCA7D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, PIXEL_DEPTH, depth) | 64 NVDEF(NVCA7D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, COLOR_SPACE_OVERRIDE, DISABLE) | 65 NVDEF(NVCA7D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, EXT_PACKET_WIN, NONE)); 66 67 return 0; 68 } 69 70 static int 71 headca7d_procamp(struct nv50_head *head, struct nv50_head_atom *asyh) 72 { 73 struct nvif_push *push = &head->disp->core->chan.push; 74 const int i = head->base.index; 75 int ret; 76 77 ret = PUSH_WAIT(push, 2); 78 if (ret) 79 return ret; 80 81 PUSH_MTHD(push, NVCA7D, HEAD_SET_PROCAMP(i), 82 NVDEF(NVCA7D, HEAD_SET_PROCAMP, COLOR_SPACE, RGB) | 83 NVDEF(NVCA7D, HEAD_SET_PROCAMP, CHROMA_LPF, DISABLE) | 84 NVDEF(NVCA7D, HEAD_SET_PROCAMP, DYNAMIC_RANGE, VESA)); 85 86 return 0; 87 } 88 89 static int 90 headca7d_dither(struct nv50_head *head, struct nv50_head_atom *asyh) 91 { 92 struct nvif_push *push = &head->disp->core->chan.push; 93 const int i = head->base.index; 94 int ret; 95 96 ret = PUSH_WAIT(push, 2); 97 if (ret) 98 return ret; 99 100 PUSH_MTHD(push, NVCA7D, HEAD_SET_DITHER_CONTROL(i), 101 NVVAL(NVCA7D, HEAD_SET_DITHER_CONTROL, ENABLE, asyh->dither.enable) | 102 NVVAL(NVCA7D, HEAD_SET_DITHER_CONTROL, BITS, asyh->dither.bits) | 103 NVDEF(NVCA7D, HEAD_SET_DITHER_CONTROL, OFFSET_ENABLE, DISABLE) | 104 NVVAL(NVCA7D, HEAD_SET_DITHER_CONTROL, MODE, asyh->dither.mode) | 105 NVVAL(NVCA7D, HEAD_SET_DITHER_CONTROL, PHASE, 0)); 106 107 return 0; 108 } 109 110 static int 111 headca7d_curs_clr(struct nv50_head *head) 112 { 113 struct nvif_push *push = &head->disp->core->chan.push; 114 const int i = head->base.index; 115 int ret; 116 117 ret = PUSH_WAIT(push, 4); 118 if (ret) 119 return ret; 120 121 PUSH_MTHD(push, NVCA7D, HEAD_SET_CONTROL_CURSOR(i), 122 NVDEF(NVCA7D, HEAD_SET_CONTROL_CURSOR, ENABLE, DISABLE) | 123 NVDEF(NVCA7D, HEAD_SET_CONTROL_CURSOR, FORMAT, A8R8G8B8)); 124 125 PUSH_MTHD(push, NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CURSOR(i, 0), 126 NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CURSOR, ENABLE, DISABLE)); 127 128 return 0; 129 } 130 131 static int 132 headca7d_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh) 133 { 134 struct nvif_push *push = &head->disp->core->chan.push; 135 const u32 curs_hi = upper_32_bits(asyh->curs.offset); 136 const u32 curs_lo = lower_32_bits(asyh->curs.offset); 137 const int i = head->base.index; 138 int ret; 139 140 ret = PUSH_WAIT(push, 7); 141 if (ret) 142 return ret; 143 144 PUSH_MTHD(push, NVCA7D, HEAD_SET_SURFACE_ADDRESS_HI_CURSOR(i, 0), curs_hi); 145 146 PUSH_MTHD(push, NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CURSOR(i, 0), 147 NVVAL(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CURSOR, ADDRESS_LO, curs_lo >> 4) | 148 NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CURSOR, TARGET, PHYSICAL_NVM) | 149 NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CURSOR, ENABLE, ENABLE)); 150 151 PUSH_MTHD(push, NVCA7D, HEAD_SET_CONTROL_CURSOR(i), 152 NVDEF(NVCA7D, HEAD_SET_CONTROL_CURSOR, ENABLE, ENABLE) | 153 NVVAL(NVCA7D, HEAD_SET_CONTROL_CURSOR, FORMAT, asyh->curs.format) | 154 NVVAL(NVCA7D, HEAD_SET_CONTROL_CURSOR, SIZE, asyh->curs.layout) | 155 NVVAL(NVCA7D, HEAD_SET_CONTROL_CURSOR, HOT_SPOT_X, 0) | 156 NVVAL(NVCA7D, HEAD_SET_CONTROL_CURSOR, HOT_SPOT_Y, 0), 157 158 HEAD_SET_CONTROL_CURSOR_COMPOSITION(i), 159 NVVAL(NVCA7D, HEAD_SET_CONTROL_CURSOR_COMPOSITION, K1, 0xff) | 160 NVDEF(NVCA7D, HEAD_SET_CONTROL_CURSOR_COMPOSITION, CURSOR_COLOR_FACTOR_SELECT, 161 K1) | 162 NVDEF(NVCA7D, HEAD_SET_CONTROL_CURSOR_COMPOSITION, VIEWPORT_COLOR_FACTOR_SELECT, 163 NEG_K1_TIMES_SRC) | 164 NVDEF(NVCA7D, HEAD_SET_CONTROL_CURSOR_COMPOSITION, MODE, BLEND)); 165 166 return 0; 167 } 168 169 static int 170 headca7d_olut_clr(struct nv50_head *head) 171 { 172 struct nvif_push *push = &head->disp->core->chan.push; 173 const int i = head->base.index; 174 int ret; 175 176 ret = PUSH_WAIT(push, 2); 177 if (ret) 178 return ret; 179 180 PUSH_MTHD(push, NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_OLUT(i), 181 NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_OLUT, ENABLE, DISABLE)); 182 183 return 0; 184 } 185 186 static int 187 headca7d_olut_set(struct nv50_head *head, struct nv50_head_atom *asyh) 188 { 189 struct nvif_push *push = &head->disp->core->chan.push; 190 const u32 olut_hi = upper_32_bits(asyh->olut.offset); 191 const u32 olut_lo = lower_32_bits(asyh->olut.offset); 192 const int i = head->base.index; 193 int ret; 194 195 ret = PUSH_WAIT(push, 6); 196 if (ret) 197 return ret; 198 199 PUSH_MTHD(push, NVCA7D, HEAD_SET_SURFACE_ADDRESS_HI_OLUT(i), olut_hi, 200 201 HEAD_SET_SURFACE_ADDRESS_LO_OLUT(i), 202 NVVAL(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_OLUT, ADDRESS_LO, olut_lo >> 4) | 203 NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_OLUT, TARGET, PHYSICAL_NVM) | 204 NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_OLUT, ENABLE, ENABLE)); 205 206 PUSH_MTHD(push, NVCA7D, HEAD_SET_OLUT_CONTROL(i), 207 NVVAL(NVCA7D, HEAD_SET_OLUT_CONTROL, INTERPOLATE, asyh->olut.output_mode) | 208 NVDEF(NVCA7D, HEAD_SET_OLUT_CONTROL, MIRROR, DISABLE) | 209 NVVAL(NVCA7D, HEAD_SET_OLUT_CONTROL, MODE, asyh->olut.mode) | 210 NVVAL(NVCA7D, HEAD_SET_OLUT_CONTROL, SIZE, asyh->olut.size), 211 212 HEAD_SET_OLUT_FP_NORM_SCALE(i), 0xffffffff); 213 214 return 0; 215 } 216 217 static int 218 headca7d_mode(struct nv50_head *head, struct nv50_head_atom *asyh) 219 { 220 struct nvif_push *push = &head->disp->core->chan.push; 221 struct nv50_head_mode *m = &asyh->mode; 222 const int i = head->base.index; 223 int ret; 224 225 ret = PUSH_WAIT(push, 11); 226 if (ret) 227 return ret; 228 229 PUSH_MTHD(push, NVCA7D, HEAD_SET_RASTER_SIZE(i), 230 NVVAL(NVCA7D, HEAD_SET_RASTER_SIZE, WIDTH, m->h.active) | 231 NVVAL(NVCA7D, HEAD_SET_RASTER_SIZE, HEIGHT, m->v.active), 232 233 HEAD_SET_RASTER_SYNC_END(i), 234 NVVAL(NVCA7D, HEAD_SET_RASTER_SYNC_END, X, m->h.synce) | 235 NVVAL(NVCA7D, HEAD_SET_RASTER_SYNC_END, Y, m->v.synce), 236 237 HEAD_SET_RASTER_BLANK_END(i), 238 NVVAL(NVCA7D, HEAD_SET_RASTER_BLANK_END, X, m->h.blanke) | 239 NVVAL(NVCA7D, HEAD_SET_RASTER_BLANK_END, Y, m->v.blanke), 240 241 HEAD_SET_RASTER_BLANK_START(i), 242 NVVAL(NVCA7D, HEAD_SET_RASTER_BLANK_START, X, m->h.blanks) | 243 NVVAL(NVCA7D, HEAD_SET_RASTER_BLANK_START, Y, m->v.blanks)); 244 245 PUSH_MTHD(push, NVCA7D, HEAD_SET_CONTROL(i), 246 NVDEF(NVCA7D, HEAD_SET_CONTROL, STRUCTURE, PROGRESSIVE)); 247 248 PUSH_MTHD(push, NVCA7D, HEAD_SET_PIXEL_CLOCK_FREQUENCY(i), 249 NVVAL(NVCA7D, HEAD_SET_PIXEL_CLOCK_FREQUENCY, HERTZ, m->clock * 1000)); 250 251 PUSH_MTHD(push, NVCA7D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(i), 252 NVVAL(NVCA7D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX, HERTZ, m->clock * 1000)); 253 254 return 0; 255 } 256 257 static int 258 headca7d_view(struct nv50_head *head, struct nv50_head_atom *asyh) 259 { 260 struct nvif_push *push = &head->disp->core->chan.push; 261 const int i = head->base.index; 262 int ret; 263 264 ret = PUSH_WAIT(push, 4); 265 if (ret) 266 return ret; 267 268 PUSH_MTHD(push, NVCA7D, HEAD_SET_VIEWPORT_SIZE_IN(i), 269 NVVAL(NVCA7D, HEAD_SET_VIEWPORT_SIZE_IN, WIDTH, asyh->view.iW) | 270 NVVAL(NVCA7D, HEAD_SET_VIEWPORT_SIZE_IN, HEIGHT, asyh->view.iH)); 271 272 PUSH_MTHD(push, NVCA7D, HEAD_SET_VIEWPORT_SIZE_OUT(i), 273 NVVAL(NVCA7D, HEAD_SET_VIEWPORT_SIZE_OUT, WIDTH, asyh->view.oW) | 274 NVVAL(NVCA7D, HEAD_SET_VIEWPORT_SIZE_OUT, HEIGHT, asyh->view.oH)); 275 return 0; 276 } 277 278 const struct nv50_head_func 279 headca7d = { 280 .view = headca7d_view, 281 .mode = headca7d_mode, 282 .olut = headc57d_olut, 283 .ilut_check = head907d_ilut_check, 284 .olut_identity = true, 285 .olut_size = 1024, 286 .olut_set = headca7d_olut_set, 287 .olut_clr = headca7d_olut_clr, 288 .curs_layout = head917d_curs_layout, 289 .curs_format = headc37d_curs_format, 290 .curs_set = headca7d_curs_set, 291 .curs_clr = headca7d_curs_clr, 292 .dither = headca7d_dither, 293 .procamp = headca7d_procamp, 294 .or = headca7d_or, 295 .static_wndw_map = headc37d_static_wndw_map, 296 .display_id = headca7d_display_id, 297 }; 298