1 /* 2 * Copyright 2011 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "disp.h" 25 #include "atom.h" 26 #include "core.h" 27 #include "head.h" 28 #include "wndw.h" 29 30 #include <linux/dma-mapping.h> 31 #include <linux/hdmi.h> 32 33 #include <drm/drmP.h> 34 #include <drm/drm_atomic_helper.h> 35 #include <drm/drm_crtc_helper.h> 36 #include <drm/drm_dp_helper.h> 37 #include <drm/drm_fb_helper.h> 38 #include <drm/drm_plane_helper.h> 39 #include <drm/drm_edid.h> 40 41 #include <nvif/class.h> 42 #include <nvif/cl0002.h> 43 #include <nvif/cl5070.h> 44 #include <nvif/cl507d.h> 45 #include <nvif/event.h> 46 47 #include "nouveau_drv.h" 48 #include "nouveau_dma.h" 49 #include "nouveau_gem.h" 50 #include "nouveau_connector.h" 51 #include "nouveau_encoder.h" 52 #include "nouveau_fence.h" 53 #include "nouveau_fbcon.h" 54 55 /****************************************************************************** 56 * Atomic state 57 *****************************************************************************/ 58 59 struct nv50_outp_atom { 60 struct list_head head; 61 62 struct drm_encoder *encoder; 63 bool flush_disable; 64 65 union { 66 struct { 67 bool ctrl:1; 68 }; 69 u8 mask; 70 } clr; 71 72 union { 73 struct { 74 bool ctrl:1; 75 }; 76 u8 mask; 77 } set; 78 }; 79 80 /****************************************************************************** 81 * EVO channel 82 *****************************************************************************/ 83 84 static int 85 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp, 86 const s32 *oclass, u8 head, void *data, u32 size, 87 struct nv50_chan *chan) 88 { 89 struct nvif_sclass *sclass; 90 int ret, i, n; 91 92 chan->device = device; 93 94 ret = n = nvif_object_sclass_get(disp, &sclass); 95 if (ret < 0) 96 return ret; 97 98 while (oclass[0]) { 99 for (i = 0; i < n; i++) { 100 if (sclass[i].oclass == oclass[0]) { 101 ret = nvif_object_init(disp, 0, oclass[0], 102 data, size, &chan->user); 103 if (ret == 0) 104 nvif_object_map(&chan->user, NULL, 0); 105 nvif_object_sclass_put(&sclass); 106 return ret; 107 } 108 } 109 oclass++; 110 } 111 112 nvif_object_sclass_put(&sclass); 113 return -ENOSYS; 114 } 115 116 static void 117 nv50_chan_destroy(struct nv50_chan *chan) 118 { 119 nvif_object_fini(&chan->user); 120 } 121 122 /****************************************************************************** 123 * DMA EVO channel 124 *****************************************************************************/ 125 126 void 127 nv50_dmac_destroy(struct nv50_dmac *dmac) 128 { 129 nvif_object_fini(&dmac->vram); 130 nvif_object_fini(&dmac->sync); 131 132 nv50_chan_destroy(&dmac->base); 133 134 nvif_mem_fini(&dmac->push); 135 } 136 137 int 138 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp, 139 const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf, 140 struct nv50_dmac *dmac) 141 { 142 struct nouveau_cli *cli = (void *)device->object.client; 143 struct nv50_disp_core_channel_dma_v0 *args = data; 144 int ret; 145 146 mutex_init(&dmac->lock); 147 148 ret = nvif_mem_init_map(&cli->mmu, NVIF_MEM_COHERENT, 0x1000, 149 &dmac->push); 150 if (ret) 151 return ret; 152 153 dmac->ptr = dmac->push.object.map.ptr; 154 155 args->pushbuf = nvif_handle(&dmac->push.object); 156 157 ret = nv50_chan_create(device, disp, oclass, head, data, size, 158 &dmac->base); 159 if (ret) 160 return ret; 161 162 ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY, 163 &(struct nv_dma_v0) { 164 .target = NV_DMA_V0_TARGET_VRAM, 165 .access = NV_DMA_V0_ACCESS_RDWR, 166 .start = syncbuf + 0x0000, 167 .limit = syncbuf + 0x0fff, 168 }, sizeof(struct nv_dma_v0), 169 &dmac->sync); 170 if (ret) 171 return ret; 172 173 ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY, 174 &(struct nv_dma_v0) { 175 .target = NV_DMA_V0_TARGET_VRAM, 176 .access = NV_DMA_V0_ACCESS_RDWR, 177 .start = 0, 178 .limit = device->info.ram_user - 1, 179 }, sizeof(struct nv_dma_v0), 180 &dmac->vram); 181 if (ret) 182 return ret; 183 184 return ret; 185 } 186 187 /****************************************************************************** 188 * EVO channel helpers 189 *****************************************************************************/ 190 u32 * 191 evo_wait(struct nv50_dmac *evoc, int nr) 192 { 193 struct nv50_dmac *dmac = evoc; 194 struct nvif_device *device = dmac->base.device; 195 u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4; 196 197 mutex_lock(&dmac->lock); 198 if (put + nr >= (PAGE_SIZE / 4) - 8) { 199 dmac->ptr[put] = 0x20000000; 200 201 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000); 202 if (nvif_msec(device, 2000, 203 if (!nvif_rd32(&dmac->base.user, 0x0004)) 204 break; 205 ) < 0) { 206 mutex_unlock(&dmac->lock); 207 pr_err("nouveau: evo channel stalled\n"); 208 return NULL; 209 } 210 211 put = 0; 212 } 213 214 return dmac->ptr + put; 215 } 216 217 void 218 evo_kick(u32 *push, struct nv50_dmac *evoc) 219 { 220 struct nv50_dmac *dmac = evoc; 221 nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2); 222 mutex_unlock(&dmac->lock); 223 } 224 225 /****************************************************************************** 226 * Output path helpers 227 *****************************************************************************/ 228 static void 229 nv50_outp_release(struct nouveau_encoder *nv_encoder) 230 { 231 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev); 232 struct { 233 struct nv50_disp_mthd_v1 base; 234 } args = { 235 .base.version = 1, 236 .base.method = NV50_DISP_MTHD_V1_RELEASE, 237 .base.hasht = nv_encoder->dcb->hasht, 238 .base.hashm = nv_encoder->dcb->hashm, 239 }; 240 241 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 242 nv_encoder->or = -1; 243 nv_encoder->link = 0; 244 } 245 246 static int 247 nv50_outp_acquire(struct nouveau_encoder *nv_encoder) 248 { 249 struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); 250 struct nv50_disp *disp = nv50_disp(drm->dev); 251 struct { 252 struct nv50_disp_mthd_v1 base; 253 struct nv50_disp_acquire_v0 info; 254 } args = { 255 .base.version = 1, 256 .base.method = NV50_DISP_MTHD_V1_ACQUIRE, 257 .base.hasht = nv_encoder->dcb->hasht, 258 .base.hashm = nv_encoder->dcb->hashm, 259 }; 260 int ret; 261 262 ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 263 if (ret) { 264 NV_ERROR(drm, "error acquiring output path: %d\n", ret); 265 return ret; 266 } 267 268 nv_encoder->or = args.info.or; 269 nv_encoder->link = args.info.link; 270 return 0; 271 } 272 273 static int 274 nv50_outp_atomic_check_view(struct drm_encoder *encoder, 275 struct drm_crtc_state *crtc_state, 276 struct drm_connector_state *conn_state, 277 struct drm_display_mode *native_mode) 278 { 279 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 280 struct drm_display_mode *mode = &crtc_state->mode; 281 struct drm_connector *connector = conn_state->connector; 282 struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state); 283 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 284 285 NV_ATOMIC(drm, "%s atomic_check\n", encoder->name); 286 asyc->scaler.full = false; 287 if (!native_mode) 288 return 0; 289 290 if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) { 291 switch (connector->connector_type) { 292 case DRM_MODE_CONNECTOR_LVDS: 293 case DRM_MODE_CONNECTOR_eDP: 294 /* Force use of scaler for non-EDID modes. */ 295 if (adjusted_mode->type & DRM_MODE_TYPE_DRIVER) 296 break; 297 mode = native_mode; 298 asyc->scaler.full = true; 299 break; 300 default: 301 break; 302 } 303 } else { 304 mode = native_mode; 305 } 306 307 if (!drm_mode_equal(adjusted_mode, mode)) { 308 drm_mode_copy(adjusted_mode, mode); 309 crtc_state->mode_changed = true; 310 } 311 312 return 0; 313 } 314 315 static int 316 nv50_outp_atomic_check(struct drm_encoder *encoder, 317 struct drm_crtc_state *crtc_state, 318 struct drm_connector_state *conn_state) 319 { 320 struct nouveau_connector *nv_connector = 321 nouveau_connector(conn_state->connector); 322 return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state, 323 nv_connector->native_mode); 324 } 325 326 /****************************************************************************** 327 * DAC 328 *****************************************************************************/ 329 static void 330 nv50_dac_disable(struct drm_encoder *encoder) 331 { 332 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 333 struct nv50_core *core = nv50_disp(encoder->dev)->core; 334 if (nv_encoder->crtc) 335 core->func->dac->ctrl(core, nv_encoder->or, 0x00000000, NULL); 336 nv_encoder->crtc = NULL; 337 nv50_outp_release(nv_encoder); 338 } 339 340 static void 341 nv50_dac_enable(struct drm_encoder *encoder) 342 { 343 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 344 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 345 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state); 346 struct nv50_core *core = nv50_disp(encoder->dev)->core; 347 348 nv50_outp_acquire(nv_encoder); 349 350 core->func->dac->ctrl(core, nv_encoder->or, 1 << nv_crtc->index, asyh); 351 asyh->or.depth = 0; 352 353 nv_encoder->crtc = encoder->crtc; 354 } 355 356 static enum drm_connector_status 357 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) 358 { 359 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 360 struct nv50_disp *disp = nv50_disp(encoder->dev); 361 struct { 362 struct nv50_disp_mthd_v1 base; 363 struct nv50_disp_dac_load_v0 load; 364 } args = { 365 .base.version = 1, 366 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD, 367 .base.hasht = nv_encoder->dcb->hasht, 368 .base.hashm = nv_encoder->dcb->hashm, 369 }; 370 int ret; 371 372 args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval; 373 if (args.load.data == 0) 374 args.load.data = 340; 375 376 ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 377 if (ret || !args.load.load) 378 return connector_status_disconnected; 379 380 return connector_status_connected; 381 } 382 383 static const struct drm_encoder_helper_funcs 384 nv50_dac_help = { 385 .atomic_check = nv50_outp_atomic_check, 386 .enable = nv50_dac_enable, 387 .disable = nv50_dac_disable, 388 .detect = nv50_dac_detect 389 }; 390 391 static void 392 nv50_dac_destroy(struct drm_encoder *encoder) 393 { 394 drm_encoder_cleanup(encoder); 395 kfree(encoder); 396 } 397 398 static const struct drm_encoder_funcs 399 nv50_dac_func = { 400 .destroy = nv50_dac_destroy, 401 }; 402 403 static int 404 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe) 405 { 406 struct nouveau_drm *drm = nouveau_drm(connector->dev); 407 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 408 struct nvkm_i2c_bus *bus; 409 struct nouveau_encoder *nv_encoder; 410 struct drm_encoder *encoder; 411 int type = DRM_MODE_ENCODER_DAC; 412 413 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 414 if (!nv_encoder) 415 return -ENOMEM; 416 nv_encoder->dcb = dcbe; 417 418 bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index); 419 if (bus) 420 nv_encoder->i2c = &bus->i2c; 421 422 encoder = to_drm_encoder(nv_encoder); 423 encoder->possible_crtcs = dcbe->heads; 424 encoder->possible_clones = 0; 425 drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type, 426 "dac-%04x-%04x", dcbe->hasht, dcbe->hashm); 427 drm_encoder_helper_add(encoder, &nv50_dac_help); 428 429 drm_mode_connector_attach_encoder(connector, encoder); 430 return 0; 431 } 432 433 /****************************************************************************** 434 * Audio 435 *****************************************************************************/ 436 static void 437 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) 438 { 439 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 440 struct nv50_disp *disp = nv50_disp(encoder->dev); 441 struct { 442 struct nv50_disp_mthd_v1 base; 443 struct nv50_disp_sor_hda_eld_v0 eld; 444 } args = { 445 .base.version = 1, 446 .base.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD, 447 .base.hasht = nv_encoder->dcb->hasht, 448 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 449 (0x0100 << nv_crtc->index), 450 }; 451 452 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 453 } 454 455 static void 456 nv50_audio_enable(struct drm_encoder *encoder, struct drm_display_mode *mode) 457 { 458 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 459 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 460 struct nouveau_connector *nv_connector; 461 struct nv50_disp *disp = nv50_disp(encoder->dev); 462 struct __packed { 463 struct { 464 struct nv50_disp_mthd_v1 mthd; 465 struct nv50_disp_sor_hda_eld_v0 eld; 466 } base; 467 u8 data[sizeof(nv_connector->base.eld)]; 468 } args = { 469 .base.mthd.version = 1, 470 .base.mthd.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD, 471 .base.mthd.hasht = nv_encoder->dcb->hasht, 472 .base.mthd.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 473 (0x0100 << nv_crtc->index), 474 }; 475 476 nv_connector = nouveau_encoder_connector_get(nv_encoder); 477 if (!drm_detect_monitor_audio(nv_connector->edid)) 478 return; 479 480 memcpy(args.data, nv_connector->base.eld, sizeof(args.data)); 481 482 nvif_mthd(&disp->disp->object, 0, &args, 483 sizeof(args.base) + drm_eld_size(args.data)); 484 } 485 486 /****************************************************************************** 487 * HDMI 488 *****************************************************************************/ 489 static void 490 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) 491 { 492 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 493 struct nv50_disp *disp = nv50_disp(encoder->dev); 494 struct { 495 struct nv50_disp_mthd_v1 base; 496 struct nv50_disp_sor_hdmi_pwr_v0 pwr; 497 } args = { 498 .base.version = 1, 499 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR, 500 .base.hasht = nv_encoder->dcb->hasht, 501 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 502 (0x0100 << nv_crtc->index), 503 }; 504 505 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 506 } 507 508 static void 509 nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_display_mode *mode) 510 { 511 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 512 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 513 struct nv50_disp *disp = nv50_disp(encoder->dev); 514 struct { 515 struct nv50_disp_mthd_v1 base; 516 struct nv50_disp_sor_hdmi_pwr_v0 pwr; 517 u8 infoframes[2 * 17]; /* two frames, up to 17 bytes each */ 518 } args = { 519 .base.version = 1, 520 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR, 521 .base.hasht = nv_encoder->dcb->hasht, 522 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 523 (0x0100 << nv_crtc->index), 524 .pwr.state = 1, 525 .pwr.rekey = 56, /* binary driver, and tegra, constant */ 526 }; 527 struct nouveau_connector *nv_connector; 528 u32 max_ac_packet; 529 union hdmi_infoframe avi_frame; 530 union hdmi_infoframe vendor_frame; 531 int ret; 532 int size; 533 534 nv_connector = nouveau_encoder_connector_get(nv_encoder); 535 if (!drm_detect_hdmi_monitor(nv_connector->edid)) 536 return; 537 538 ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi, mode, 539 false); 540 if (!ret) { 541 /* We have an AVI InfoFrame, populate it to the display */ 542 args.pwr.avi_infoframe_length 543 = hdmi_infoframe_pack(&avi_frame, args.infoframes, 17); 544 } 545 546 ret = drm_hdmi_vendor_infoframe_from_display_mode(&vendor_frame.vendor.hdmi, 547 &nv_connector->base, mode); 548 if (!ret) { 549 /* We have a Vendor InfoFrame, populate it to the display */ 550 args.pwr.vendor_infoframe_length 551 = hdmi_infoframe_pack(&vendor_frame, 552 args.infoframes 553 + args.pwr.avi_infoframe_length, 554 17); 555 } 556 557 max_ac_packet = mode->htotal - mode->hdisplay; 558 max_ac_packet -= args.pwr.rekey; 559 max_ac_packet -= 18; /* constant from tegra */ 560 args.pwr.max_ac_packet = max_ac_packet / 32; 561 562 size = sizeof(args.base) 563 + sizeof(args.pwr) 564 + args.pwr.avi_infoframe_length 565 + args.pwr.vendor_infoframe_length; 566 nvif_mthd(&disp->disp->object, 0, &args, size); 567 nv50_audio_enable(encoder, mode); 568 } 569 570 /****************************************************************************** 571 * MST 572 *****************************************************************************/ 573 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr) 574 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector) 575 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder) 576 577 struct nv50_mstm { 578 struct nouveau_encoder *outp; 579 580 struct drm_dp_mst_topology_mgr mgr; 581 struct nv50_msto *msto[4]; 582 583 bool modified; 584 bool disabled; 585 int links; 586 }; 587 588 struct nv50_mstc { 589 struct nv50_mstm *mstm; 590 struct drm_dp_mst_port *port; 591 struct drm_connector connector; 592 593 struct drm_display_mode *native; 594 struct edid *edid; 595 596 int pbn; 597 }; 598 599 struct nv50_msto { 600 struct drm_encoder encoder; 601 602 struct nv50_head *head; 603 struct nv50_mstc *mstc; 604 bool disabled; 605 }; 606 607 static struct drm_dp_payload * 608 nv50_msto_payload(struct nv50_msto *msto) 609 { 610 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); 611 struct nv50_mstc *mstc = msto->mstc; 612 struct nv50_mstm *mstm = mstc->mstm; 613 int vcpi = mstc->port->vcpi.vcpi, i; 614 615 NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi); 616 for (i = 0; i < mstm->mgr.max_payloads; i++) { 617 struct drm_dp_payload *payload = &mstm->mgr.payloads[i]; 618 NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n", 619 mstm->outp->base.base.name, i, payload->vcpi, 620 payload->start_slot, payload->num_slots); 621 } 622 623 for (i = 0; i < mstm->mgr.max_payloads; i++) { 624 struct drm_dp_payload *payload = &mstm->mgr.payloads[i]; 625 if (payload->vcpi == vcpi) 626 return payload; 627 } 628 629 return NULL; 630 } 631 632 static void 633 nv50_msto_cleanup(struct nv50_msto *msto) 634 { 635 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); 636 struct nv50_mstc *mstc = msto->mstc; 637 struct nv50_mstm *mstm = mstc->mstm; 638 639 NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name); 640 if (mstc->port && mstc->port->vcpi.vcpi > 0 && !nv50_msto_payload(msto)) 641 drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port); 642 if (msto->disabled) { 643 msto->mstc = NULL; 644 msto->head = NULL; 645 msto->disabled = false; 646 } 647 } 648 649 static void 650 nv50_msto_prepare(struct nv50_msto *msto) 651 { 652 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); 653 struct nv50_mstc *mstc = msto->mstc; 654 struct nv50_mstm *mstm = mstc->mstm; 655 struct { 656 struct nv50_disp_mthd_v1 base; 657 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi; 658 } args = { 659 .base.version = 1, 660 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI, 661 .base.hasht = mstm->outp->dcb->hasht, 662 .base.hashm = (0xf0ff & mstm->outp->dcb->hashm) | 663 (0x0100 << msto->head->base.index), 664 }; 665 666 NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name); 667 if (mstc->port && mstc->port->vcpi.vcpi > 0) { 668 struct drm_dp_payload *payload = nv50_msto_payload(msto); 669 if (payload) { 670 args.vcpi.start_slot = payload->start_slot; 671 args.vcpi.num_slots = payload->num_slots; 672 args.vcpi.pbn = mstc->port->vcpi.pbn; 673 args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn; 674 } 675 } 676 677 NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n", 678 msto->encoder.name, msto->head->base.base.name, 679 args.vcpi.start_slot, args.vcpi.num_slots, 680 args.vcpi.pbn, args.vcpi.aligned_pbn); 681 nvif_mthd(&drm->display->disp.object, 0, &args, sizeof(args)); 682 } 683 684 static int 685 nv50_msto_atomic_check(struct drm_encoder *encoder, 686 struct drm_crtc_state *crtc_state, 687 struct drm_connector_state *conn_state) 688 { 689 struct nv50_mstc *mstc = nv50_mstc(conn_state->connector); 690 struct nv50_mstm *mstm = mstc->mstm; 691 int bpp = conn_state->connector->display_info.bpc * 3; 692 int slots; 693 694 mstc->pbn = drm_dp_calc_pbn_mode(crtc_state->adjusted_mode.clock, bpp); 695 696 slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn); 697 if (slots < 0) 698 return slots; 699 700 return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state, 701 mstc->native); 702 } 703 704 static void 705 nv50_msto_enable(struct drm_encoder *encoder) 706 { 707 struct nv50_head *head = nv50_head(encoder->crtc); 708 struct nv50_msto *msto = nv50_msto(encoder); 709 struct nv50_mstc *mstc = NULL; 710 struct nv50_mstm *mstm = NULL; 711 struct drm_connector *connector; 712 struct drm_connector_list_iter conn_iter; 713 u8 proto, depth; 714 int slots; 715 bool r; 716 717 drm_connector_list_iter_begin(encoder->dev, &conn_iter); 718 drm_for_each_connector_iter(connector, &conn_iter) { 719 if (connector->state->best_encoder == &msto->encoder) { 720 mstc = nv50_mstc(connector); 721 mstm = mstc->mstm; 722 break; 723 } 724 } 725 drm_connector_list_iter_end(&conn_iter); 726 727 if (WARN_ON(!mstc)) 728 return; 729 730 slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn); 731 r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, mstc->pbn, slots); 732 WARN_ON(!r); 733 734 if (!mstm->links++) 735 nv50_outp_acquire(mstm->outp); 736 737 if (mstm->outp->link & 1) 738 proto = 0x8; 739 else 740 proto = 0x9; 741 742 switch (mstc->connector.display_info.bpc) { 743 case 6: depth = 0x2; break; 744 case 8: depth = 0x5; break; 745 case 10: 746 default: depth = 0x6; break; 747 } 748 749 mstm->outp->update(mstm->outp, head->base.index, 750 nv50_head_atom(head->base.base.state), proto, depth); 751 752 msto->head = head; 753 msto->mstc = mstc; 754 mstm->modified = true; 755 } 756 757 static void 758 nv50_msto_disable(struct drm_encoder *encoder) 759 { 760 struct nv50_msto *msto = nv50_msto(encoder); 761 struct nv50_mstc *mstc = msto->mstc; 762 struct nv50_mstm *mstm = mstc->mstm; 763 764 if (mstc->port) 765 drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port); 766 767 mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0); 768 mstm->modified = true; 769 if (!--mstm->links) 770 mstm->disabled = true; 771 msto->disabled = true; 772 } 773 774 static const struct drm_encoder_helper_funcs 775 nv50_msto_help = { 776 .disable = nv50_msto_disable, 777 .enable = nv50_msto_enable, 778 .atomic_check = nv50_msto_atomic_check, 779 }; 780 781 static void 782 nv50_msto_destroy(struct drm_encoder *encoder) 783 { 784 struct nv50_msto *msto = nv50_msto(encoder); 785 drm_encoder_cleanup(&msto->encoder); 786 kfree(msto); 787 } 788 789 static const struct drm_encoder_funcs 790 nv50_msto = { 791 .destroy = nv50_msto_destroy, 792 }; 793 794 static int 795 nv50_msto_new(struct drm_device *dev, u32 heads, const char *name, int id, 796 struct nv50_msto **pmsto) 797 { 798 struct nv50_msto *msto; 799 int ret; 800 801 if (!(msto = *pmsto = kzalloc(sizeof(*msto), GFP_KERNEL))) 802 return -ENOMEM; 803 804 ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto, 805 DRM_MODE_ENCODER_DPMST, "%s-mst-%d", name, id); 806 if (ret) { 807 kfree(*pmsto); 808 *pmsto = NULL; 809 return ret; 810 } 811 812 drm_encoder_helper_add(&msto->encoder, &nv50_msto_help); 813 msto->encoder.possible_crtcs = heads; 814 return 0; 815 } 816 817 static struct drm_encoder * 818 nv50_mstc_atomic_best_encoder(struct drm_connector *connector, 819 struct drm_connector_state *connector_state) 820 { 821 struct nv50_head *head = nv50_head(connector_state->crtc); 822 struct nv50_mstc *mstc = nv50_mstc(connector); 823 if (mstc->port) { 824 struct nv50_mstm *mstm = mstc->mstm; 825 return &mstm->msto[head->base.index]->encoder; 826 } 827 return NULL; 828 } 829 830 static struct drm_encoder * 831 nv50_mstc_best_encoder(struct drm_connector *connector) 832 { 833 struct nv50_mstc *mstc = nv50_mstc(connector); 834 if (mstc->port) { 835 struct nv50_mstm *mstm = mstc->mstm; 836 return &mstm->msto[0]->encoder; 837 } 838 return NULL; 839 } 840 841 static enum drm_mode_status 842 nv50_mstc_mode_valid(struct drm_connector *connector, 843 struct drm_display_mode *mode) 844 { 845 return MODE_OK; 846 } 847 848 static int 849 nv50_mstc_get_modes(struct drm_connector *connector) 850 { 851 struct nv50_mstc *mstc = nv50_mstc(connector); 852 int ret = 0; 853 854 mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port); 855 drm_mode_connector_update_edid_property(&mstc->connector, mstc->edid); 856 if (mstc->edid) 857 ret = drm_add_edid_modes(&mstc->connector, mstc->edid); 858 859 if (!mstc->connector.display_info.bpc) 860 mstc->connector.display_info.bpc = 8; 861 862 if (mstc->native) 863 drm_mode_destroy(mstc->connector.dev, mstc->native); 864 mstc->native = nouveau_conn_native_mode(&mstc->connector); 865 return ret; 866 } 867 868 static const struct drm_connector_helper_funcs 869 nv50_mstc_help = { 870 .get_modes = nv50_mstc_get_modes, 871 .mode_valid = nv50_mstc_mode_valid, 872 .best_encoder = nv50_mstc_best_encoder, 873 .atomic_best_encoder = nv50_mstc_atomic_best_encoder, 874 }; 875 876 static enum drm_connector_status 877 nv50_mstc_detect(struct drm_connector *connector, bool force) 878 { 879 struct nv50_mstc *mstc = nv50_mstc(connector); 880 if (!mstc->port) 881 return connector_status_disconnected; 882 return drm_dp_mst_detect_port(connector, mstc->port->mgr, mstc->port); 883 } 884 885 static void 886 nv50_mstc_destroy(struct drm_connector *connector) 887 { 888 struct nv50_mstc *mstc = nv50_mstc(connector); 889 drm_connector_cleanup(&mstc->connector); 890 kfree(mstc); 891 } 892 893 static const struct drm_connector_funcs 894 nv50_mstc = { 895 .reset = nouveau_conn_reset, 896 .detect = nv50_mstc_detect, 897 .fill_modes = drm_helper_probe_single_connector_modes, 898 .destroy = nv50_mstc_destroy, 899 .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state, 900 .atomic_destroy_state = nouveau_conn_atomic_destroy_state, 901 .atomic_set_property = nouveau_conn_atomic_set_property, 902 .atomic_get_property = nouveau_conn_atomic_get_property, 903 }; 904 905 static int 906 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port, 907 const char *path, struct nv50_mstc **pmstc) 908 { 909 struct drm_device *dev = mstm->outp->base.base.dev; 910 struct nv50_mstc *mstc; 911 int ret, i; 912 913 if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL))) 914 return -ENOMEM; 915 mstc->mstm = mstm; 916 mstc->port = port; 917 918 ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc, 919 DRM_MODE_CONNECTOR_DisplayPort); 920 if (ret) { 921 kfree(*pmstc); 922 *pmstc = NULL; 923 return ret; 924 } 925 926 drm_connector_helper_add(&mstc->connector, &nv50_mstc_help); 927 928 mstc->connector.funcs->reset(&mstc->connector); 929 nouveau_conn_attach_properties(&mstc->connector); 930 931 for (i = 0; i < ARRAY_SIZE(mstm->msto) && mstm->msto[i]; i++) 932 drm_mode_connector_attach_encoder(&mstc->connector, &mstm->msto[i]->encoder); 933 934 drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0); 935 drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0); 936 drm_mode_connector_set_path_property(&mstc->connector, path); 937 return 0; 938 } 939 940 static void 941 nv50_mstm_cleanup(struct nv50_mstm *mstm) 942 { 943 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev); 944 struct drm_encoder *encoder; 945 int ret; 946 947 NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name); 948 ret = drm_dp_check_act_status(&mstm->mgr); 949 950 ret = drm_dp_update_payload_part2(&mstm->mgr); 951 952 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { 953 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 954 struct nv50_msto *msto = nv50_msto(encoder); 955 struct nv50_mstc *mstc = msto->mstc; 956 if (mstc && mstc->mstm == mstm) 957 nv50_msto_cleanup(msto); 958 } 959 } 960 961 mstm->modified = false; 962 } 963 964 static void 965 nv50_mstm_prepare(struct nv50_mstm *mstm) 966 { 967 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev); 968 struct drm_encoder *encoder; 969 int ret; 970 971 NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name); 972 ret = drm_dp_update_payload_part1(&mstm->mgr); 973 974 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { 975 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 976 struct nv50_msto *msto = nv50_msto(encoder); 977 struct nv50_mstc *mstc = msto->mstc; 978 if (mstc && mstc->mstm == mstm) 979 nv50_msto_prepare(msto); 980 } 981 } 982 983 if (mstm->disabled) { 984 if (!mstm->links) 985 nv50_outp_release(mstm->outp); 986 mstm->disabled = false; 987 } 988 } 989 990 static void 991 nv50_mstm_hotplug(struct drm_dp_mst_topology_mgr *mgr) 992 { 993 struct nv50_mstm *mstm = nv50_mstm(mgr); 994 drm_kms_helper_hotplug_event(mstm->outp->base.base.dev); 995 } 996 997 static void 998 nv50_mstm_destroy_connector(struct drm_dp_mst_topology_mgr *mgr, 999 struct drm_connector *connector) 1000 { 1001 struct nouveau_drm *drm = nouveau_drm(connector->dev); 1002 struct nv50_mstc *mstc = nv50_mstc(connector); 1003 1004 drm_connector_unregister(&mstc->connector); 1005 1006 drm_fb_helper_remove_one_connector(&drm->fbcon->helper, &mstc->connector); 1007 1008 drm_modeset_lock(&drm->dev->mode_config.connection_mutex, NULL); 1009 mstc->port = NULL; 1010 drm_modeset_unlock(&drm->dev->mode_config.connection_mutex); 1011 1012 drm_connector_unreference(&mstc->connector); 1013 } 1014 1015 static void 1016 nv50_mstm_register_connector(struct drm_connector *connector) 1017 { 1018 struct nouveau_drm *drm = nouveau_drm(connector->dev); 1019 1020 drm_fb_helper_add_one_connector(&drm->fbcon->helper, connector); 1021 1022 drm_connector_register(connector); 1023 } 1024 1025 static struct drm_connector * 1026 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr, 1027 struct drm_dp_mst_port *port, const char *path) 1028 { 1029 struct nv50_mstm *mstm = nv50_mstm(mgr); 1030 struct nv50_mstc *mstc; 1031 int ret; 1032 1033 ret = nv50_mstc_new(mstm, port, path, &mstc); 1034 if (ret) { 1035 if (mstc) 1036 mstc->connector.funcs->destroy(&mstc->connector); 1037 return NULL; 1038 } 1039 1040 return &mstc->connector; 1041 } 1042 1043 static const struct drm_dp_mst_topology_cbs 1044 nv50_mstm = { 1045 .add_connector = nv50_mstm_add_connector, 1046 .register_connector = nv50_mstm_register_connector, 1047 .destroy_connector = nv50_mstm_destroy_connector, 1048 .hotplug = nv50_mstm_hotplug, 1049 }; 1050 1051 void 1052 nv50_mstm_service(struct nv50_mstm *mstm) 1053 { 1054 struct drm_dp_aux *aux = mstm ? mstm->mgr.aux : NULL; 1055 bool handled = true; 1056 int ret; 1057 u8 esi[8] = {}; 1058 1059 if (!aux) 1060 return; 1061 1062 while (handled) { 1063 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8); 1064 if (ret != 8) { 1065 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false); 1066 return; 1067 } 1068 1069 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled); 1070 if (!handled) 1071 break; 1072 1073 drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 3); 1074 } 1075 } 1076 1077 void 1078 nv50_mstm_remove(struct nv50_mstm *mstm) 1079 { 1080 if (mstm) 1081 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false); 1082 } 1083 1084 static int 1085 nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state) 1086 { 1087 struct nouveau_encoder *outp = mstm->outp; 1088 struct { 1089 struct nv50_disp_mthd_v1 base; 1090 struct nv50_disp_sor_dp_mst_link_v0 mst; 1091 } args = { 1092 .base.version = 1, 1093 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK, 1094 .base.hasht = outp->dcb->hasht, 1095 .base.hashm = outp->dcb->hashm, 1096 .mst.state = state, 1097 }; 1098 struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev); 1099 struct nvif_object *disp = &drm->display->disp.object; 1100 int ret; 1101 1102 if (dpcd >= 0x12) { 1103 ret = drm_dp_dpcd_readb(mstm->mgr.aux, DP_MSTM_CTRL, &dpcd); 1104 if (ret < 0) 1105 return ret; 1106 1107 dpcd &= ~DP_MST_EN; 1108 if (state) 1109 dpcd |= DP_MST_EN; 1110 1111 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, dpcd); 1112 if (ret < 0) 1113 return ret; 1114 } 1115 1116 return nvif_mthd(disp, 0, &args, sizeof(args)); 1117 } 1118 1119 int 1120 nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow) 1121 { 1122 int ret, state = 0; 1123 1124 if (!mstm) 1125 return 0; 1126 1127 if (dpcd[0] >= 0x12) { 1128 ret = drm_dp_dpcd_readb(mstm->mgr.aux, DP_MSTM_CAP, &dpcd[1]); 1129 if (ret < 0) 1130 return ret; 1131 1132 if (!(dpcd[1] & DP_MST_CAP)) 1133 dpcd[0] = 0x11; 1134 else 1135 state = allow; 1136 } 1137 1138 ret = nv50_mstm_enable(mstm, dpcd[0], state); 1139 if (ret) 1140 return ret; 1141 1142 ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, state); 1143 if (ret) 1144 return nv50_mstm_enable(mstm, dpcd[0], 0); 1145 1146 return mstm->mgr.mst_state; 1147 } 1148 1149 static void 1150 nv50_mstm_fini(struct nv50_mstm *mstm) 1151 { 1152 if (mstm && mstm->mgr.mst_state) 1153 drm_dp_mst_topology_mgr_suspend(&mstm->mgr); 1154 } 1155 1156 static void 1157 nv50_mstm_init(struct nv50_mstm *mstm) 1158 { 1159 if (mstm && mstm->mgr.mst_state) 1160 drm_dp_mst_topology_mgr_resume(&mstm->mgr); 1161 } 1162 1163 static void 1164 nv50_mstm_del(struct nv50_mstm **pmstm) 1165 { 1166 struct nv50_mstm *mstm = *pmstm; 1167 if (mstm) { 1168 kfree(*pmstm); 1169 *pmstm = NULL; 1170 } 1171 } 1172 1173 static int 1174 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max, 1175 int conn_base_id, struct nv50_mstm **pmstm) 1176 { 1177 const int max_payloads = hweight8(outp->dcb->heads); 1178 struct drm_device *dev = outp->base.base.dev; 1179 struct nv50_mstm *mstm; 1180 int ret, i; 1181 u8 dpcd; 1182 1183 /* This is a workaround for some monitors not functioning 1184 * correctly in MST mode on initial module load. I think 1185 * some bad interaction with the VBIOS may be responsible. 1186 * 1187 * A good ol' off and on again seems to work here ;) 1188 */ 1189 ret = drm_dp_dpcd_readb(aux, DP_DPCD_REV, &dpcd); 1190 if (ret >= 0 && dpcd >= 0x12) 1191 drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0); 1192 1193 if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL))) 1194 return -ENOMEM; 1195 mstm->outp = outp; 1196 mstm->mgr.cbs = &nv50_mstm; 1197 1198 ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max, 1199 max_payloads, conn_base_id); 1200 if (ret) 1201 return ret; 1202 1203 for (i = 0; i < max_payloads; i++) { 1204 ret = nv50_msto_new(dev, outp->dcb->heads, outp->base.base.name, 1205 i, &mstm->msto[i]); 1206 if (ret) 1207 return ret; 1208 } 1209 1210 return 0; 1211 } 1212 1213 /****************************************************************************** 1214 * SOR 1215 *****************************************************************************/ 1216 static void 1217 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head, 1218 struct nv50_head_atom *asyh, u8 proto, u8 depth) 1219 { 1220 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev); 1221 struct nv50_core *core = disp->core; 1222 1223 if (!asyh) { 1224 nv_encoder->ctrl &= ~BIT(head); 1225 if (!(nv_encoder->ctrl & 0x0000000f)) 1226 nv_encoder->ctrl = 0; 1227 } else { 1228 nv_encoder->ctrl |= proto << 8; 1229 nv_encoder->ctrl |= BIT(head); 1230 asyh->or.depth = depth; 1231 } 1232 1233 core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh); 1234 } 1235 1236 static void 1237 nv50_sor_disable(struct drm_encoder *encoder) 1238 { 1239 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1240 struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc); 1241 1242 nv_encoder->crtc = NULL; 1243 1244 if (nv_crtc) { 1245 struct nvkm_i2c_aux *aux = nv_encoder->aux; 1246 u8 pwr; 1247 1248 if (aux) { 1249 int ret = nvkm_rdaux(aux, DP_SET_POWER, &pwr, 1); 1250 if (ret == 0) { 1251 pwr &= ~DP_SET_POWER_MASK; 1252 pwr |= DP_SET_POWER_D3; 1253 nvkm_wraux(aux, DP_SET_POWER, &pwr, 1); 1254 } 1255 } 1256 1257 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0); 1258 nv50_audio_disable(encoder, nv_crtc); 1259 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc); 1260 nv50_outp_release(nv_encoder); 1261 } 1262 } 1263 1264 static void 1265 nv50_sor_enable(struct drm_encoder *encoder) 1266 { 1267 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1268 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 1269 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state); 1270 struct drm_display_mode *mode = &asyh->state.adjusted_mode; 1271 struct { 1272 struct nv50_disp_mthd_v1 base; 1273 struct nv50_disp_sor_lvds_script_v0 lvds; 1274 } lvds = { 1275 .base.version = 1, 1276 .base.method = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT, 1277 .base.hasht = nv_encoder->dcb->hasht, 1278 .base.hashm = nv_encoder->dcb->hashm, 1279 }; 1280 struct nv50_disp *disp = nv50_disp(encoder->dev); 1281 struct drm_device *dev = encoder->dev; 1282 struct nouveau_drm *drm = nouveau_drm(dev); 1283 struct nouveau_connector *nv_connector; 1284 struct nvbios *bios = &drm->vbios; 1285 u8 proto = 0xf; 1286 u8 depth = 0x0; 1287 1288 nv_connector = nouveau_encoder_connector_get(nv_encoder); 1289 nv_encoder->crtc = encoder->crtc; 1290 nv50_outp_acquire(nv_encoder); 1291 1292 switch (nv_encoder->dcb->type) { 1293 case DCB_OUTPUT_TMDS: 1294 if (nv_encoder->link & 1) { 1295 proto = 0x1; 1296 /* Only enable dual-link if: 1297 * - Need to (i.e. rate > 165MHz) 1298 * - DCB says we can 1299 * - Not an HDMI monitor, since there's no dual-link 1300 * on HDMI. 1301 */ 1302 if (mode->clock >= 165000 && 1303 nv_encoder->dcb->duallink_possible && 1304 !drm_detect_hdmi_monitor(nv_connector->edid)) 1305 proto |= 0x4; 1306 } else { 1307 proto = 0x2; 1308 } 1309 1310 nv50_hdmi_enable(&nv_encoder->base.base, mode); 1311 break; 1312 case DCB_OUTPUT_LVDS: 1313 proto = 0x0; 1314 1315 if (bios->fp_no_ddc) { 1316 if (bios->fp.dual_link) 1317 lvds.lvds.script |= 0x0100; 1318 if (bios->fp.if_is_24bit) 1319 lvds.lvds.script |= 0x0200; 1320 } else { 1321 if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) { 1322 if (((u8 *)nv_connector->edid)[121] == 2) 1323 lvds.lvds.script |= 0x0100; 1324 } else 1325 if (mode->clock >= bios->fp.duallink_transition_clk) { 1326 lvds.lvds.script |= 0x0100; 1327 } 1328 1329 if (lvds.lvds.script & 0x0100) { 1330 if (bios->fp.strapless_is_24bit & 2) 1331 lvds.lvds.script |= 0x0200; 1332 } else { 1333 if (bios->fp.strapless_is_24bit & 1) 1334 lvds.lvds.script |= 0x0200; 1335 } 1336 1337 if (nv_connector->base.display_info.bpc == 8) 1338 lvds.lvds.script |= 0x0200; 1339 } 1340 1341 nvif_mthd(&disp->disp->object, 0, &lvds, sizeof(lvds)); 1342 break; 1343 case DCB_OUTPUT_DP: 1344 if (nv_connector->base.display_info.bpc == 6) 1345 depth = 0x2; 1346 else 1347 if (nv_connector->base.display_info.bpc == 8) 1348 depth = 0x5; 1349 else 1350 depth = 0x6; 1351 1352 if (nv_encoder->link & 1) 1353 proto = 0x8; 1354 else 1355 proto = 0x9; 1356 1357 nv50_audio_enable(encoder, mode); 1358 break; 1359 default: 1360 BUG(); 1361 break; 1362 } 1363 1364 nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth); 1365 } 1366 1367 static const struct drm_encoder_helper_funcs 1368 nv50_sor_help = { 1369 .atomic_check = nv50_outp_atomic_check, 1370 .enable = nv50_sor_enable, 1371 .disable = nv50_sor_disable, 1372 }; 1373 1374 static void 1375 nv50_sor_destroy(struct drm_encoder *encoder) 1376 { 1377 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1378 nv50_mstm_del(&nv_encoder->dp.mstm); 1379 drm_encoder_cleanup(encoder); 1380 kfree(encoder); 1381 } 1382 1383 static const struct drm_encoder_funcs 1384 nv50_sor_func = { 1385 .destroy = nv50_sor_destroy, 1386 }; 1387 1388 static int 1389 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe) 1390 { 1391 struct nouveau_connector *nv_connector = nouveau_connector(connector); 1392 struct nouveau_drm *drm = nouveau_drm(connector->dev); 1393 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 1394 struct nouveau_encoder *nv_encoder; 1395 struct drm_encoder *encoder; 1396 int type, ret; 1397 1398 switch (dcbe->type) { 1399 case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break; 1400 case DCB_OUTPUT_TMDS: 1401 case DCB_OUTPUT_DP: 1402 default: 1403 type = DRM_MODE_ENCODER_TMDS; 1404 break; 1405 } 1406 1407 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 1408 if (!nv_encoder) 1409 return -ENOMEM; 1410 nv_encoder->dcb = dcbe; 1411 nv_encoder->update = nv50_sor_update; 1412 1413 encoder = to_drm_encoder(nv_encoder); 1414 encoder->possible_crtcs = dcbe->heads; 1415 encoder->possible_clones = 0; 1416 drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type, 1417 "sor-%04x-%04x", dcbe->hasht, dcbe->hashm); 1418 drm_encoder_helper_add(encoder, &nv50_sor_help); 1419 1420 drm_mode_connector_attach_encoder(connector, encoder); 1421 1422 if (dcbe->type == DCB_OUTPUT_DP) { 1423 struct nv50_disp *disp = nv50_disp(encoder->dev); 1424 struct nvkm_i2c_aux *aux = 1425 nvkm_i2c_aux_find(i2c, dcbe->i2c_index); 1426 if (aux) { 1427 if (disp->disp->object.oclass < GF110_DISP) { 1428 /* HW has no support for address-only 1429 * transactions, so we're required to 1430 * use custom I2C-over-AUX code. 1431 */ 1432 nv_encoder->i2c = &aux->i2c; 1433 } else { 1434 nv_encoder->i2c = &nv_connector->aux.ddc; 1435 } 1436 nv_encoder->aux = aux; 1437 } 1438 1439 /*TODO: Use DP Info Table to check for support. */ 1440 if (disp->disp->object.oclass >= GF110_DISP) { 1441 ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 16, 1442 nv_connector->base.base.id, 1443 &nv_encoder->dp.mstm); 1444 if (ret) 1445 return ret; 1446 } 1447 } else { 1448 struct nvkm_i2c_bus *bus = 1449 nvkm_i2c_bus_find(i2c, dcbe->i2c_index); 1450 if (bus) 1451 nv_encoder->i2c = &bus->i2c; 1452 } 1453 1454 return 0; 1455 } 1456 1457 /****************************************************************************** 1458 * PIOR 1459 *****************************************************************************/ 1460 static int 1461 nv50_pior_atomic_check(struct drm_encoder *encoder, 1462 struct drm_crtc_state *crtc_state, 1463 struct drm_connector_state *conn_state) 1464 { 1465 int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state); 1466 if (ret) 1467 return ret; 1468 crtc_state->adjusted_mode.clock *= 2; 1469 return 0; 1470 } 1471 1472 static void 1473 nv50_pior_disable(struct drm_encoder *encoder) 1474 { 1475 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1476 struct nv50_core *core = nv50_disp(encoder->dev)->core; 1477 if (nv_encoder->crtc) 1478 core->func->pior->ctrl(core, nv_encoder->or, 0x00000000, NULL); 1479 nv_encoder->crtc = NULL; 1480 nv50_outp_release(nv_encoder); 1481 } 1482 1483 static void 1484 nv50_pior_enable(struct drm_encoder *encoder) 1485 { 1486 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1487 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 1488 struct nouveau_connector *nv_connector; 1489 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state); 1490 struct nv50_core *core = nv50_disp(encoder->dev)->core; 1491 u8 owner = 1 << nv_crtc->index; 1492 u8 proto; 1493 1494 nv50_outp_acquire(nv_encoder); 1495 1496 nv_connector = nouveau_encoder_connector_get(nv_encoder); 1497 switch (nv_connector->base.display_info.bpc) { 1498 case 10: asyh->or.depth = 0x6; break; 1499 case 8: asyh->or.depth = 0x5; break; 1500 case 6: asyh->or.depth = 0x2; break; 1501 default: asyh->or.depth = 0x0; break; 1502 } 1503 1504 switch (nv_encoder->dcb->type) { 1505 case DCB_OUTPUT_TMDS: 1506 case DCB_OUTPUT_DP: 1507 proto = 0x0; 1508 break; 1509 default: 1510 BUG(); 1511 break; 1512 } 1513 1514 core->func->pior->ctrl(core, nv_encoder->or, (proto << 8) | owner, asyh); 1515 nv_encoder->crtc = encoder->crtc; 1516 } 1517 1518 static const struct drm_encoder_helper_funcs 1519 nv50_pior_help = { 1520 .atomic_check = nv50_pior_atomic_check, 1521 .enable = nv50_pior_enable, 1522 .disable = nv50_pior_disable, 1523 }; 1524 1525 static void 1526 nv50_pior_destroy(struct drm_encoder *encoder) 1527 { 1528 drm_encoder_cleanup(encoder); 1529 kfree(encoder); 1530 } 1531 1532 static const struct drm_encoder_funcs 1533 nv50_pior_func = { 1534 .destroy = nv50_pior_destroy, 1535 }; 1536 1537 static int 1538 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe) 1539 { 1540 struct nouveau_drm *drm = nouveau_drm(connector->dev); 1541 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 1542 struct nvkm_i2c_bus *bus = NULL; 1543 struct nvkm_i2c_aux *aux = NULL; 1544 struct i2c_adapter *ddc; 1545 struct nouveau_encoder *nv_encoder; 1546 struct drm_encoder *encoder; 1547 int type; 1548 1549 switch (dcbe->type) { 1550 case DCB_OUTPUT_TMDS: 1551 bus = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev)); 1552 ddc = bus ? &bus->i2c : NULL; 1553 type = DRM_MODE_ENCODER_TMDS; 1554 break; 1555 case DCB_OUTPUT_DP: 1556 aux = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev)); 1557 ddc = aux ? &aux->i2c : NULL; 1558 type = DRM_MODE_ENCODER_TMDS; 1559 break; 1560 default: 1561 return -ENODEV; 1562 } 1563 1564 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 1565 if (!nv_encoder) 1566 return -ENOMEM; 1567 nv_encoder->dcb = dcbe; 1568 nv_encoder->i2c = ddc; 1569 nv_encoder->aux = aux; 1570 1571 encoder = to_drm_encoder(nv_encoder); 1572 encoder->possible_crtcs = dcbe->heads; 1573 encoder->possible_clones = 0; 1574 drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type, 1575 "pior-%04x-%04x", dcbe->hasht, dcbe->hashm); 1576 drm_encoder_helper_add(encoder, &nv50_pior_help); 1577 1578 drm_mode_connector_attach_encoder(connector, encoder); 1579 return 0; 1580 } 1581 1582 /****************************************************************************** 1583 * Atomic 1584 *****************************************************************************/ 1585 1586 static void 1587 nv50_disp_atomic_commit_core(struct nouveau_drm *drm, u32 interlock) 1588 { 1589 struct nv50_disp *disp = nv50_disp(drm->dev); 1590 struct nv50_core *core = disp->core; 1591 struct nv50_mstm *mstm; 1592 struct drm_encoder *encoder; 1593 1594 NV_ATOMIC(drm, "commit core %08x\n", interlock); 1595 1596 drm_for_each_encoder(encoder, drm->dev) { 1597 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 1598 mstm = nouveau_encoder(encoder)->dp.mstm; 1599 if (mstm && mstm->modified) 1600 nv50_mstm_prepare(mstm); 1601 } 1602 } 1603 1604 core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY); 1605 core->func->update(core, interlock, true); 1606 if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY, 1607 disp->core->chan.base.device)) 1608 NV_ERROR(drm, "core notifier timeout\n"); 1609 1610 drm_for_each_encoder(encoder, drm->dev) { 1611 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 1612 mstm = nouveau_encoder(encoder)->dp.mstm; 1613 if (mstm && mstm->modified) 1614 nv50_mstm_cleanup(mstm); 1615 } 1616 } 1617 } 1618 1619 static void 1620 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state) 1621 { 1622 struct drm_device *dev = state->dev; 1623 struct drm_crtc_state *new_crtc_state, *old_crtc_state; 1624 struct drm_crtc *crtc; 1625 struct drm_plane_state *new_plane_state; 1626 struct drm_plane *plane; 1627 struct nouveau_drm *drm = nouveau_drm(dev); 1628 struct nv50_disp *disp = nv50_disp(dev); 1629 struct nv50_atom *atom = nv50_atom(state); 1630 struct nv50_outp_atom *outp, *outt; 1631 u32 interlock_core = 0; 1632 u32 interlock_chan = 0; 1633 int i; 1634 1635 NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable); 1636 drm_atomic_helper_wait_for_fences(dev, state, false); 1637 drm_atomic_helper_wait_for_dependencies(state); 1638 drm_atomic_helper_update_legacy_modeset_state(dev, state); 1639 1640 if (atom->lock_core) 1641 mutex_lock(&disp->mutex); 1642 1643 /* Disable head(s). */ 1644 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 1645 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); 1646 struct nv50_head *head = nv50_head(crtc); 1647 1648 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name, 1649 asyh->clr.mask, asyh->set.mask); 1650 if (old_crtc_state->active && !new_crtc_state->active) 1651 drm_crtc_vblank_off(crtc); 1652 1653 if (asyh->clr.mask) { 1654 nv50_head_flush_clr(head, asyh, atom->flush_disable); 1655 interlock_core |= 1; 1656 } 1657 } 1658 1659 /* Disable plane(s). */ 1660 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 1661 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 1662 struct nv50_wndw *wndw = nv50_wndw(plane); 1663 1664 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name, 1665 asyw->clr.mask, asyw->set.mask); 1666 if (!asyw->clr.mask) 1667 continue; 1668 1669 interlock_chan |= nv50_wndw_flush_clr(wndw, interlock_core, 1670 atom->flush_disable, 1671 asyw); 1672 } 1673 1674 /* Disable output path(s). */ 1675 list_for_each_entry(outp, &atom->outp, head) { 1676 const struct drm_encoder_helper_funcs *help; 1677 struct drm_encoder *encoder; 1678 1679 encoder = outp->encoder; 1680 help = encoder->helper_private; 1681 1682 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name, 1683 outp->clr.mask, outp->set.mask); 1684 1685 if (outp->clr.mask) { 1686 help->disable(encoder); 1687 interlock_core |= 1; 1688 if (outp->flush_disable) { 1689 nv50_disp_atomic_commit_core(drm, interlock_chan); 1690 interlock_core = 0; 1691 interlock_chan = 0; 1692 } 1693 } 1694 } 1695 1696 /* Flush disable. */ 1697 if (interlock_core) { 1698 if (atom->flush_disable) { 1699 nv50_disp_atomic_commit_core(drm, interlock_chan); 1700 interlock_core = 0; 1701 interlock_chan = 0; 1702 } 1703 } 1704 1705 /* Update output path(s). */ 1706 list_for_each_entry_safe(outp, outt, &atom->outp, head) { 1707 const struct drm_encoder_helper_funcs *help; 1708 struct drm_encoder *encoder; 1709 1710 encoder = outp->encoder; 1711 help = encoder->helper_private; 1712 1713 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name, 1714 outp->set.mask, outp->clr.mask); 1715 1716 if (outp->set.mask) { 1717 help->enable(encoder); 1718 interlock_core = 1; 1719 } 1720 1721 list_del(&outp->head); 1722 kfree(outp); 1723 } 1724 1725 /* Update head(s). */ 1726 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 1727 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); 1728 struct nv50_head *head = nv50_head(crtc); 1729 1730 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name, 1731 asyh->set.mask, asyh->clr.mask); 1732 1733 if (asyh->set.mask) { 1734 nv50_head_flush_set(head, asyh); 1735 interlock_core = 1; 1736 } 1737 1738 if (new_crtc_state->active) { 1739 if (!old_crtc_state->active) 1740 drm_crtc_vblank_on(crtc); 1741 if (new_crtc_state->event) 1742 drm_crtc_vblank_get(crtc); 1743 } 1744 } 1745 1746 /* Update plane(s). */ 1747 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 1748 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 1749 struct nv50_wndw *wndw = nv50_wndw(plane); 1750 1751 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name, 1752 asyw->set.mask, asyw->clr.mask); 1753 if ( !asyw->set.mask && 1754 (!asyw->clr.mask || atom->flush_disable)) 1755 continue; 1756 1757 interlock_chan |= nv50_wndw_flush_set(wndw, interlock_core, asyw); 1758 } 1759 1760 /* Flush update. */ 1761 if (interlock_core) { 1762 if (interlock_chan || !atom->state.legacy_cursor_update) 1763 nv50_disp_atomic_commit_core(drm, interlock_chan); 1764 else 1765 disp->core->func->update(disp->core, 0, false); 1766 } 1767 1768 if (atom->lock_core) 1769 mutex_unlock(&disp->mutex); 1770 1771 /* Wait for HW to signal completion. */ 1772 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 1773 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 1774 struct nv50_wndw *wndw = nv50_wndw(plane); 1775 int ret = nv50_wndw_wait_armed(wndw, asyw); 1776 if (ret) 1777 NV_ERROR(drm, "%s: timeout\n", plane->name); 1778 } 1779 1780 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 1781 if (new_crtc_state->event) { 1782 unsigned long flags; 1783 /* Get correct count/ts if racing with vblank irq */ 1784 if (new_crtc_state->active) 1785 drm_crtc_accurate_vblank_count(crtc); 1786 spin_lock_irqsave(&crtc->dev->event_lock, flags); 1787 drm_crtc_send_vblank_event(crtc, new_crtc_state->event); 1788 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 1789 1790 new_crtc_state->event = NULL; 1791 if (new_crtc_state->active) 1792 drm_crtc_vblank_put(crtc); 1793 } 1794 } 1795 1796 drm_atomic_helper_commit_hw_done(state); 1797 drm_atomic_helper_cleanup_planes(dev, state); 1798 drm_atomic_helper_commit_cleanup_done(state); 1799 drm_atomic_state_put(state); 1800 } 1801 1802 static void 1803 nv50_disp_atomic_commit_work(struct work_struct *work) 1804 { 1805 struct drm_atomic_state *state = 1806 container_of(work, typeof(*state), commit_work); 1807 nv50_disp_atomic_commit_tail(state); 1808 } 1809 1810 static int 1811 nv50_disp_atomic_commit(struct drm_device *dev, 1812 struct drm_atomic_state *state, bool nonblock) 1813 { 1814 struct nouveau_drm *drm = nouveau_drm(dev); 1815 struct drm_plane_state *new_plane_state; 1816 struct drm_plane *plane; 1817 struct drm_crtc *crtc; 1818 bool active = false; 1819 int ret, i; 1820 1821 ret = pm_runtime_get_sync(dev->dev); 1822 if (ret < 0 && ret != -EACCES) 1823 return ret; 1824 1825 ret = drm_atomic_helper_setup_commit(state, nonblock); 1826 if (ret) 1827 goto done; 1828 1829 INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work); 1830 1831 ret = drm_atomic_helper_prepare_planes(dev, state); 1832 if (ret) 1833 goto done; 1834 1835 if (!nonblock) { 1836 ret = drm_atomic_helper_wait_for_fences(dev, state, true); 1837 if (ret) 1838 goto err_cleanup; 1839 } 1840 1841 ret = drm_atomic_helper_swap_state(state, true); 1842 if (ret) 1843 goto err_cleanup; 1844 1845 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 1846 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 1847 struct nv50_wndw *wndw = nv50_wndw(plane); 1848 1849 if (asyw->set.image) 1850 nv50_wndw_ntfy_enable(wndw, asyw); 1851 } 1852 1853 drm_atomic_state_get(state); 1854 1855 if (nonblock) 1856 queue_work(system_unbound_wq, &state->commit_work); 1857 else 1858 nv50_disp_atomic_commit_tail(state); 1859 1860 drm_for_each_crtc(crtc, dev) { 1861 if (crtc->state->enable) { 1862 if (!drm->have_disp_power_ref) { 1863 drm->have_disp_power_ref = true; 1864 return 0; 1865 } 1866 active = true; 1867 break; 1868 } 1869 } 1870 1871 if (!active && drm->have_disp_power_ref) { 1872 pm_runtime_put_autosuspend(dev->dev); 1873 drm->have_disp_power_ref = false; 1874 } 1875 1876 err_cleanup: 1877 if (ret) 1878 drm_atomic_helper_cleanup_planes(dev, state); 1879 done: 1880 pm_runtime_put_autosuspend(dev->dev); 1881 return ret; 1882 } 1883 1884 static struct nv50_outp_atom * 1885 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder) 1886 { 1887 struct nv50_outp_atom *outp; 1888 1889 list_for_each_entry(outp, &atom->outp, head) { 1890 if (outp->encoder == encoder) 1891 return outp; 1892 } 1893 1894 outp = kzalloc(sizeof(*outp), GFP_KERNEL); 1895 if (!outp) 1896 return ERR_PTR(-ENOMEM); 1897 1898 list_add(&outp->head, &atom->outp); 1899 outp->encoder = encoder; 1900 return outp; 1901 } 1902 1903 static int 1904 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom, 1905 struct drm_connector_state *old_connector_state) 1906 { 1907 struct drm_encoder *encoder = old_connector_state->best_encoder; 1908 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 1909 struct drm_crtc *crtc; 1910 struct nv50_outp_atom *outp; 1911 1912 if (!(crtc = old_connector_state->crtc)) 1913 return 0; 1914 1915 old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc); 1916 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc); 1917 if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) { 1918 outp = nv50_disp_outp_atomic_add(atom, encoder); 1919 if (IS_ERR(outp)) 1920 return PTR_ERR(outp); 1921 1922 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 1923 outp->flush_disable = true; 1924 atom->flush_disable = true; 1925 } 1926 outp->clr.ctrl = true; 1927 atom->lock_core = true; 1928 } 1929 1930 return 0; 1931 } 1932 1933 static int 1934 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom, 1935 struct drm_connector_state *connector_state) 1936 { 1937 struct drm_encoder *encoder = connector_state->best_encoder; 1938 struct drm_crtc_state *new_crtc_state; 1939 struct drm_crtc *crtc; 1940 struct nv50_outp_atom *outp; 1941 1942 if (!(crtc = connector_state->crtc)) 1943 return 0; 1944 1945 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc); 1946 if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) { 1947 outp = nv50_disp_outp_atomic_add(atom, encoder); 1948 if (IS_ERR(outp)) 1949 return PTR_ERR(outp); 1950 1951 outp->set.ctrl = true; 1952 atom->lock_core = true; 1953 } 1954 1955 return 0; 1956 } 1957 1958 static int 1959 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) 1960 { 1961 struct nv50_atom *atom = nv50_atom(state); 1962 struct drm_connector_state *old_connector_state, *new_connector_state; 1963 struct drm_connector *connector; 1964 int ret, i; 1965 1966 ret = drm_atomic_helper_check(dev, state); 1967 if (ret) 1968 return ret; 1969 1970 for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) { 1971 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state); 1972 if (ret) 1973 return ret; 1974 1975 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state); 1976 if (ret) 1977 return ret; 1978 } 1979 1980 return 0; 1981 } 1982 1983 static void 1984 nv50_disp_atomic_state_clear(struct drm_atomic_state *state) 1985 { 1986 struct nv50_atom *atom = nv50_atom(state); 1987 struct nv50_outp_atom *outp, *outt; 1988 1989 list_for_each_entry_safe(outp, outt, &atom->outp, head) { 1990 list_del(&outp->head); 1991 kfree(outp); 1992 } 1993 1994 drm_atomic_state_default_clear(state); 1995 } 1996 1997 static void 1998 nv50_disp_atomic_state_free(struct drm_atomic_state *state) 1999 { 2000 struct nv50_atom *atom = nv50_atom(state); 2001 drm_atomic_state_default_release(&atom->state); 2002 kfree(atom); 2003 } 2004 2005 static struct drm_atomic_state * 2006 nv50_disp_atomic_state_alloc(struct drm_device *dev) 2007 { 2008 struct nv50_atom *atom; 2009 if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) || 2010 drm_atomic_state_init(dev, &atom->state) < 0) { 2011 kfree(atom); 2012 return NULL; 2013 } 2014 INIT_LIST_HEAD(&atom->outp); 2015 return &atom->state; 2016 } 2017 2018 static const struct drm_mode_config_funcs 2019 nv50_disp_func = { 2020 .fb_create = nouveau_user_framebuffer_create, 2021 .output_poll_changed = drm_fb_helper_output_poll_changed, 2022 .atomic_check = nv50_disp_atomic_check, 2023 .atomic_commit = nv50_disp_atomic_commit, 2024 .atomic_state_alloc = nv50_disp_atomic_state_alloc, 2025 .atomic_state_clear = nv50_disp_atomic_state_clear, 2026 .atomic_state_free = nv50_disp_atomic_state_free, 2027 }; 2028 2029 /****************************************************************************** 2030 * Init 2031 *****************************************************************************/ 2032 2033 void 2034 nv50_display_fini(struct drm_device *dev) 2035 { 2036 struct nouveau_encoder *nv_encoder; 2037 struct drm_encoder *encoder; 2038 struct drm_plane *plane; 2039 2040 drm_for_each_plane(plane, dev) { 2041 struct nv50_wndw *wndw = nv50_wndw(plane); 2042 if (plane->funcs != &nv50_wndw) 2043 continue; 2044 nv50_wndw_fini(wndw); 2045 } 2046 2047 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2048 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 2049 nv_encoder = nouveau_encoder(encoder); 2050 nv50_mstm_fini(nv_encoder->dp.mstm); 2051 } 2052 } 2053 } 2054 2055 int 2056 nv50_display_init(struct drm_device *dev) 2057 { 2058 struct nv50_core *core = nv50_disp(dev)->core; 2059 struct drm_encoder *encoder; 2060 struct drm_plane *plane; 2061 2062 core->func->init(core); 2063 2064 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2065 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 2066 struct nouveau_encoder *nv_encoder = 2067 nouveau_encoder(encoder); 2068 nv50_mstm_init(nv_encoder->dp.mstm); 2069 } 2070 } 2071 2072 drm_for_each_plane(plane, dev) { 2073 struct nv50_wndw *wndw = nv50_wndw(plane); 2074 if (plane->funcs != &nv50_wndw) 2075 continue; 2076 nv50_wndw_init(wndw); 2077 } 2078 2079 return 0; 2080 } 2081 2082 void 2083 nv50_display_destroy(struct drm_device *dev) 2084 { 2085 struct nv50_disp *disp = nv50_disp(dev); 2086 2087 nv50_core_del(&disp->core); 2088 2089 nouveau_bo_unmap(disp->sync); 2090 if (disp->sync) 2091 nouveau_bo_unpin(disp->sync); 2092 nouveau_bo_ref(NULL, &disp->sync); 2093 2094 nouveau_display(dev)->priv = NULL; 2095 kfree(disp); 2096 } 2097 2098 MODULE_PARM_DESC(atomic, "Expose atomic ioctl (default: disabled)"); 2099 static int nouveau_atomic = 0; 2100 module_param_named(atomic, nouveau_atomic, int, 0400); 2101 2102 int 2103 nv50_display_create(struct drm_device *dev) 2104 { 2105 struct nvif_device *device = &nouveau_drm(dev)->client.device; 2106 struct nouveau_drm *drm = nouveau_drm(dev); 2107 struct dcb_table *dcb = &drm->vbios.dcb; 2108 struct drm_connector *connector, *tmp; 2109 struct nv50_disp *disp; 2110 struct dcb_output *dcbe; 2111 int crtcs, ret, i; 2112 2113 disp = kzalloc(sizeof(*disp), GFP_KERNEL); 2114 if (!disp) 2115 return -ENOMEM; 2116 2117 mutex_init(&disp->mutex); 2118 2119 nouveau_display(dev)->priv = disp; 2120 nouveau_display(dev)->dtor = nv50_display_destroy; 2121 nouveau_display(dev)->init = nv50_display_init; 2122 nouveau_display(dev)->fini = nv50_display_fini; 2123 disp->disp = &nouveau_display(dev)->disp; 2124 dev->mode_config.funcs = &nv50_disp_func; 2125 dev->driver->driver_features |= DRIVER_PREFER_XBGR_30BPP; 2126 if (nouveau_atomic) 2127 dev->driver->driver_features |= DRIVER_ATOMIC; 2128 2129 /* small shared memory area we use for notifiers and semaphores */ 2130 ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM, 2131 0, 0x0000, NULL, NULL, &disp->sync); 2132 if (!ret) { 2133 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true); 2134 if (!ret) { 2135 ret = nouveau_bo_map(disp->sync); 2136 if (ret) 2137 nouveau_bo_unpin(disp->sync); 2138 } 2139 if (ret) 2140 nouveau_bo_ref(NULL, &disp->sync); 2141 } 2142 2143 if (ret) 2144 goto out; 2145 2146 /* allocate master evo channel */ 2147 ret = nv50_core_new(drm, &disp->core); 2148 if (ret) 2149 goto out; 2150 2151 /* create crtc objects to represent the hw heads */ 2152 if (disp->disp->object.oclass >= GF110_DISP) 2153 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf; 2154 else 2155 crtcs = 0x3; 2156 2157 for (i = 0; i < fls(crtcs); i++) { 2158 if (!(crtcs & (1 << i))) 2159 continue; 2160 ret = nv50_head_create(dev, i); 2161 if (ret) 2162 goto out; 2163 } 2164 2165 /* create encoder/connector objects based on VBIOS DCB table */ 2166 for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) { 2167 connector = nouveau_connector_create(dev, dcbe->connector); 2168 if (IS_ERR(connector)) 2169 continue; 2170 2171 if (dcbe->location == DCB_LOC_ON_CHIP) { 2172 switch (dcbe->type) { 2173 case DCB_OUTPUT_TMDS: 2174 case DCB_OUTPUT_LVDS: 2175 case DCB_OUTPUT_DP: 2176 ret = nv50_sor_create(connector, dcbe); 2177 break; 2178 case DCB_OUTPUT_ANALOG: 2179 ret = nv50_dac_create(connector, dcbe); 2180 break; 2181 default: 2182 ret = -ENODEV; 2183 break; 2184 } 2185 } else { 2186 ret = nv50_pior_create(connector, dcbe); 2187 } 2188 2189 if (ret) { 2190 NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n", 2191 dcbe->location, dcbe->type, 2192 ffs(dcbe->or) - 1, ret); 2193 ret = 0; 2194 } 2195 } 2196 2197 /* cull any connectors we created that don't have an encoder */ 2198 list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) { 2199 if (connector->encoder_ids[0]) 2200 continue; 2201 2202 NV_WARN(drm, "%s has no encoders, removing\n", 2203 connector->name); 2204 connector->funcs->destroy(connector); 2205 } 2206 2207 out: 2208 if (ret) 2209 nv50_display_destroy(dev); 2210 return ret; 2211 } 2212