1 /* 2 * Copyright 2011 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "disp.h" 25 #include "atom.h" 26 #include "core.h" 27 #include "head.h" 28 #include "wndw.h" 29 #include "handles.h" 30 31 #include <linux/dma-mapping.h> 32 #include <linux/hdmi.h> 33 #include <linux/component.h> 34 35 #include <drm/drm_atomic_helper.h> 36 #include <drm/drm_dp_helper.h> 37 #include <drm/drm_edid.h> 38 #include <drm/drm_fb_helper.h> 39 #include <drm/drm_plane_helper.h> 40 #include <drm/drm_probe_helper.h> 41 #include <drm/drm_scdc_helper.h> 42 #include <drm/drm_vblank.h> 43 44 #include <nvif/class.h> 45 #include <nvif/cl0002.h> 46 #include <nvif/cl5070.h> 47 #include <nvif/cl507d.h> 48 #include <nvif/event.h> 49 #include <nvif/timer.h> 50 51 #include "nouveau_drv.h" 52 #include "nouveau_dma.h" 53 #include "nouveau_gem.h" 54 #include "nouveau_connector.h" 55 #include "nouveau_encoder.h" 56 #include "nouveau_fence.h" 57 #include "nouveau_fbcon.h" 58 59 #include <subdev/bios/dp.h> 60 61 /****************************************************************************** 62 * EVO channel 63 *****************************************************************************/ 64 65 static int 66 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp, 67 const s32 *oclass, u8 head, void *data, u32 size, 68 struct nv50_chan *chan) 69 { 70 struct nvif_sclass *sclass; 71 int ret, i, n; 72 73 chan->device = device; 74 75 ret = n = nvif_object_sclass_get(disp, &sclass); 76 if (ret < 0) 77 return ret; 78 79 while (oclass[0]) { 80 for (i = 0; i < n; i++) { 81 if (sclass[i].oclass == oclass[0]) { 82 ret = nvif_object_init(disp, 0, oclass[0], 83 data, size, &chan->user); 84 if (ret == 0) 85 nvif_object_map(&chan->user, NULL, 0); 86 nvif_object_sclass_put(&sclass); 87 return ret; 88 } 89 } 90 oclass++; 91 } 92 93 nvif_object_sclass_put(&sclass); 94 return -ENOSYS; 95 } 96 97 static void 98 nv50_chan_destroy(struct nv50_chan *chan) 99 { 100 nvif_object_fini(&chan->user); 101 } 102 103 /****************************************************************************** 104 * DMA EVO channel 105 *****************************************************************************/ 106 107 void 108 nv50_dmac_destroy(struct nv50_dmac *dmac) 109 { 110 nvif_object_fini(&dmac->vram); 111 nvif_object_fini(&dmac->sync); 112 113 nv50_chan_destroy(&dmac->base); 114 115 nvif_mem_fini(&dmac->push); 116 } 117 118 int 119 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp, 120 const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf, 121 struct nv50_dmac *dmac) 122 { 123 struct nouveau_cli *cli = (void *)device->object.client; 124 struct nv50_disp_core_channel_dma_v0 *args = data; 125 u8 type = NVIF_MEM_COHERENT; 126 int ret; 127 128 mutex_init(&dmac->lock); 129 130 /* Pascal added support for 47-bit physical addresses, but some 131 * parts of EVO still only accept 40-bit PAs. 132 * 133 * To avoid issues on systems with large amounts of RAM, and on 134 * systems where an IOMMU maps pages at a high address, we need 135 * to allocate push buffers in VRAM instead. 136 * 137 * This appears to match NVIDIA's behaviour on Pascal. 138 */ 139 if (device->info.family == NV_DEVICE_INFO_V0_PASCAL) 140 type |= NVIF_MEM_VRAM; 141 142 ret = nvif_mem_init_map(&cli->mmu, type, 0x1000, &dmac->push); 143 if (ret) 144 return ret; 145 146 dmac->ptr = dmac->push.object.map.ptr; 147 148 args->pushbuf = nvif_handle(&dmac->push.object); 149 150 ret = nv50_chan_create(device, disp, oclass, head, data, size, 151 &dmac->base); 152 if (ret) 153 return ret; 154 155 if (!syncbuf) 156 return 0; 157 158 ret = nvif_object_init(&dmac->base.user, NV50_DISP_HANDLE_SYNCBUF, 159 NV_DMA_IN_MEMORY, 160 &(struct nv_dma_v0) { 161 .target = NV_DMA_V0_TARGET_VRAM, 162 .access = NV_DMA_V0_ACCESS_RDWR, 163 .start = syncbuf + 0x0000, 164 .limit = syncbuf + 0x0fff, 165 }, sizeof(struct nv_dma_v0), 166 &dmac->sync); 167 if (ret) 168 return ret; 169 170 ret = nvif_object_init(&dmac->base.user, NV50_DISP_HANDLE_VRAM, 171 NV_DMA_IN_MEMORY, 172 &(struct nv_dma_v0) { 173 .target = NV_DMA_V0_TARGET_VRAM, 174 .access = NV_DMA_V0_ACCESS_RDWR, 175 .start = 0, 176 .limit = device->info.ram_user - 1, 177 }, sizeof(struct nv_dma_v0), 178 &dmac->vram); 179 if (ret) 180 return ret; 181 182 return ret; 183 } 184 185 /****************************************************************************** 186 * EVO channel helpers 187 *****************************************************************************/ 188 static void 189 evo_flush(struct nv50_dmac *dmac) 190 { 191 /* Push buffer fetches are not coherent with BAR1, we need to ensure 192 * writes have been flushed right through to VRAM before writing PUT. 193 */ 194 if (dmac->push.type & NVIF_MEM_VRAM) { 195 struct nvif_device *device = dmac->base.device; 196 nvif_wr32(&device->object, 0x070000, 0x00000001); 197 nvif_msec(device, 2000, 198 if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002)) 199 break; 200 ); 201 } 202 } 203 204 u32 * 205 evo_wait(struct nv50_dmac *evoc, int nr) 206 { 207 struct nv50_dmac *dmac = evoc; 208 struct nvif_device *device = dmac->base.device; 209 u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4; 210 211 mutex_lock(&dmac->lock); 212 if (put + nr >= (PAGE_SIZE / 4) - 8) { 213 dmac->ptr[put] = 0x20000000; 214 evo_flush(dmac); 215 216 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000); 217 if (nvif_msec(device, 2000, 218 if (!nvif_rd32(&dmac->base.user, 0x0004)) 219 break; 220 ) < 0) { 221 mutex_unlock(&dmac->lock); 222 pr_err("nouveau: evo channel stalled\n"); 223 return NULL; 224 } 225 226 put = 0; 227 } 228 229 return dmac->ptr + put; 230 } 231 232 void 233 evo_kick(u32 *push, struct nv50_dmac *evoc) 234 { 235 struct nv50_dmac *dmac = evoc; 236 237 evo_flush(dmac); 238 239 nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2); 240 mutex_unlock(&dmac->lock); 241 } 242 243 /****************************************************************************** 244 * Output path helpers 245 *****************************************************************************/ 246 static void 247 nv50_outp_release(struct nouveau_encoder *nv_encoder) 248 { 249 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev); 250 struct { 251 struct nv50_disp_mthd_v1 base; 252 } args = { 253 .base.version = 1, 254 .base.method = NV50_DISP_MTHD_V1_RELEASE, 255 .base.hasht = nv_encoder->dcb->hasht, 256 .base.hashm = nv_encoder->dcb->hashm, 257 }; 258 259 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 260 nv_encoder->or = -1; 261 nv_encoder->link = 0; 262 } 263 264 static int 265 nv50_outp_acquire(struct nouveau_encoder *nv_encoder, bool hda) 266 { 267 struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); 268 struct nv50_disp *disp = nv50_disp(drm->dev); 269 struct { 270 struct nv50_disp_mthd_v1 base; 271 struct nv50_disp_acquire_v0 info; 272 } args = { 273 .base.version = 1, 274 .base.method = NV50_DISP_MTHD_V1_ACQUIRE, 275 .base.hasht = nv_encoder->dcb->hasht, 276 .base.hashm = nv_encoder->dcb->hashm, 277 .info.hda = hda, 278 }; 279 int ret; 280 281 ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 282 if (ret) { 283 NV_ERROR(drm, "error acquiring output path: %d\n", ret); 284 return ret; 285 } 286 287 nv_encoder->or = args.info.or; 288 nv_encoder->link = args.info.link; 289 return 0; 290 } 291 292 static int 293 nv50_outp_atomic_check_view(struct drm_encoder *encoder, 294 struct drm_crtc_state *crtc_state, 295 struct drm_connector_state *conn_state, 296 struct drm_display_mode *native_mode) 297 { 298 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 299 struct drm_display_mode *mode = &crtc_state->mode; 300 struct drm_connector *connector = conn_state->connector; 301 struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state); 302 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 303 304 NV_ATOMIC(drm, "%s atomic_check\n", encoder->name); 305 asyc->scaler.full = false; 306 if (!native_mode) 307 return 0; 308 309 if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) { 310 switch (connector->connector_type) { 311 case DRM_MODE_CONNECTOR_LVDS: 312 case DRM_MODE_CONNECTOR_eDP: 313 /* Don't force scaler for EDID modes with 314 * same size as the native one (e.g. different 315 * refresh rate) 316 */ 317 if (mode->hdisplay == native_mode->hdisplay && 318 mode->vdisplay == native_mode->vdisplay && 319 mode->type & DRM_MODE_TYPE_DRIVER) 320 break; 321 mode = native_mode; 322 asyc->scaler.full = true; 323 break; 324 default: 325 break; 326 } 327 } else { 328 mode = native_mode; 329 } 330 331 if (!drm_mode_equal(adjusted_mode, mode)) { 332 drm_mode_copy(adjusted_mode, mode); 333 crtc_state->mode_changed = true; 334 } 335 336 return 0; 337 } 338 339 static int 340 nv50_outp_atomic_check(struct drm_encoder *encoder, 341 struct drm_crtc_state *crtc_state, 342 struct drm_connector_state *conn_state) 343 { 344 struct drm_connector *connector = conn_state->connector; 345 struct nouveau_connector *nv_connector = nouveau_connector(connector); 346 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state); 347 int ret; 348 349 ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state, 350 nv_connector->native_mode); 351 if (ret) 352 return ret; 353 354 if (crtc_state->mode_changed || crtc_state->connectors_changed) 355 asyh->or.bpc = connector->display_info.bpc; 356 357 return 0; 358 } 359 360 /****************************************************************************** 361 * DAC 362 *****************************************************************************/ 363 static void 364 nv50_dac_disable(struct drm_encoder *encoder) 365 { 366 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 367 struct nv50_core *core = nv50_disp(encoder->dev)->core; 368 if (nv_encoder->crtc) 369 core->func->dac->ctrl(core, nv_encoder->or, 0x00000000, NULL); 370 nv_encoder->crtc = NULL; 371 nv50_outp_release(nv_encoder); 372 } 373 374 static void 375 nv50_dac_enable(struct drm_encoder *encoder) 376 { 377 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 378 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 379 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state); 380 struct nv50_core *core = nv50_disp(encoder->dev)->core; 381 382 nv50_outp_acquire(nv_encoder, false); 383 384 core->func->dac->ctrl(core, nv_encoder->or, 1 << nv_crtc->index, asyh); 385 asyh->or.depth = 0; 386 387 nv_encoder->crtc = encoder->crtc; 388 } 389 390 static enum drm_connector_status 391 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) 392 { 393 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 394 struct nv50_disp *disp = nv50_disp(encoder->dev); 395 struct { 396 struct nv50_disp_mthd_v1 base; 397 struct nv50_disp_dac_load_v0 load; 398 } args = { 399 .base.version = 1, 400 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD, 401 .base.hasht = nv_encoder->dcb->hasht, 402 .base.hashm = nv_encoder->dcb->hashm, 403 }; 404 int ret; 405 406 args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval; 407 if (args.load.data == 0) 408 args.load.data = 340; 409 410 ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 411 if (ret || !args.load.load) 412 return connector_status_disconnected; 413 414 return connector_status_connected; 415 } 416 417 static const struct drm_encoder_helper_funcs 418 nv50_dac_help = { 419 .atomic_check = nv50_outp_atomic_check, 420 .enable = nv50_dac_enable, 421 .disable = nv50_dac_disable, 422 .detect = nv50_dac_detect 423 }; 424 425 static void 426 nv50_dac_destroy(struct drm_encoder *encoder) 427 { 428 drm_encoder_cleanup(encoder); 429 kfree(encoder); 430 } 431 432 static const struct drm_encoder_funcs 433 nv50_dac_func = { 434 .destroy = nv50_dac_destroy, 435 }; 436 437 static int 438 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe) 439 { 440 struct nouveau_drm *drm = nouveau_drm(connector->dev); 441 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 442 struct nvkm_i2c_bus *bus; 443 struct nouveau_encoder *nv_encoder; 444 struct drm_encoder *encoder; 445 int type = DRM_MODE_ENCODER_DAC; 446 447 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 448 if (!nv_encoder) 449 return -ENOMEM; 450 nv_encoder->dcb = dcbe; 451 452 bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index); 453 if (bus) 454 nv_encoder->i2c = &bus->i2c; 455 456 encoder = to_drm_encoder(nv_encoder); 457 encoder->possible_crtcs = dcbe->heads; 458 encoder->possible_clones = 0; 459 drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type, 460 "dac-%04x-%04x", dcbe->hasht, dcbe->hashm); 461 drm_encoder_helper_add(encoder, &nv50_dac_help); 462 463 drm_connector_attach_encoder(connector, encoder); 464 return 0; 465 } 466 467 /* 468 * audio component binding for ELD notification 469 */ 470 static void 471 nv50_audio_component_eld_notify(struct drm_audio_component *acomp, int port, 472 int dev_id) 473 { 474 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) 475 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, 476 port, dev_id); 477 } 478 479 static int 480 nv50_audio_component_get_eld(struct device *kdev, int port, int dev_id, 481 bool *enabled, unsigned char *buf, int max_bytes) 482 { 483 struct drm_device *drm_dev = dev_get_drvdata(kdev); 484 struct nouveau_drm *drm = nouveau_drm(drm_dev); 485 struct drm_encoder *encoder; 486 struct nouveau_encoder *nv_encoder; 487 struct nouveau_connector *nv_connector; 488 struct nouveau_crtc *nv_crtc; 489 int ret = 0; 490 491 *enabled = false; 492 drm_for_each_encoder(encoder, drm->dev) { 493 nv_encoder = nouveau_encoder(encoder); 494 nv_connector = nouveau_encoder_connector_get(nv_encoder); 495 nv_crtc = nouveau_crtc(encoder->crtc); 496 if (!nv_connector || !nv_crtc || nv_encoder->or != port || 497 nv_crtc->index != dev_id) 498 continue; 499 *enabled = nv_encoder->audio; 500 if (*enabled) { 501 ret = drm_eld_size(nv_connector->base.eld); 502 memcpy(buf, nv_connector->base.eld, 503 min(max_bytes, ret)); 504 } 505 break; 506 } 507 return ret; 508 } 509 510 static const struct drm_audio_component_ops nv50_audio_component_ops = { 511 .get_eld = nv50_audio_component_get_eld, 512 }; 513 514 static int 515 nv50_audio_component_bind(struct device *kdev, struct device *hda_kdev, 516 void *data) 517 { 518 struct drm_device *drm_dev = dev_get_drvdata(kdev); 519 struct nouveau_drm *drm = nouveau_drm(drm_dev); 520 struct drm_audio_component *acomp = data; 521 522 if (WARN_ON(!device_link_add(hda_kdev, kdev, DL_FLAG_STATELESS))) 523 return -ENOMEM; 524 525 drm_modeset_lock_all(drm_dev); 526 acomp->ops = &nv50_audio_component_ops; 527 acomp->dev = kdev; 528 drm->audio.component = acomp; 529 drm_modeset_unlock_all(drm_dev); 530 return 0; 531 } 532 533 static void 534 nv50_audio_component_unbind(struct device *kdev, struct device *hda_kdev, 535 void *data) 536 { 537 struct drm_device *drm_dev = dev_get_drvdata(kdev); 538 struct nouveau_drm *drm = nouveau_drm(drm_dev); 539 struct drm_audio_component *acomp = data; 540 541 drm_modeset_lock_all(drm_dev); 542 drm->audio.component = NULL; 543 acomp->ops = NULL; 544 acomp->dev = NULL; 545 drm_modeset_unlock_all(drm_dev); 546 } 547 548 static const struct component_ops nv50_audio_component_bind_ops = { 549 .bind = nv50_audio_component_bind, 550 .unbind = nv50_audio_component_unbind, 551 }; 552 553 static void 554 nv50_audio_component_init(struct nouveau_drm *drm) 555 { 556 if (!component_add(drm->dev->dev, &nv50_audio_component_bind_ops)) 557 drm->audio.component_registered = true; 558 } 559 560 static void 561 nv50_audio_component_fini(struct nouveau_drm *drm) 562 { 563 if (drm->audio.component_registered) { 564 component_del(drm->dev->dev, &nv50_audio_component_bind_ops); 565 drm->audio.component_registered = false; 566 } 567 } 568 569 /****************************************************************************** 570 * Audio 571 *****************************************************************************/ 572 static void 573 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) 574 { 575 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 576 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 577 struct nv50_disp *disp = nv50_disp(encoder->dev); 578 struct { 579 struct nv50_disp_mthd_v1 base; 580 struct nv50_disp_sor_hda_eld_v0 eld; 581 } args = { 582 .base.version = 1, 583 .base.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD, 584 .base.hasht = nv_encoder->dcb->hasht, 585 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 586 (0x0100 << nv_crtc->index), 587 }; 588 589 if (!nv_encoder->audio) 590 return; 591 592 nv_encoder->audio = false; 593 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 594 595 nv50_audio_component_eld_notify(drm->audio.component, nv_encoder->or, 596 nv_crtc->index); 597 } 598 599 static void 600 nv50_audio_enable(struct drm_encoder *encoder, struct drm_display_mode *mode) 601 { 602 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 603 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 604 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 605 struct nouveau_connector *nv_connector; 606 struct nv50_disp *disp = nv50_disp(encoder->dev); 607 struct __packed { 608 struct { 609 struct nv50_disp_mthd_v1 mthd; 610 struct nv50_disp_sor_hda_eld_v0 eld; 611 } base; 612 u8 data[sizeof(nv_connector->base.eld)]; 613 } args = { 614 .base.mthd.version = 1, 615 .base.mthd.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD, 616 .base.mthd.hasht = nv_encoder->dcb->hasht, 617 .base.mthd.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 618 (0x0100 << nv_crtc->index), 619 }; 620 621 nv_connector = nouveau_encoder_connector_get(nv_encoder); 622 if (!drm_detect_monitor_audio(nv_connector->edid)) 623 return; 624 625 memcpy(args.data, nv_connector->base.eld, sizeof(args.data)); 626 627 nvif_mthd(&disp->disp->object, 0, &args, 628 sizeof(args.base) + drm_eld_size(args.data)); 629 nv_encoder->audio = true; 630 631 nv50_audio_component_eld_notify(drm->audio.component, nv_encoder->or, 632 nv_crtc->index); 633 } 634 635 /****************************************************************************** 636 * HDMI 637 *****************************************************************************/ 638 static void 639 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) 640 { 641 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 642 struct nv50_disp *disp = nv50_disp(encoder->dev); 643 struct { 644 struct nv50_disp_mthd_v1 base; 645 struct nv50_disp_sor_hdmi_pwr_v0 pwr; 646 } args = { 647 .base.version = 1, 648 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR, 649 .base.hasht = nv_encoder->dcb->hasht, 650 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 651 (0x0100 << nv_crtc->index), 652 }; 653 654 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 655 } 656 657 static void 658 nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_display_mode *mode) 659 { 660 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 661 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 662 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 663 struct nv50_disp *disp = nv50_disp(encoder->dev); 664 struct { 665 struct nv50_disp_mthd_v1 base; 666 struct nv50_disp_sor_hdmi_pwr_v0 pwr; 667 u8 infoframes[2 * 17]; /* two frames, up to 17 bytes each */ 668 } args = { 669 .base.version = 1, 670 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR, 671 .base.hasht = nv_encoder->dcb->hasht, 672 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 673 (0x0100 << nv_crtc->index), 674 .pwr.state = 1, 675 .pwr.rekey = 56, /* binary driver, and tegra, constant */ 676 }; 677 struct nouveau_connector *nv_connector; 678 struct drm_hdmi_info *hdmi; 679 u32 max_ac_packet; 680 union hdmi_infoframe avi_frame; 681 union hdmi_infoframe vendor_frame; 682 bool high_tmds_clock_ratio = false, scrambling = false; 683 u8 config; 684 int ret; 685 int size; 686 687 nv_connector = nouveau_encoder_connector_get(nv_encoder); 688 if (!drm_detect_hdmi_monitor(nv_connector->edid)) 689 return; 690 691 hdmi = &nv_connector->base.display_info.hdmi; 692 693 ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi, 694 &nv_connector->base, mode); 695 if (!ret) { 696 /* We have an AVI InfoFrame, populate it to the display */ 697 args.pwr.avi_infoframe_length 698 = hdmi_infoframe_pack(&avi_frame, args.infoframes, 17); 699 } 700 701 ret = drm_hdmi_vendor_infoframe_from_display_mode(&vendor_frame.vendor.hdmi, 702 &nv_connector->base, mode); 703 if (!ret) { 704 /* We have a Vendor InfoFrame, populate it to the display */ 705 args.pwr.vendor_infoframe_length 706 = hdmi_infoframe_pack(&vendor_frame, 707 args.infoframes 708 + args.pwr.avi_infoframe_length, 709 17); 710 } 711 712 max_ac_packet = mode->htotal - mode->hdisplay; 713 max_ac_packet -= args.pwr.rekey; 714 max_ac_packet -= 18; /* constant from tegra */ 715 args.pwr.max_ac_packet = max_ac_packet / 32; 716 717 if (hdmi->scdc.scrambling.supported) { 718 high_tmds_clock_ratio = mode->clock > 340000; 719 scrambling = high_tmds_clock_ratio || 720 hdmi->scdc.scrambling.low_rates; 721 } 722 723 args.pwr.scdc = 724 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_SCRAMBLE * scrambling | 725 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_DIV_BY_4 * high_tmds_clock_ratio; 726 727 size = sizeof(args.base) 728 + sizeof(args.pwr) 729 + args.pwr.avi_infoframe_length 730 + args.pwr.vendor_infoframe_length; 731 nvif_mthd(&disp->disp->object, 0, &args, size); 732 733 nv50_audio_enable(encoder, mode); 734 735 /* If SCDC is supported by the downstream monitor, update 736 * divider / scrambling settings to what we programmed above. 737 */ 738 if (!hdmi->scdc.scrambling.supported) 739 return; 740 741 ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &config); 742 if (ret < 0) { 743 NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret); 744 return; 745 } 746 config &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE); 747 config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 * high_tmds_clock_ratio; 748 config |= SCDC_SCRAMBLING_ENABLE * scrambling; 749 ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, config); 750 if (ret < 0) 751 NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n", 752 config, ret); 753 } 754 755 /****************************************************************************** 756 * MST 757 *****************************************************************************/ 758 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr) 759 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector) 760 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder) 761 762 struct nv50_mstm { 763 struct nouveau_encoder *outp; 764 765 struct drm_dp_mst_topology_mgr mgr; 766 767 bool modified; 768 bool disabled; 769 int links; 770 }; 771 772 struct nv50_mstc { 773 struct nv50_mstm *mstm; 774 struct drm_dp_mst_port *port; 775 struct drm_connector connector; 776 777 struct drm_display_mode *native; 778 struct edid *edid; 779 }; 780 781 struct nv50_msto { 782 struct drm_encoder encoder; 783 784 struct nv50_head *head; 785 struct nv50_mstc *mstc; 786 bool disabled; 787 }; 788 789 struct nouveau_encoder *nv50_real_outp(struct drm_encoder *encoder) 790 { 791 struct nv50_msto *msto; 792 793 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) 794 return nouveau_encoder(encoder); 795 796 msto = nv50_msto(encoder); 797 if (!msto->mstc) 798 return NULL; 799 return msto->mstc->mstm->outp; 800 } 801 802 static struct drm_dp_payload * 803 nv50_msto_payload(struct nv50_msto *msto) 804 { 805 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); 806 struct nv50_mstc *mstc = msto->mstc; 807 struct nv50_mstm *mstm = mstc->mstm; 808 int vcpi = mstc->port->vcpi.vcpi, i; 809 810 WARN_ON(!mutex_is_locked(&mstm->mgr.payload_lock)); 811 812 NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi); 813 for (i = 0; i < mstm->mgr.max_payloads; i++) { 814 struct drm_dp_payload *payload = &mstm->mgr.payloads[i]; 815 NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n", 816 mstm->outp->base.base.name, i, payload->vcpi, 817 payload->start_slot, payload->num_slots); 818 } 819 820 for (i = 0; i < mstm->mgr.max_payloads; i++) { 821 struct drm_dp_payload *payload = &mstm->mgr.payloads[i]; 822 if (payload->vcpi == vcpi) 823 return payload; 824 } 825 826 return NULL; 827 } 828 829 static void 830 nv50_msto_cleanup(struct nv50_msto *msto) 831 { 832 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); 833 struct nv50_mstc *mstc = msto->mstc; 834 struct nv50_mstm *mstm = mstc->mstm; 835 836 if (!msto->disabled) 837 return; 838 839 NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name); 840 841 drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port); 842 843 msto->mstc = NULL; 844 msto->disabled = false; 845 } 846 847 static void 848 nv50_msto_prepare(struct nv50_msto *msto) 849 { 850 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); 851 struct nv50_mstc *mstc = msto->mstc; 852 struct nv50_mstm *mstm = mstc->mstm; 853 struct { 854 struct nv50_disp_mthd_v1 base; 855 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi; 856 } args = { 857 .base.version = 1, 858 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI, 859 .base.hasht = mstm->outp->dcb->hasht, 860 .base.hashm = (0xf0ff & mstm->outp->dcb->hashm) | 861 (0x0100 << msto->head->base.index), 862 }; 863 864 mutex_lock(&mstm->mgr.payload_lock); 865 866 NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name); 867 if (mstc->port->vcpi.vcpi > 0) { 868 struct drm_dp_payload *payload = nv50_msto_payload(msto); 869 if (payload) { 870 args.vcpi.start_slot = payload->start_slot; 871 args.vcpi.num_slots = payload->num_slots; 872 args.vcpi.pbn = mstc->port->vcpi.pbn; 873 args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn; 874 } 875 } 876 877 NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n", 878 msto->encoder.name, msto->head->base.base.name, 879 args.vcpi.start_slot, args.vcpi.num_slots, 880 args.vcpi.pbn, args.vcpi.aligned_pbn); 881 882 nvif_mthd(&drm->display->disp.object, 0, &args, sizeof(args)); 883 mutex_unlock(&mstm->mgr.payload_lock); 884 } 885 886 static int 887 nv50_msto_atomic_check(struct drm_encoder *encoder, 888 struct drm_crtc_state *crtc_state, 889 struct drm_connector_state *conn_state) 890 { 891 struct drm_atomic_state *state = crtc_state->state; 892 struct drm_connector *connector = conn_state->connector; 893 struct nv50_mstc *mstc = nv50_mstc(connector); 894 struct nv50_mstm *mstm = mstc->mstm; 895 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state); 896 int slots; 897 int ret; 898 899 ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state, 900 mstc->native); 901 if (ret) 902 return ret; 903 904 if (!crtc_state->mode_changed && !crtc_state->connectors_changed) 905 return 0; 906 907 /* 908 * When restoring duplicated states, we need to make sure that the bw 909 * remains the same and avoid recalculating it, as the connector's bpc 910 * may have changed after the state was duplicated 911 */ 912 if (!state->duplicated) { 913 const int clock = crtc_state->adjusted_mode.clock; 914 915 asyh->or.bpc = connector->display_info.bpc; 916 asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3, 917 false); 918 } 919 920 slots = drm_dp_atomic_find_vcpi_slots(state, &mstm->mgr, mstc->port, 921 asyh->dp.pbn, 0); 922 if (slots < 0) 923 return slots; 924 925 asyh->dp.tu = slots; 926 927 return 0; 928 } 929 930 static u8 931 nv50_dp_bpc_to_depth(unsigned int bpc) 932 { 933 switch (bpc) { 934 case 6: return 0x2; 935 case 8: return 0x5; 936 case 10: /* fall-through */ 937 default: return 0x6; 938 } 939 } 940 941 static void 942 nv50_msto_enable(struct drm_encoder *encoder) 943 { 944 struct nv50_head *head = nv50_head(encoder->crtc); 945 struct nv50_head_atom *armh = nv50_head_atom(head->base.base.state); 946 struct nv50_msto *msto = nv50_msto(encoder); 947 struct nv50_mstc *mstc = NULL; 948 struct nv50_mstm *mstm = NULL; 949 struct drm_connector *connector; 950 struct drm_connector_list_iter conn_iter; 951 u8 proto; 952 bool r; 953 954 drm_connector_list_iter_begin(encoder->dev, &conn_iter); 955 drm_for_each_connector_iter(connector, &conn_iter) { 956 if (connector->state->best_encoder == &msto->encoder) { 957 mstc = nv50_mstc(connector); 958 mstm = mstc->mstm; 959 break; 960 } 961 } 962 drm_connector_list_iter_end(&conn_iter); 963 964 if (WARN_ON(!mstc)) 965 return; 966 967 r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, armh->dp.pbn, 968 armh->dp.tu); 969 if (!r) 970 DRM_DEBUG_KMS("Failed to allocate VCPI\n"); 971 972 if (!mstm->links++) 973 nv50_outp_acquire(mstm->outp, false /*XXX: MST audio.*/); 974 975 if (mstm->outp->link & 1) 976 proto = 0x8; 977 else 978 proto = 0x9; 979 980 mstm->outp->update(mstm->outp, head->base.index, armh, proto, 981 nv50_dp_bpc_to_depth(armh->or.bpc)); 982 983 msto->mstc = mstc; 984 mstm->modified = true; 985 } 986 987 static void 988 nv50_msto_disable(struct drm_encoder *encoder) 989 { 990 struct nv50_msto *msto = nv50_msto(encoder); 991 struct nv50_mstc *mstc = msto->mstc; 992 struct nv50_mstm *mstm = mstc->mstm; 993 994 drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port); 995 996 mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0); 997 mstm->modified = true; 998 if (!--mstm->links) 999 mstm->disabled = true; 1000 msto->disabled = true; 1001 } 1002 1003 static const struct drm_encoder_helper_funcs 1004 nv50_msto_help = { 1005 .disable = nv50_msto_disable, 1006 .enable = nv50_msto_enable, 1007 .atomic_check = nv50_msto_atomic_check, 1008 }; 1009 1010 static void 1011 nv50_msto_destroy(struct drm_encoder *encoder) 1012 { 1013 struct nv50_msto *msto = nv50_msto(encoder); 1014 drm_encoder_cleanup(&msto->encoder); 1015 kfree(msto); 1016 } 1017 1018 static const struct drm_encoder_funcs 1019 nv50_msto = { 1020 .destroy = nv50_msto_destroy, 1021 }; 1022 1023 static struct nv50_msto * 1024 nv50_msto_new(struct drm_device *dev, struct nv50_head *head, int id) 1025 { 1026 struct nv50_msto *msto; 1027 int ret; 1028 1029 msto = kzalloc(sizeof(*msto), GFP_KERNEL); 1030 if (!msto) 1031 return ERR_PTR(-ENOMEM); 1032 1033 ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto, 1034 DRM_MODE_ENCODER_DPMST, "mst-%d", id); 1035 if (ret) { 1036 kfree(msto); 1037 return ERR_PTR(ret); 1038 } 1039 1040 drm_encoder_helper_add(&msto->encoder, &nv50_msto_help); 1041 msto->encoder.possible_crtcs = drm_crtc_mask(&head->base.base); 1042 msto->head = head; 1043 return msto; 1044 } 1045 1046 static struct drm_encoder * 1047 nv50_mstc_atomic_best_encoder(struct drm_connector *connector, 1048 struct drm_connector_state *connector_state) 1049 { 1050 struct nv50_mstc *mstc = nv50_mstc(connector); 1051 struct drm_crtc *crtc = connector_state->crtc; 1052 1053 if (!(mstc->mstm->outp->dcb->heads & drm_crtc_mask(crtc))) 1054 return NULL; 1055 1056 return &nv50_head(crtc)->msto->encoder; 1057 } 1058 1059 static enum drm_mode_status 1060 nv50_mstc_mode_valid(struct drm_connector *connector, 1061 struct drm_display_mode *mode) 1062 { 1063 struct nv50_mstc *mstc = nv50_mstc(connector); 1064 struct nouveau_encoder *outp = mstc->mstm->outp; 1065 1066 /* TODO: calculate the PBN from the dotclock and validate against the 1067 * MSTB's max possible PBN 1068 */ 1069 1070 return nv50_dp_mode_valid(connector, outp, mode, NULL); 1071 } 1072 1073 static int 1074 nv50_mstc_get_modes(struct drm_connector *connector) 1075 { 1076 struct nv50_mstc *mstc = nv50_mstc(connector); 1077 int ret = 0; 1078 1079 mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port); 1080 drm_connector_update_edid_property(&mstc->connector, mstc->edid); 1081 if (mstc->edid) 1082 ret = drm_add_edid_modes(&mstc->connector, mstc->edid); 1083 1084 /* 1085 * XXX: Since we don't use HDR in userspace quite yet, limit the bpc 1086 * to 8 to save bandwidth on the topology. In the future, we'll want 1087 * to properly fix this by dynamically selecting the highest possible 1088 * bpc that would fit in the topology 1089 */ 1090 if (connector->display_info.bpc) 1091 connector->display_info.bpc = 1092 clamp(connector->display_info.bpc, 6U, 8U); 1093 else 1094 connector->display_info.bpc = 8; 1095 1096 if (mstc->native) 1097 drm_mode_destroy(mstc->connector.dev, mstc->native); 1098 mstc->native = nouveau_conn_native_mode(&mstc->connector); 1099 return ret; 1100 } 1101 1102 static int 1103 nv50_mstc_atomic_check(struct drm_connector *connector, 1104 struct drm_atomic_state *state) 1105 { 1106 struct nv50_mstc *mstc = nv50_mstc(connector); 1107 struct drm_dp_mst_topology_mgr *mgr = &mstc->mstm->mgr; 1108 struct drm_connector_state *new_conn_state = 1109 drm_atomic_get_new_connector_state(state, connector); 1110 struct drm_connector_state *old_conn_state = 1111 drm_atomic_get_old_connector_state(state, connector); 1112 struct drm_crtc_state *crtc_state; 1113 struct drm_crtc *new_crtc = new_conn_state->crtc; 1114 1115 if (!old_conn_state->crtc) 1116 return 0; 1117 1118 /* We only want to free VCPI if this state disables the CRTC on this 1119 * connector 1120 */ 1121 if (new_crtc) { 1122 crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc); 1123 1124 if (!crtc_state || 1125 !drm_atomic_crtc_needs_modeset(crtc_state) || 1126 crtc_state->enable) 1127 return 0; 1128 } 1129 1130 return drm_dp_atomic_release_vcpi_slots(state, mgr, mstc->port); 1131 } 1132 1133 static int 1134 nv50_mstc_detect(struct drm_connector *connector, 1135 struct drm_modeset_acquire_ctx *ctx, bool force) 1136 { 1137 struct nv50_mstc *mstc = nv50_mstc(connector); 1138 int ret; 1139 1140 if (drm_connector_is_unregistered(connector)) 1141 return connector_status_disconnected; 1142 1143 ret = pm_runtime_get_sync(connector->dev->dev); 1144 if (ret < 0 && ret != -EACCES) { 1145 pm_runtime_put_autosuspend(connector->dev->dev); 1146 return connector_status_disconnected; 1147 } 1148 1149 ret = drm_dp_mst_detect_port(connector, ctx, mstc->port->mgr, 1150 mstc->port); 1151 1152 pm_runtime_mark_last_busy(connector->dev->dev); 1153 pm_runtime_put_autosuspend(connector->dev->dev); 1154 return ret; 1155 } 1156 1157 static const struct drm_connector_helper_funcs 1158 nv50_mstc_help = { 1159 .get_modes = nv50_mstc_get_modes, 1160 .mode_valid = nv50_mstc_mode_valid, 1161 .atomic_best_encoder = nv50_mstc_atomic_best_encoder, 1162 .atomic_check = nv50_mstc_atomic_check, 1163 .detect_ctx = nv50_mstc_detect, 1164 }; 1165 1166 static void 1167 nv50_mstc_destroy(struct drm_connector *connector) 1168 { 1169 struct nv50_mstc *mstc = nv50_mstc(connector); 1170 1171 drm_connector_cleanup(&mstc->connector); 1172 drm_dp_mst_put_port_malloc(mstc->port); 1173 1174 kfree(mstc); 1175 } 1176 1177 static const struct drm_connector_funcs 1178 nv50_mstc = { 1179 .reset = nouveau_conn_reset, 1180 .fill_modes = drm_helper_probe_single_connector_modes, 1181 .destroy = nv50_mstc_destroy, 1182 .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state, 1183 .atomic_destroy_state = nouveau_conn_atomic_destroy_state, 1184 .atomic_set_property = nouveau_conn_atomic_set_property, 1185 .atomic_get_property = nouveau_conn_atomic_get_property, 1186 }; 1187 1188 static int 1189 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port, 1190 const char *path, struct nv50_mstc **pmstc) 1191 { 1192 struct drm_device *dev = mstm->outp->base.base.dev; 1193 struct drm_crtc *crtc; 1194 struct nv50_mstc *mstc; 1195 int ret; 1196 1197 if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL))) 1198 return -ENOMEM; 1199 mstc->mstm = mstm; 1200 mstc->port = port; 1201 1202 ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc, 1203 DRM_MODE_CONNECTOR_DisplayPort); 1204 if (ret) { 1205 kfree(*pmstc); 1206 *pmstc = NULL; 1207 return ret; 1208 } 1209 1210 drm_connector_helper_add(&mstc->connector, &nv50_mstc_help); 1211 1212 mstc->connector.funcs->reset(&mstc->connector); 1213 nouveau_conn_attach_properties(&mstc->connector); 1214 1215 drm_for_each_crtc(crtc, dev) { 1216 if (!(mstm->outp->dcb->heads & drm_crtc_mask(crtc))) 1217 continue; 1218 1219 drm_connector_attach_encoder(&mstc->connector, 1220 &nv50_head(crtc)->msto->encoder); 1221 } 1222 1223 drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0); 1224 drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0); 1225 drm_connector_set_path_property(&mstc->connector, path); 1226 drm_dp_mst_get_port_malloc(port); 1227 return 0; 1228 } 1229 1230 static void 1231 nv50_mstm_cleanup(struct nv50_mstm *mstm) 1232 { 1233 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev); 1234 struct drm_encoder *encoder; 1235 int ret; 1236 1237 NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name); 1238 ret = drm_dp_check_act_status(&mstm->mgr); 1239 1240 ret = drm_dp_update_payload_part2(&mstm->mgr); 1241 1242 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { 1243 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 1244 struct nv50_msto *msto = nv50_msto(encoder); 1245 struct nv50_mstc *mstc = msto->mstc; 1246 if (mstc && mstc->mstm == mstm) 1247 nv50_msto_cleanup(msto); 1248 } 1249 } 1250 1251 mstm->modified = false; 1252 } 1253 1254 static void 1255 nv50_mstm_prepare(struct nv50_mstm *mstm) 1256 { 1257 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev); 1258 struct drm_encoder *encoder; 1259 int ret; 1260 1261 NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name); 1262 ret = drm_dp_update_payload_part1(&mstm->mgr); 1263 1264 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { 1265 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 1266 struct nv50_msto *msto = nv50_msto(encoder); 1267 struct nv50_mstc *mstc = msto->mstc; 1268 if (mstc && mstc->mstm == mstm) 1269 nv50_msto_prepare(msto); 1270 } 1271 } 1272 1273 if (mstm->disabled) { 1274 if (!mstm->links) 1275 nv50_outp_release(mstm->outp); 1276 mstm->disabled = false; 1277 } 1278 } 1279 1280 static struct drm_connector * 1281 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr, 1282 struct drm_dp_mst_port *port, const char *path) 1283 { 1284 struct nv50_mstm *mstm = nv50_mstm(mgr); 1285 struct nv50_mstc *mstc; 1286 int ret; 1287 1288 ret = nv50_mstc_new(mstm, port, path, &mstc); 1289 if (ret) 1290 return NULL; 1291 1292 return &mstc->connector; 1293 } 1294 1295 static const struct drm_dp_mst_topology_cbs 1296 nv50_mstm = { 1297 .add_connector = nv50_mstm_add_connector, 1298 }; 1299 1300 void 1301 nv50_mstm_service(struct nv50_mstm *mstm) 1302 { 1303 struct drm_dp_aux *aux = mstm ? mstm->mgr.aux : NULL; 1304 bool handled = true; 1305 int ret; 1306 u8 esi[8] = {}; 1307 1308 if (!aux) 1309 return; 1310 1311 while (handled) { 1312 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8); 1313 if (ret != 8) { 1314 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false); 1315 return; 1316 } 1317 1318 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled); 1319 if (!handled) 1320 break; 1321 1322 drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 3); 1323 } 1324 } 1325 1326 void 1327 nv50_mstm_remove(struct nv50_mstm *mstm) 1328 { 1329 if (mstm) 1330 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false); 1331 } 1332 1333 static int 1334 nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state) 1335 { 1336 struct nouveau_encoder *outp = mstm->outp; 1337 struct { 1338 struct nv50_disp_mthd_v1 base; 1339 struct nv50_disp_sor_dp_mst_link_v0 mst; 1340 } args = { 1341 .base.version = 1, 1342 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK, 1343 .base.hasht = outp->dcb->hasht, 1344 .base.hashm = outp->dcb->hashm, 1345 .mst.state = state, 1346 }; 1347 struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev); 1348 struct nvif_object *disp = &drm->display->disp.object; 1349 int ret; 1350 1351 if (dpcd >= 0x12) { 1352 /* Even if we're enabling MST, start with disabling the 1353 * branching unit to clear any sink-side MST topology state 1354 * that wasn't set by us 1355 */ 1356 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, 0); 1357 if (ret < 0) 1358 return ret; 1359 1360 if (state) { 1361 /* Now, start initializing */ 1362 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, 1363 DP_MST_EN); 1364 if (ret < 0) 1365 return ret; 1366 } 1367 } 1368 1369 return nvif_mthd(disp, 0, &args, sizeof(args)); 1370 } 1371 1372 int 1373 nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow) 1374 { 1375 struct drm_dp_aux *aux; 1376 int ret; 1377 bool old_state, new_state; 1378 u8 mstm_ctrl; 1379 1380 if (!mstm) 1381 return 0; 1382 1383 mutex_lock(&mstm->mgr.lock); 1384 1385 old_state = mstm->mgr.mst_state; 1386 new_state = old_state; 1387 aux = mstm->mgr.aux; 1388 1389 if (old_state) { 1390 /* Just check that the MST hub is still as we expect it */ 1391 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CTRL, &mstm_ctrl); 1392 if (ret < 0 || !(mstm_ctrl & DP_MST_EN)) { 1393 DRM_DEBUG_KMS("Hub gone, disabling MST topology\n"); 1394 new_state = false; 1395 } 1396 } else if (dpcd[0] >= 0x12) { 1397 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CAP, &dpcd[1]); 1398 if (ret < 0) 1399 goto probe_error; 1400 1401 if (!(dpcd[1] & DP_MST_CAP)) 1402 dpcd[0] = 0x11; 1403 else 1404 new_state = allow; 1405 } 1406 1407 if (new_state == old_state) { 1408 mutex_unlock(&mstm->mgr.lock); 1409 return new_state; 1410 } 1411 1412 ret = nv50_mstm_enable(mstm, dpcd[0], new_state); 1413 if (ret) 1414 goto probe_error; 1415 1416 mutex_unlock(&mstm->mgr.lock); 1417 1418 ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, new_state); 1419 if (ret) 1420 return nv50_mstm_enable(mstm, dpcd[0], 0); 1421 1422 return new_state; 1423 1424 probe_error: 1425 mutex_unlock(&mstm->mgr.lock); 1426 return ret; 1427 } 1428 1429 static void 1430 nv50_mstm_fini(struct nv50_mstm *mstm) 1431 { 1432 if (mstm && mstm->mgr.mst_state) 1433 drm_dp_mst_topology_mgr_suspend(&mstm->mgr); 1434 } 1435 1436 static void 1437 nv50_mstm_init(struct nv50_mstm *mstm, bool runtime) 1438 { 1439 int ret; 1440 1441 if (!mstm || !mstm->mgr.mst_state) 1442 return; 1443 1444 ret = drm_dp_mst_topology_mgr_resume(&mstm->mgr, !runtime); 1445 if (ret == -1) { 1446 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false); 1447 drm_kms_helper_hotplug_event(mstm->mgr.dev); 1448 } 1449 } 1450 1451 static void 1452 nv50_mstm_del(struct nv50_mstm **pmstm) 1453 { 1454 struct nv50_mstm *mstm = *pmstm; 1455 if (mstm) { 1456 drm_dp_mst_topology_mgr_destroy(&mstm->mgr); 1457 kfree(*pmstm); 1458 *pmstm = NULL; 1459 } 1460 } 1461 1462 static int 1463 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max, 1464 int conn_base_id, struct nv50_mstm **pmstm) 1465 { 1466 const int max_payloads = hweight8(outp->dcb->heads); 1467 struct drm_device *dev = outp->base.base.dev; 1468 struct nv50_mstm *mstm; 1469 int ret; 1470 u8 dpcd; 1471 1472 /* This is a workaround for some monitors not functioning 1473 * correctly in MST mode on initial module load. I think 1474 * some bad interaction with the VBIOS may be responsible. 1475 * 1476 * A good ol' off and on again seems to work here ;) 1477 */ 1478 ret = drm_dp_dpcd_readb(aux, DP_DPCD_REV, &dpcd); 1479 if (ret >= 0 && dpcd >= 0x12) 1480 drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0); 1481 1482 if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL))) 1483 return -ENOMEM; 1484 mstm->outp = outp; 1485 mstm->mgr.cbs = &nv50_mstm; 1486 1487 ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max, 1488 max_payloads, conn_base_id); 1489 if (ret) 1490 return ret; 1491 1492 return 0; 1493 } 1494 1495 /****************************************************************************** 1496 * SOR 1497 *****************************************************************************/ 1498 static void 1499 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head, 1500 struct nv50_head_atom *asyh, u8 proto, u8 depth) 1501 { 1502 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev); 1503 struct nv50_core *core = disp->core; 1504 1505 if (!asyh) { 1506 nv_encoder->ctrl &= ~BIT(head); 1507 if (!(nv_encoder->ctrl & 0x0000000f)) 1508 nv_encoder->ctrl = 0; 1509 } else { 1510 nv_encoder->ctrl |= proto << 8; 1511 nv_encoder->ctrl |= BIT(head); 1512 asyh->or.depth = depth; 1513 } 1514 1515 core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh); 1516 } 1517 1518 static void 1519 nv50_sor_disable(struct drm_encoder *encoder) 1520 { 1521 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1522 struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc); 1523 1524 nv_encoder->crtc = NULL; 1525 1526 if (nv_crtc) { 1527 struct nvkm_i2c_aux *aux = nv_encoder->aux; 1528 u8 pwr; 1529 1530 if (aux) { 1531 int ret = nvkm_rdaux(aux, DP_SET_POWER, &pwr, 1); 1532 if (ret == 0) { 1533 pwr &= ~DP_SET_POWER_MASK; 1534 pwr |= DP_SET_POWER_D3; 1535 nvkm_wraux(aux, DP_SET_POWER, &pwr, 1); 1536 } 1537 } 1538 1539 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0); 1540 nv50_audio_disable(encoder, nv_crtc); 1541 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc); 1542 nv50_outp_release(nv_encoder); 1543 } 1544 } 1545 1546 static void 1547 nv50_sor_enable(struct drm_encoder *encoder) 1548 { 1549 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1550 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 1551 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state); 1552 struct drm_display_mode *mode = &asyh->state.adjusted_mode; 1553 struct { 1554 struct nv50_disp_mthd_v1 base; 1555 struct nv50_disp_sor_lvds_script_v0 lvds; 1556 } lvds = { 1557 .base.version = 1, 1558 .base.method = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT, 1559 .base.hasht = nv_encoder->dcb->hasht, 1560 .base.hashm = nv_encoder->dcb->hashm, 1561 }; 1562 struct nv50_disp *disp = nv50_disp(encoder->dev); 1563 struct drm_device *dev = encoder->dev; 1564 struct nouveau_drm *drm = nouveau_drm(dev); 1565 struct nouveau_connector *nv_connector; 1566 struct nvbios *bios = &drm->vbios; 1567 bool hda = false; 1568 u8 proto = 0xf; 1569 u8 depth = 0x0; 1570 1571 nv_connector = nouveau_encoder_connector_get(nv_encoder); 1572 nv_encoder->crtc = encoder->crtc; 1573 1574 if ((disp->disp->object.oclass == GT214_DISP || 1575 disp->disp->object.oclass >= GF110_DISP) && 1576 drm_detect_monitor_audio(nv_connector->edid)) 1577 hda = true; 1578 nv50_outp_acquire(nv_encoder, hda); 1579 1580 switch (nv_encoder->dcb->type) { 1581 case DCB_OUTPUT_TMDS: 1582 if (nv_encoder->link & 1) { 1583 proto = 0x1; 1584 /* Only enable dual-link if: 1585 * - Need to (i.e. rate > 165MHz) 1586 * - DCB says we can 1587 * - Not an HDMI monitor, since there's no dual-link 1588 * on HDMI. 1589 */ 1590 if (mode->clock >= 165000 && 1591 nv_encoder->dcb->duallink_possible && 1592 !drm_detect_hdmi_monitor(nv_connector->edid)) 1593 proto |= 0x4; 1594 } else { 1595 proto = 0x2; 1596 } 1597 1598 nv50_hdmi_enable(&nv_encoder->base.base, mode); 1599 break; 1600 case DCB_OUTPUT_LVDS: 1601 proto = 0x0; 1602 1603 if (bios->fp_no_ddc) { 1604 if (bios->fp.dual_link) 1605 lvds.lvds.script |= 0x0100; 1606 if (bios->fp.if_is_24bit) 1607 lvds.lvds.script |= 0x0200; 1608 } else { 1609 if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) { 1610 if (((u8 *)nv_connector->edid)[121] == 2) 1611 lvds.lvds.script |= 0x0100; 1612 } else 1613 if (mode->clock >= bios->fp.duallink_transition_clk) { 1614 lvds.lvds.script |= 0x0100; 1615 } 1616 1617 if (lvds.lvds.script & 0x0100) { 1618 if (bios->fp.strapless_is_24bit & 2) 1619 lvds.lvds.script |= 0x0200; 1620 } else { 1621 if (bios->fp.strapless_is_24bit & 1) 1622 lvds.lvds.script |= 0x0200; 1623 } 1624 1625 if (asyh->or.bpc == 8) 1626 lvds.lvds.script |= 0x0200; 1627 } 1628 1629 nvif_mthd(&disp->disp->object, 0, &lvds, sizeof(lvds)); 1630 break; 1631 case DCB_OUTPUT_DP: 1632 depth = nv50_dp_bpc_to_depth(asyh->or.bpc); 1633 1634 if (nv_encoder->link & 1) 1635 proto = 0x8; 1636 else 1637 proto = 0x9; 1638 1639 nv50_audio_enable(encoder, mode); 1640 break; 1641 default: 1642 BUG(); 1643 break; 1644 } 1645 1646 nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth); 1647 } 1648 1649 static const struct drm_encoder_helper_funcs 1650 nv50_sor_help = { 1651 .atomic_check = nv50_outp_atomic_check, 1652 .enable = nv50_sor_enable, 1653 .disable = nv50_sor_disable, 1654 }; 1655 1656 static void 1657 nv50_sor_destroy(struct drm_encoder *encoder) 1658 { 1659 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1660 nv50_mstm_del(&nv_encoder->dp.mstm); 1661 drm_encoder_cleanup(encoder); 1662 kfree(encoder); 1663 } 1664 1665 static const struct drm_encoder_funcs 1666 nv50_sor_func = { 1667 .destroy = nv50_sor_destroy, 1668 }; 1669 1670 static bool nv50_has_mst(struct nouveau_drm *drm) 1671 { 1672 struct nvkm_bios *bios = nvxx_bios(&drm->client.device); 1673 u32 data; 1674 u8 ver, hdr, cnt, len; 1675 1676 data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len); 1677 return data && ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04); 1678 } 1679 1680 static int 1681 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe) 1682 { 1683 struct nouveau_connector *nv_connector = nouveau_connector(connector); 1684 struct nouveau_drm *drm = nouveau_drm(connector->dev); 1685 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 1686 struct nouveau_encoder *nv_encoder; 1687 struct drm_encoder *encoder; 1688 struct nv50_disp *disp = nv50_disp(connector->dev); 1689 int type, ret; 1690 1691 switch (dcbe->type) { 1692 case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break; 1693 case DCB_OUTPUT_TMDS: 1694 case DCB_OUTPUT_DP: 1695 default: 1696 type = DRM_MODE_ENCODER_TMDS; 1697 break; 1698 } 1699 1700 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 1701 if (!nv_encoder) 1702 return -ENOMEM; 1703 nv_encoder->dcb = dcbe; 1704 nv_encoder->update = nv50_sor_update; 1705 1706 encoder = to_drm_encoder(nv_encoder); 1707 encoder->possible_crtcs = dcbe->heads; 1708 encoder->possible_clones = 0; 1709 drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type, 1710 "sor-%04x-%04x", dcbe->hasht, dcbe->hashm); 1711 drm_encoder_helper_add(encoder, &nv50_sor_help); 1712 1713 drm_connector_attach_encoder(connector, encoder); 1714 1715 disp->core->func->sor->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1); 1716 1717 if (dcbe->type == DCB_OUTPUT_DP) { 1718 struct nvkm_i2c_aux *aux = 1719 nvkm_i2c_aux_find(i2c, dcbe->i2c_index); 1720 1721 if (aux) { 1722 if (disp->disp->object.oclass < GF110_DISP) { 1723 /* HW has no support for address-only 1724 * transactions, so we're required to 1725 * use custom I2C-over-AUX code. 1726 */ 1727 nv_encoder->i2c = &aux->i2c; 1728 } else { 1729 nv_encoder->i2c = &nv_connector->aux.ddc; 1730 } 1731 nv_encoder->aux = aux; 1732 } 1733 1734 if (nv_connector->type != DCB_CONNECTOR_eDP && 1735 nv50_has_mst(drm)) { 1736 ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 1737 16, nv_connector->base.base.id, 1738 &nv_encoder->dp.mstm); 1739 if (ret) 1740 return ret; 1741 } 1742 } else { 1743 struct nvkm_i2c_bus *bus = 1744 nvkm_i2c_bus_find(i2c, dcbe->i2c_index); 1745 if (bus) 1746 nv_encoder->i2c = &bus->i2c; 1747 } 1748 1749 return 0; 1750 } 1751 1752 /****************************************************************************** 1753 * PIOR 1754 *****************************************************************************/ 1755 static int 1756 nv50_pior_atomic_check(struct drm_encoder *encoder, 1757 struct drm_crtc_state *crtc_state, 1758 struct drm_connector_state *conn_state) 1759 { 1760 int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state); 1761 if (ret) 1762 return ret; 1763 crtc_state->adjusted_mode.clock *= 2; 1764 return 0; 1765 } 1766 1767 static void 1768 nv50_pior_disable(struct drm_encoder *encoder) 1769 { 1770 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1771 struct nv50_core *core = nv50_disp(encoder->dev)->core; 1772 if (nv_encoder->crtc) 1773 core->func->pior->ctrl(core, nv_encoder->or, 0x00000000, NULL); 1774 nv_encoder->crtc = NULL; 1775 nv50_outp_release(nv_encoder); 1776 } 1777 1778 static void 1779 nv50_pior_enable(struct drm_encoder *encoder) 1780 { 1781 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1782 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 1783 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state); 1784 struct nv50_core *core = nv50_disp(encoder->dev)->core; 1785 u8 owner = 1 << nv_crtc->index; 1786 u8 proto; 1787 1788 nv50_outp_acquire(nv_encoder, false); 1789 1790 switch (asyh->or.bpc) { 1791 case 10: asyh->or.depth = 0x6; break; 1792 case 8: asyh->or.depth = 0x5; break; 1793 case 6: asyh->or.depth = 0x2; break; 1794 default: asyh->or.depth = 0x0; break; 1795 } 1796 1797 switch (nv_encoder->dcb->type) { 1798 case DCB_OUTPUT_TMDS: 1799 case DCB_OUTPUT_DP: 1800 proto = 0x0; 1801 break; 1802 default: 1803 BUG(); 1804 break; 1805 } 1806 1807 core->func->pior->ctrl(core, nv_encoder->or, (proto << 8) | owner, asyh); 1808 nv_encoder->crtc = encoder->crtc; 1809 } 1810 1811 static const struct drm_encoder_helper_funcs 1812 nv50_pior_help = { 1813 .atomic_check = nv50_pior_atomic_check, 1814 .enable = nv50_pior_enable, 1815 .disable = nv50_pior_disable, 1816 }; 1817 1818 static void 1819 nv50_pior_destroy(struct drm_encoder *encoder) 1820 { 1821 drm_encoder_cleanup(encoder); 1822 kfree(encoder); 1823 } 1824 1825 static const struct drm_encoder_funcs 1826 nv50_pior_func = { 1827 .destroy = nv50_pior_destroy, 1828 }; 1829 1830 static int 1831 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe) 1832 { 1833 struct drm_device *dev = connector->dev; 1834 struct nouveau_drm *drm = nouveau_drm(dev); 1835 struct nv50_disp *disp = nv50_disp(dev); 1836 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 1837 struct nvkm_i2c_bus *bus = NULL; 1838 struct nvkm_i2c_aux *aux = NULL; 1839 struct i2c_adapter *ddc; 1840 struct nouveau_encoder *nv_encoder; 1841 struct drm_encoder *encoder; 1842 int type; 1843 1844 switch (dcbe->type) { 1845 case DCB_OUTPUT_TMDS: 1846 bus = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev)); 1847 ddc = bus ? &bus->i2c : NULL; 1848 type = DRM_MODE_ENCODER_TMDS; 1849 break; 1850 case DCB_OUTPUT_DP: 1851 aux = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev)); 1852 ddc = aux ? &aux->i2c : NULL; 1853 type = DRM_MODE_ENCODER_TMDS; 1854 break; 1855 default: 1856 return -ENODEV; 1857 } 1858 1859 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 1860 if (!nv_encoder) 1861 return -ENOMEM; 1862 nv_encoder->dcb = dcbe; 1863 nv_encoder->i2c = ddc; 1864 nv_encoder->aux = aux; 1865 1866 encoder = to_drm_encoder(nv_encoder); 1867 encoder->possible_crtcs = dcbe->heads; 1868 encoder->possible_clones = 0; 1869 drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type, 1870 "pior-%04x-%04x", dcbe->hasht, dcbe->hashm); 1871 drm_encoder_helper_add(encoder, &nv50_pior_help); 1872 1873 drm_connector_attach_encoder(connector, encoder); 1874 1875 disp->core->func->pior->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1); 1876 1877 return 0; 1878 } 1879 1880 /****************************************************************************** 1881 * Atomic 1882 *****************************************************************************/ 1883 1884 static void 1885 nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock) 1886 { 1887 struct nouveau_drm *drm = nouveau_drm(state->dev); 1888 struct nv50_disp *disp = nv50_disp(drm->dev); 1889 struct nv50_core *core = disp->core; 1890 struct nv50_mstm *mstm; 1891 struct drm_encoder *encoder; 1892 1893 NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]); 1894 1895 drm_for_each_encoder(encoder, drm->dev) { 1896 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 1897 mstm = nouveau_encoder(encoder)->dp.mstm; 1898 if (mstm && mstm->modified) 1899 nv50_mstm_prepare(mstm); 1900 } 1901 } 1902 1903 core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY); 1904 core->func->update(core, interlock, true); 1905 if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY, 1906 disp->core->chan.base.device)) 1907 NV_ERROR(drm, "core notifier timeout\n"); 1908 1909 drm_for_each_encoder(encoder, drm->dev) { 1910 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 1911 mstm = nouveau_encoder(encoder)->dp.mstm; 1912 if (mstm && mstm->modified) 1913 nv50_mstm_cleanup(mstm); 1914 } 1915 } 1916 } 1917 1918 static void 1919 nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock) 1920 { 1921 struct drm_plane_state *new_plane_state; 1922 struct drm_plane *plane; 1923 int i; 1924 1925 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 1926 struct nv50_wndw *wndw = nv50_wndw(plane); 1927 if (interlock[wndw->interlock.type] & wndw->interlock.data) { 1928 if (wndw->func->update) 1929 wndw->func->update(wndw, interlock); 1930 } 1931 } 1932 } 1933 1934 static void 1935 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state) 1936 { 1937 struct drm_device *dev = state->dev; 1938 struct drm_crtc_state *new_crtc_state, *old_crtc_state; 1939 struct drm_crtc *crtc; 1940 struct drm_plane_state *new_plane_state; 1941 struct drm_plane *plane; 1942 struct nouveau_drm *drm = nouveau_drm(dev); 1943 struct nv50_disp *disp = nv50_disp(dev); 1944 struct nv50_atom *atom = nv50_atom(state); 1945 struct nv50_core *core = disp->core; 1946 struct nv50_outp_atom *outp, *outt; 1947 u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {}; 1948 int i; 1949 bool flushed = false; 1950 1951 NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable); 1952 nv50_crc_atomic_stop_reporting(state); 1953 drm_atomic_helper_wait_for_fences(dev, state, false); 1954 drm_atomic_helper_wait_for_dependencies(state); 1955 drm_atomic_helper_update_legacy_modeset_state(dev, state); 1956 1957 if (atom->lock_core) 1958 mutex_lock(&disp->mutex); 1959 1960 /* Disable head(s). */ 1961 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 1962 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); 1963 struct nv50_head *head = nv50_head(crtc); 1964 1965 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name, 1966 asyh->clr.mask, asyh->set.mask); 1967 1968 if (old_crtc_state->active && !new_crtc_state->active) { 1969 pm_runtime_put_noidle(dev->dev); 1970 drm_crtc_vblank_off(crtc); 1971 } 1972 1973 if (asyh->clr.mask) { 1974 nv50_head_flush_clr(head, asyh, atom->flush_disable); 1975 interlock[NV50_DISP_INTERLOCK_CORE] |= 1; 1976 } 1977 } 1978 1979 /* Disable plane(s). */ 1980 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 1981 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 1982 struct nv50_wndw *wndw = nv50_wndw(plane); 1983 1984 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name, 1985 asyw->clr.mask, asyw->set.mask); 1986 if (!asyw->clr.mask) 1987 continue; 1988 1989 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw); 1990 } 1991 1992 /* Disable output path(s). */ 1993 list_for_each_entry(outp, &atom->outp, head) { 1994 const struct drm_encoder_helper_funcs *help; 1995 struct drm_encoder *encoder; 1996 1997 encoder = outp->encoder; 1998 help = encoder->helper_private; 1999 2000 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name, 2001 outp->clr.mask, outp->set.mask); 2002 2003 if (outp->clr.mask) { 2004 help->disable(encoder); 2005 interlock[NV50_DISP_INTERLOCK_CORE] |= 1; 2006 if (outp->flush_disable) { 2007 nv50_disp_atomic_commit_wndw(state, interlock); 2008 nv50_disp_atomic_commit_core(state, interlock); 2009 memset(interlock, 0x00, sizeof(interlock)); 2010 2011 flushed = true; 2012 } 2013 } 2014 } 2015 2016 /* Flush disable. */ 2017 if (interlock[NV50_DISP_INTERLOCK_CORE]) { 2018 if (atom->flush_disable) { 2019 nv50_disp_atomic_commit_wndw(state, interlock); 2020 nv50_disp_atomic_commit_core(state, interlock); 2021 memset(interlock, 0x00, sizeof(interlock)); 2022 2023 flushed = true; 2024 } 2025 } 2026 2027 if (flushed) 2028 nv50_crc_atomic_release_notifier_contexts(state); 2029 nv50_crc_atomic_init_notifier_contexts(state); 2030 2031 /* Update output path(s). */ 2032 list_for_each_entry_safe(outp, outt, &atom->outp, head) { 2033 const struct drm_encoder_helper_funcs *help; 2034 struct drm_encoder *encoder; 2035 2036 encoder = outp->encoder; 2037 help = encoder->helper_private; 2038 2039 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name, 2040 outp->set.mask, outp->clr.mask); 2041 2042 if (outp->set.mask) { 2043 help->enable(encoder); 2044 interlock[NV50_DISP_INTERLOCK_CORE] = 1; 2045 } 2046 2047 list_del(&outp->head); 2048 kfree(outp); 2049 } 2050 2051 /* Update head(s). */ 2052 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 2053 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); 2054 struct nv50_head *head = nv50_head(crtc); 2055 2056 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name, 2057 asyh->set.mask, asyh->clr.mask); 2058 2059 if (asyh->set.mask) { 2060 nv50_head_flush_set(head, asyh); 2061 interlock[NV50_DISP_INTERLOCK_CORE] = 1; 2062 } 2063 2064 if (new_crtc_state->active) { 2065 if (!old_crtc_state->active) { 2066 drm_crtc_vblank_on(crtc); 2067 pm_runtime_get_noresume(dev->dev); 2068 } 2069 if (new_crtc_state->event) 2070 drm_crtc_vblank_get(crtc); 2071 } 2072 } 2073 2074 /* Update window->head assignment. 2075 * 2076 * This has to happen in an update that's not interlocked with 2077 * any window channels to avoid hitting HW error checks. 2078 * 2079 *TODO: Proper handling of window ownership (Turing apparently 2080 * supports non-fixed mappings). 2081 */ 2082 if (core->assign_windows) { 2083 core->func->wndw.owner(core); 2084 core->func->update(core, interlock, false); 2085 core->assign_windows = false; 2086 interlock[NV50_DISP_INTERLOCK_CORE] = 0; 2087 } 2088 2089 /* Update plane(s). */ 2090 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2091 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 2092 struct nv50_wndw *wndw = nv50_wndw(plane); 2093 2094 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name, 2095 asyw->set.mask, asyw->clr.mask); 2096 if ( !asyw->set.mask && 2097 (!asyw->clr.mask || atom->flush_disable)) 2098 continue; 2099 2100 nv50_wndw_flush_set(wndw, interlock, asyw); 2101 } 2102 2103 /* Flush update. */ 2104 nv50_disp_atomic_commit_wndw(state, interlock); 2105 2106 if (interlock[NV50_DISP_INTERLOCK_CORE]) { 2107 if (interlock[NV50_DISP_INTERLOCK_BASE] || 2108 interlock[NV50_DISP_INTERLOCK_OVLY] || 2109 interlock[NV50_DISP_INTERLOCK_WNDW] || 2110 !atom->state.legacy_cursor_update) 2111 nv50_disp_atomic_commit_core(state, interlock); 2112 else 2113 disp->core->func->update(disp->core, interlock, false); 2114 } 2115 2116 if (atom->lock_core) 2117 mutex_unlock(&disp->mutex); 2118 2119 /* Wait for HW to signal completion. */ 2120 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2121 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 2122 struct nv50_wndw *wndw = nv50_wndw(plane); 2123 int ret = nv50_wndw_wait_armed(wndw, asyw); 2124 if (ret) 2125 NV_ERROR(drm, "%s: timeout\n", plane->name); 2126 } 2127 2128 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 2129 if (new_crtc_state->event) { 2130 unsigned long flags; 2131 /* Get correct count/ts if racing with vblank irq */ 2132 if (new_crtc_state->active) 2133 drm_crtc_accurate_vblank_count(crtc); 2134 spin_lock_irqsave(&crtc->dev->event_lock, flags); 2135 drm_crtc_send_vblank_event(crtc, new_crtc_state->event); 2136 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 2137 2138 new_crtc_state->event = NULL; 2139 if (new_crtc_state->active) 2140 drm_crtc_vblank_put(crtc); 2141 } 2142 } 2143 2144 nv50_crc_atomic_start_reporting(state); 2145 if (!flushed) 2146 nv50_crc_atomic_release_notifier_contexts(state); 2147 drm_atomic_helper_commit_hw_done(state); 2148 drm_atomic_helper_cleanup_planes(dev, state); 2149 drm_atomic_helper_commit_cleanup_done(state); 2150 drm_atomic_state_put(state); 2151 2152 /* Drop the RPM ref we got from nv50_disp_atomic_commit() */ 2153 pm_runtime_mark_last_busy(dev->dev); 2154 pm_runtime_put_autosuspend(dev->dev); 2155 } 2156 2157 static void 2158 nv50_disp_atomic_commit_work(struct work_struct *work) 2159 { 2160 struct drm_atomic_state *state = 2161 container_of(work, typeof(*state), commit_work); 2162 nv50_disp_atomic_commit_tail(state); 2163 } 2164 2165 static int 2166 nv50_disp_atomic_commit(struct drm_device *dev, 2167 struct drm_atomic_state *state, bool nonblock) 2168 { 2169 struct drm_plane_state *new_plane_state; 2170 struct drm_plane *plane; 2171 int ret, i; 2172 2173 ret = pm_runtime_get_sync(dev->dev); 2174 if (ret < 0 && ret != -EACCES) 2175 return ret; 2176 2177 ret = drm_atomic_helper_setup_commit(state, nonblock); 2178 if (ret) 2179 goto done; 2180 2181 INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work); 2182 2183 ret = drm_atomic_helper_prepare_planes(dev, state); 2184 if (ret) 2185 goto done; 2186 2187 if (!nonblock) { 2188 ret = drm_atomic_helper_wait_for_fences(dev, state, true); 2189 if (ret) 2190 goto err_cleanup; 2191 } 2192 2193 ret = drm_atomic_helper_swap_state(state, true); 2194 if (ret) 2195 goto err_cleanup; 2196 2197 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2198 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 2199 struct nv50_wndw *wndw = nv50_wndw(plane); 2200 2201 if (asyw->set.image) 2202 nv50_wndw_ntfy_enable(wndw, asyw); 2203 } 2204 2205 drm_atomic_state_get(state); 2206 2207 /* 2208 * Grab another RPM ref for the commit tail, which will release the 2209 * ref when it's finished 2210 */ 2211 pm_runtime_get_noresume(dev->dev); 2212 2213 if (nonblock) 2214 queue_work(system_unbound_wq, &state->commit_work); 2215 else 2216 nv50_disp_atomic_commit_tail(state); 2217 2218 err_cleanup: 2219 if (ret) 2220 drm_atomic_helper_cleanup_planes(dev, state); 2221 done: 2222 pm_runtime_put_autosuspend(dev->dev); 2223 return ret; 2224 } 2225 2226 static struct nv50_outp_atom * 2227 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder) 2228 { 2229 struct nv50_outp_atom *outp; 2230 2231 list_for_each_entry(outp, &atom->outp, head) { 2232 if (outp->encoder == encoder) 2233 return outp; 2234 } 2235 2236 outp = kzalloc(sizeof(*outp), GFP_KERNEL); 2237 if (!outp) 2238 return ERR_PTR(-ENOMEM); 2239 2240 list_add(&outp->head, &atom->outp); 2241 outp->encoder = encoder; 2242 return outp; 2243 } 2244 2245 static int 2246 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom, 2247 struct drm_connector_state *old_connector_state) 2248 { 2249 struct drm_encoder *encoder = old_connector_state->best_encoder; 2250 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 2251 struct drm_crtc *crtc; 2252 struct nv50_outp_atom *outp; 2253 2254 if (!(crtc = old_connector_state->crtc)) 2255 return 0; 2256 2257 old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc); 2258 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc); 2259 if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) { 2260 outp = nv50_disp_outp_atomic_add(atom, encoder); 2261 if (IS_ERR(outp)) 2262 return PTR_ERR(outp); 2263 2264 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 2265 outp->flush_disable = true; 2266 atom->flush_disable = true; 2267 } 2268 outp->clr.ctrl = true; 2269 atom->lock_core = true; 2270 } 2271 2272 return 0; 2273 } 2274 2275 static int 2276 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom, 2277 struct drm_connector_state *connector_state) 2278 { 2279 struct drm_encoder *encoder = connector_state->best_encoder; 2280 struct drm_crtc_state *new_crtc_state; 2281 struct drm_crtc *crtc; 2282 struct nv50_outp_atom *outp; 2283 2284 if (!(crtc = connector_state->crtc)) 2285 return 0; 2286 2287 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc); 2288 if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) { 2289 outp = nv50_disp_outp_atomic_add(atom, encoder); 2290 if (IS_ERR(outp)) 2291 return PTR_ERR(outp); 2292 2293 outp->set.ctrl = true; 2294 atom->lock_core = true; 2295 } 2296 2297 return 0; 2298 } 2299 2300 static int 2301 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) 2302 { 2303 struct nv50_atom *atom = nv50_atom(state); 2304 struct nv50_core *core = nv50_disp(dev)->core; 2305 struct drm_connector_state *old_connector_state, *new_connector_state; 2306 struct drm_connector *connector; 2307 struct drm_crtc_state *new_crtc_state; 2308 struct drm_crtc *crtc; 2309 struct nv50_head *head; 2310 struct nv50_head_atom *asyh; 2311 int ret, i; 2312 2313 if (core->assign_windows && core->func->head->static_wndw_map) { 2314 drm_for_each_crtc(crtc, dev) { 2315 new_crtc_state = drm_atomic_get_crtc_state(state, 2316 crtc); 2317 if (IS_ERR(new_crtc_state)) 2318 return PTR_ERR(new_crtc_state); 2319 2320 head = nv50_head(crtc); 2321 asyh = nv50_head_atom(new_crtc_state); 2322 core->func->head->static_wndw_map(head, asyh); 2323 } 2324 } 2325 2326 /* We need to handle colour management on a per-plane basis. */ 2327 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 2328 if (new_crtc_state->color_mgmt_changed) { 2329 ret = drm_atomic_add_affected_planes(state, crtc); 2330 if (ret) 2331 return ret; 2332 } 2333 } 2334 2335 ret = drm_atomic_helper_check(dev, state); 2336 if (ret) 2337 return ret; 2338 2339 for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) { 2340 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state); 2341 if (ret) 2342 return ret; 2343 2344 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state); 2345 if (ret) 2346 return ret; 2347 } 2348 2349 ret = drm_dp_mst_atomic_check(state); 2350 if (ret) 2351 return ret; 2352 2353 nv50_crc_atomic_check_outp(atom); 2354 2355 return 0; 2356 } 2357 2358 static void 2359 nv50_disp_atomic_state_clear(struct drm_atomic_state *state) 2360 { 2361 struct nv50_atom *atom = nv50_atom(state); 2362 struct nv50_outp_atom *outp, *outt; 2363 2364 list_for_each_entry_safe(outp, outt, &atom->outp, head) { 2365 list_del(&outp->head); 2366 kfree(outp); 2367 } 2368 2369 drm_atomic_state_default_clear(state); 2370 } 2371 2372 static void 2373 nv50_disp_atomic_state_free(struct drm_atomic_state *state) 2374 { 2375 struct nv50_atom *atom = nv50_atom(state); 2376 drm_atomic_state_default_release(&atom->state); 2377 kfree(atom); 2378 } 2379 2380 static struct drm_atomic_state * 2381 nv50_disp_atomic_state_alloc(struct drm_device *dev) 2382 { 2383 struct nv50_atom *atom; 2384 if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) || 2385 drm_atomic_state_init(dev, &atom->state) < 0) { 2386 kfree(atom); 2387 return NULL; 2388 } 2389 INIT_LIST_HEAD(&atom->outp); 2390 return &atom->state; 2391 } 2392 2393 static const struct drm_mode_config_funcs 2394 nv50_disp_func = { 2395 .fb_create = nouveau_user_framebuffer_create, 2396 .output_poll_changed = nouveau_fbcon_output_poll_changed, 2397 .atomic_check = nv50_disp_atomic_check, 2398 .atomic_commit = nv50_disp_atomic_commit, 2399 .atomic_state_alloc = nv50_disp_atomic_state_alloc, 2400 .atomic_state_clear = nv50_disp_atomic_state_clear, 2401 .atomic_state_free = nv50_disp_atomic_state_free, 2402 }; 2403 2404 /****************************************************************************** 2405 * Init 2406 *****************************************************************************/ 2407 2408 static void 2409 nv50_display_fini(struct drm_device *dev, bool suspend) 2410 { 2411 struct nouveau_encoder *nv_encoder; 2412 struct drm_encoder *encoder; 2413 struct drm_plane *plane; 2414 2415 drm_for_each_plane(plane, dev) { 2416 struct nv50_wndw *wndw = nv50_wndw(plane); 2417 if (plane->funcs != &nv50_wndw) 2418 continue; 2419 nv50_wndw_fini(wndw); 2420 } 2421 2422 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2423 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 2424 nv_encoder = nouveau_encoder(encoder); 2425 nv50_mstm_fini(nv_encoder->dp.mstm); 2426 } 2427 } 2428 } 2429 2430 static int 2431 nv50_display_init(struct drm_device *dev, bool resume, bool runtime) 2432 { 2433 struct nv50_core *core = nv50_disp(dev)->core; 2434 struct drm_encoder *encoder; 2435 struct drm_plane *plane; 2436 2437 if (resume || runtime) 2438 core->func->init(core); 2439 2440 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2441 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 2442 struct nouveau_encoder *nv_encoder = 2443 nouveau_encoder(encoder); 2444 nv50_mstm_init(nv_encoder->dp.mstm, runtime); 2445 } 2446 } 2447 2448 drm_for_each_plane(plane, dev) { 2449 struct nv50_wndw *wndw = nv50_wndw(plane); 2450 if (plane->funcs != &nv50_wndw) 2451 continue; 2452 nv50_wndw_init(wndw); 2453 } 2454 2455 return 0; 2456 } 2457 2458 static void 2459 nv50_display_destroy(struct drm_device *dev) 2460 { 2461 struct nv50_disp *disp = nv50_disp(dev); 2462 2463 nv50_audio_component_fini(nouveau_drm(dev)); 2464 2465 nvif_object_unmap(&disp->caps); 2466 nvif_object_fini(&disp->caps); 2467 nv50_core_del(&disp->core); 2468 2469 nouveau_bo_unmap(disp->sync); 2470 if (disp->sync) 2471 nouveau_bo_unpin(disp->sync); 2472 nouveau_bo_ref(NULL, &disp->sync); 2473 2474 nouveau_display(dev)->priv = NULL; 2475 kfree(disp); 2476 } 2477 2478 int 2479 nv50_display_create(struct drm_device *dev) 2480 { 2481 struct nvif_device *device = &nouveau_drm(dev)->client.device; 2482 struct nouveau_drm *drm = nouveau_drm(dev); 2483 struct dcb_table *dcb = &drm->vbios.dcb; 2484 struct drm_connector *connector, *tmp; 2485 struct nv50_disp *disp; 2486 struct dcb_output *dcbe; 2487 int crtcs, ret, i; 2488 bool has_mst = nv50_has_mst(drm); 2489 2490 disp = kzalloc(sizeof(*disp), GFP_KERNEL); 2491 if (!disp) 2492 return -ENOMEM; 2493 2494 mutex_init(&disp->mutex); 2495 2496 nouveau_display(dev)->priv = disp; 2497 nouveau_display(dev)->dtor = nv50_display_destroy; 2498 nouveau_display(dev)->init = nv50_display_init; 2499 nouveau_display(dev)->fini = nv50_display_fini; 2500 disp->disp = &nouveau_display(dev)->disp; 2501 dev->mode_config.funcs = &nv50_disp_func; 2502 dev->mode_config.quirk_addfb_prefer_xbgr_30bpp = true; 2503 dev->mode_config.normalize_zpos = true; 2504 2505 /* small shared memory area we use for notifiers and semaphores */ 2506 ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM, 2507 0, 0x0000, NULL, NULL, &disp->sync); 2508 if (!ret) { 2509 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true); 2510 if (!ret) { 2511 ret = nouveau_bo_map(disp->sync); 2512 if (ret) 2513 nouveau_bo_unpin(disp->sync); 2514 } 2515 if (ret) 2516 nouveau_bo_ref(NULL, &disp->sync); 2517 } 2518 2519 if (ret) 2520 goto out; 2521 2522 /* allocate master evo channel */ 2523 ret = nv50_core_new(drm, &disp->core); 2524 if (ret) 2525 goto out; 2526 2527 disp->core->func->init(disp->core); 2528 if (disp->core->func->caps_init) { 2529 ret = disp->core->func->caps_init(drm, disp); 2530 if (ret) 2531 goto out; 2532 } 2533 2534 /* Assign the correct format modifiers */ 2535 if (disp->disp->object.oclass >= TU102_DISP) 2536 nouveau_display(dev)->format_modifiers = wndwc57e_modifiers; 2537 else 2538 if (disp->disp->object.oclass >= GF110_DISP) 2539 nouveau_display(dev)->format_modifiers = disp90xx_modifiers; 2540 else 2541 nouveau_display(dev)->format_modifiers = disp50xx_modifiers; 2542 2543 /* create crtc objects to represent the hw heads */ 2544 if (disp->disp->object.oclass >= GV100_DISP) 2545 crtcs = nvif_rd32(&device->object, 0x610060) & 0xff; 2546 else 2547 if (disp->disp->object.oclass >= GF110_DISP) 2548 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf; 2549 else 2550 crtcs = 0x3; 2551 2552 for (i = 0; i < fls(crtcs); i++) { 2553 struct nv50_head *head; 2554 2555 if (!(crtcs & (1 << i))) 2556 continue; 2557 2558 head = nv50_head_create(dev, i); 2559 if (IS_ERR(head)) { 2560 ret = PTR_ERR(head); 2561 goto out; 2562 } 2563 2564 if (has_mst) { 2565 head->msto = nv50_msto_new(dev, head, i); 2566 if (IS_ERR(head->msto)) { 2567 ret = PTR_ERR(head->msto); 2568 head->msto = NULL; 2569 goto out; 2570 } 2571 2572 /* 2573 * FIXME: This is a hack to workaround the following 2574 * issues: 2575 * 2576 * https://gitlab.gnome.org/GNOME/mutter/issues/759 2577 * https://gitlab.freedesktop.org/xorg/xserver/merge_requests/277 2578 * 2579 * Once these issues are closed, this should be 2580 * removed 2581 */ 2582 head->msto->encoder.possible_crtcs = crtcs; 2583 } 2584 } 2585 2586 /* create encoder/connector objects based on VBIOS DCB table */ 2587 for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) { 2588 connector = nouveau_connector_create(dev, dcbe); 2589 if (IS_ERR(connector)) 2590 continue; 2591 2592 if (dcbe->location == DCB_LOC_ON_CHIP) { 2593 switch (dcbe->type) { 2594 case DCB_OUTPUT_TMDS: 2595 case DCB_OUTPUT_LVDS: 2596 case DCB_OUTPUT_DP: 2597 ret = nv50_sor_create(connector, dcbe); 2598 break; 2599 case DCB_OUTPUT_ANALOG: 2600 ret = nv50_dac_create(connector, dcbe); 2601 break; 2602 default: 2603 ret = -ENODEV; 2604 break; 2605 } 2606 } else { 2607 ret = nv50_pior_create(connector, dcbe); 2608 } 2609 2610 if (ret) { 2611 NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n", 2612 dcbe->location, dcbe->type, 2613 ffs(dcbe->or) - 1, ret); 2614 ret = 0; 2615 } 2616 } 2617 2618 /* cull any connectors we created that don't have an encoder */ 2619 list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) { 2620 if (connector->possible_encoders) 2621 continue; 2622 2623 NV_WARN(drm, "%s has no encoders, removing\n", 2624 connector->name); 2625 connector->funcs->destroy(connector); 2626 } 2627 2628 /* Disable vblank irqs aggressively for power-saving, safe on nv50+ */ 2629 dev->vblank_disable_immediate = true; 2630 2631 nv50_audio_component_init(drm); 2632 2633 out: 2634 if (ret) 2635 nv50_display_destroy(dev); 2636 return ret; 2637 } 2638 2639 /****************************************************************************** 2640 * Format modifiers 2641 *****************************************************************************/ 2642 2643 /**************************************************************** 2644 * Log2(block height) ----------------------------+ * 2645 * Page Kind ----------------------------------+ | * 2646 * Gob Height/Page Kind Generation ------+ | | * 2647 * Sector layout -------+ | | | * 2648 * Compression ------+ | | | | */ 2649 const u64 disp50xx_modifiers[] = { /* | | | | | */ 2650 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 0), 2651 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 1), 2652 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 2), 2653 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 3), 2654 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 4), 2655 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 5), 2656 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 0), 2657 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 1), 2658 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 2), 2659 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 3), 2660 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 4), 2661 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 5), 2662 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 0), 2663 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 1), 2664 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 2), 2665 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 3), 2666 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 4), 2667 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 5), 2668 DRM_FORMAT_MOD_LINEAR, 2669 DRM_FORMAT_MOD_INVALID 2670 }; 2671 2672 /**************************************************************** 2673 * Log2(block height) ----------------------------+ * 2674 * Page Kind ----------------------------------+ | * 2675 * Gob Height/Page Kind Generation ------+ | | * 2676 * Sector layout -------+ | | | * 2677 * Compression ------+ | | | | */ 2678 const u64 disp90xx_modifiers[] = { /* | | | | | */ 2679 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 0), 2680 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 1), 2681 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 2), 2682 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 3), 2683 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 4), 2684 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 5), 2685 DRM_FORMAT_MOD_LINEAR, 2686 DRM_FORMAT_MOD_INVALID 2687 }; 2688