xref: /linux/drivers/gpu/drm/nouveau/dispnv04/cursor.c (revision 1a6463425552a8b9960e5a19b25421895846925c)
1*1a646342SBen Skeggs #include <drm/drmP.h>
2*1a646342SBen Skeggs #include <drm/drm_mode.h>
3*1a646342SBen Skeggs #include "nouveau_drm.h"
4*1a646342SBen Skeggs #include "nouveau_reg.h"
5*1a646342SBen Skeggs #include "nouveau_crtc.h"
6*1a646342SBen Skeggs #include "hw.h"
7*1a646342SBen Skeggs 
8*1a646342SBen Skeggs static void
9*1a646342SBen Skeggs nv04_cursor_show(struct nouveau_crtc *nv_crtc, bool update)
10*1a646342SBen Skeggs {
11*1a646342SBen Skeggs 	nv_show_cursor(nv_crtc->base.dev, nv_crtc->index, true);
12*1a646342SBen Skeggs }
13*1a646342SBen Skeggs 
14*1a646342SBen Skeggs static void
15*1a646342SBen Skeggs nv04_cursor_hide(struct nouveau_crtc *nv_crtc, bool update)
16*1a646342SBen Skeggs {
17*1a646342SBen Skeggs 	nv_show_cursor(nv_crtc->base.dev, nv_crtc->index, false);
18*1a646342SBen Skeggs }
19*1a646342SBen Skeggs 
20*1a646342SBen Skeggs static void
21*1a646342SBen Skeggs nv04_cursor_set_pos(struct nouveau_crtc *nv_crtc, int x, int y)
22*1a646342SBen Skeggs {
23*1a646342SBen Skeggs 	nv_crtc->cursor_saved_x = x; nv_crtc->cursor_saved_y = y;
24*1a646342SBen Skeggs 	NVWriteRAMDAC(nv_crtc->base.dev, nv_crtc->index,
25*1a646342SBen Skeggs 		      NV_PRAMDAC_CU_START_POS,
26*1a646342SBen Skeggs 		      XLATE(y, 0, NV_PRAMDAC_CU_START_POS_Y) |
27*1a646342SBen Skeggs 		      XLATE(x, 0, NV_PRAMDAC_CU_START_POS_X));
28*1a646342SBen Skeggs }
29*1a646342SBen Skeggs 
30*1a646342SBen Skeggs static void
31*1a646342SBen Skeggs crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index)
32*1a646342SBen Skeggs {
33*1a646342SBen Skeggs 	NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index,
34*1a646342SBen Skeggs 		       crtcstate->CRTC[index]);
35*1a646342SBen Skeggs }
36*1a646342SBen Skeggs 
37*1a646342SBen Skeggs static void
38*1a646342SBen Skeggs nv04_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset)
39*1a646342SBen Skeggs {
40*1a646342SBen Skeggs 	struct drm_device *dev = nv_crtc->base.dev;
41*1a646342SBen Skeggs 	struct nouveau_drm *drm = nouveau_drm(dev);
42*1a646342SBen Skeggs 	struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
43*1a646342SBen Skeggs 	struct drm_crtc *crtc = &nv_crtc->base;
44*1a646342SBen Skeggs 
45*1a646342SBen Skeggs 	regp->CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] =
46*1a646342SBen Skeggs 		MASK(NV_CIO_CRE_HCUR_ASI) |
47*1a646342SBen Skeggs 		XLATE(offset, 17, NV_CIO_CRE_HCUR_ADDR0_ADR);
48*1a646342SBen Skeggs 	regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] =
49*1a646342SBen Skeggs 		XLATE(offset, 11, NV_CIO_CRE_HCUR_ADDR1_ADR);
50*1a646342SBen Skeggs 	if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)
51*1a646342SBen Skeggs 		regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] |=
52*1a646342SBen Skeggs 			MASK(NV_CIO_CRE_HCUR_ADDR1_CUR_DBL);
53*1a646342SBen Skeggs 	regp->CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX] = offset >> 24;
54*1a646342SBen Skeggs 
55*1a646342SBen Skeggs 	crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
56*1a646342SBen Skeggs 	crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
57*1a646342SBen Skeggs 	crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
58*1a646342SBen Skeggs 	if (nv_device(drm->device)->card_type == NV_40)
59*1a646342SBen Skeggs 		nv_fix_nv40_hw_cursor(dev, nv_crtc->index);
60*1a646342SBen Skeggs }
61*1a646342SBen Skeggs 
62*1a646342SBen Skeggs int
63*1a646342SBen Skeggs nv04_cursor_init(struct nouveau_crtc *crtc)
64*1a646342SBen Skeggs {
65*1a646342SBen Skeggs 	crtc->cursor.set_offset = nv04_cursor_set_offset;
66*1a646342SBen Skeggs 	crtc->cursor.set_pos = nv04_cursor_set_pos;
67*1a646342SBen Skeggs 	crtc->cursor.hide = nv04_cursor_hide;
68*1a646342SBen Skeggs 	crtc->cursor.show = nv04_cursor_show;
69*1a646342SBen Skeggs 	return 0;
70*1a646342SBen Skeggs }
71